x86 fixes
Subsystems (4)
Linus,
Please pull the latest x86/urgent Git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-urgent-2024-04-14
# HEAD: 7211274fe0ee352332255e41ab5e628b86e83994 x86/cpu/amd: Move TOPOEXT enablement into the topology parser
Misc x86 fixes:
- Follow up fixes for the BHI mitigations code.
- Fix !SPECULATION_MITIGATIONS bug not turning off mitigations as expected.
- Work around an APIC emulation bug when the kernel is built with Clang and run as a SEV guest.
- Follow up x86 topology fixes.
Note that there's minor cleanups included in the BHI fixes, which we'd normally delay to the next merge window, but the BHI mitigations code is new and will be backported widely, so we thought it would be better to have a unified codebase at this stage. (Let me know if that assumption is wrong and I'll rebase it.)
Thanks,
Ingo
------------------>
Adam Dunlap (1):
x86/apic: Force native_apic_mem_read() to use the MOV instruction
Daniel Sneddon (1):
x86/bugs: Fix return type of spectre_bhi_state()
Ingo Molnar (1):
x86/bugs: Rename various 'ia32_cap' variables to 'x86_arch_cap_msr'
Josh Poimboeuf (6):
x86/bugs: Fix BHI documentation
x86/bugs: Cache the value of MSR_IA32_ARCH_CAPABILITIES
x86/bugs: Fix BHI handling of RRSBA
x86/bugs: Clarify that syscall hardening isn't a BHI mitigation x86/bugs: Remove CONFIG_BHI_MITIGATION_AUTO and spectre_bhi=auto x86/bugs: Replace CONFIG_SPECTRE_BHI_{ON,OFF} with CONFIG_MITIGATION_SPECTRE_BHI
Sean Christopherson (1):
x86/cpu: Actually turn off mitigations by default for SPECULATION_MITIGATIONS=n
Thomas Gleixner (4):
x86/topology: Don't update cpu_possible_map in topo_set_cpuids() x86/cpu/amd: Make the CPUID 0x80000008 parser correct x86/cpu/amd: Make the NODEID_MSR union actually work x86/cpu/amd: Move TOPOEXT enablement into the topology parser
Documentation/admin-guide/hw-vuln/spectre.rst | 22 +++---- Documentation/admin-guide/kernel-parameters.txt | 12 ++-- arch/x86/Kconfig | 22 +------ arch/x86/include/asm/apic.h | 3 +- arch/x86/kernel/apic/apic.c | 6 +- arch/x86/kernel/cpu/amd.c | 15 ----- arch/x86/kernel/cpu/bugs.c | 82 +++++++++++-------------- arch/x86/kernel/cpu/common.c | 48 +++++++-------- arch/x86/kernel/cpu/topology.c | 7 ++- arch/x86/kernel/cpu/topology_amd.c | 51 ++++++++++++--- kernel/cpu.c | 3 +- 11 files changed, 131 insertions(+), 140 deletions(-)
Documentation/admin-guide/hw-vuln/spectre.rst +9 -13
@@ -439,12 +439,12 @@ The possible values in this file are: - System is protected by retpoline * - BHI: BHI_DIS_S - System is protected by BHI_DIS_S - * - BHI: SW loop; KVM SW loop + * - BHI: SW loop, KVM SW loop - System is protected by software clearing sequence - * - BHI: Syscall hardening - - Syscalls are hardened against BHI - * - BHI: Syscall hardening; KVM: SW loop - - System is protected from userspace attacks by syscall hardening; KVM is protected by software clearing sequence + * - BHI: Vulnerable + - System is vulnerable to BHI + * - BHI: Vulnerable, KVM: SW loop + - System is vulnerable; KVM is protected by software clearing sequence Full mitigation might require a microcode update from the CPU vendor. When the necessary microcode is not available, the kernel will
@@ -661,18 +661,14 @@ kernel command line. spectre_bhi= [X86] Control mitigation of Branch History Injection - (BHI) vulnerability. Syscalls are hardened against BHI - regardless of this setting. This setting affects the deployment + (BHI) vulnerability. This setting affects the deployment of the HW BHI control and the SW BHB clearing sequence. on - unconditionally enable. + (default) Enable the HW or SW mitigation as + needed. off - unconditionally disable. - auto - enable if hardware mitigation - control(BHI_DIS_S) is available, otherwise - enable alternate mitigation in KVM. + Disable the mitigation. For spectre_v2_user see Documentation/admin-guide/kernel-parameters.txt
Documentation/admin-guide/kernel-parameters.txt +5 -7
@@ -3444,6 +3444,7 @@ retbleed=off [X86] spec_rstack_overflow=off [X86] spec_store_bypass_disable=off [X86,PPC] + spectre_bhi=off [X86] spectre_v2_user=off [X86] srbds=off [X86,INTEL] ssbd=force-off [ARM64]
@@ -6064,16 +6065,13 @@ See Documentation/admin-guide/laptops/sonypi.rst spectre_bhi= [X86] Control mitigation of Branch History Injection - (BHI) vulnerability. Syscalls are hardened against BHI - reglardless of this setting. This setting affects the + (BHI) vulnerability. This setting affects the deployment of the HW BHI control and the SW BHB clearing sequence. - on - unconditionally enable. - off - unconditionally disable. - auto - (default) enable hardware mitigation - (BHI_DIS_S) if available, otherwise enable - alternate mitigation in KVM. + on - (default) Enable the HW or SW mitigation + as needed. + off - Disable the mitigation. spectre_v2= [X86,EARLY] Control mitigation of Spectre variant 2 (indirect branch speculation) vulnerability.
arch/x86/Kconfig +3 -19
@@ -2633,32 +2633,16 @@ config MITIGATION_RFDS stored in floating point, vector and integer registers. See also <file:Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst> -choice - prompt "Clear branch history" +config MITIGATION_SPECTRE_BHI + bool "Mitigate Spectre-BHB (Branch History Injection)" depends on CPU_SUP_INTEL - default SPECTRE_BHI_ON + default y help Enable BHI mitigations. BHI attacks are a form of Spectre V2 attacks where the branch history buffer is poisoned to speculatively steer indirect branches. See <file:Documentation/admin-guide/hw-vuln/spectre.rst> -config SPECTRE_BHI_ON - bool "on" - help - Equivalent to setting spectre_bhi=on command line parameter. -config SPECTRE_BHI_OFF - bool "off" - help - Equivalent to setting spectre_bhi=off command line parameter. -config SPECTRE_BHI_AUTO - bool "auto" - depends on BROKEN - help - Equivalent to setting spectre_bhi=auto command line parameter. - -endchoice - endif config ARCH_HAS_ADD_PAGES
arch/x86/include/asm/apic.h +2 -1
@@ -13,6 +13,7 @@#include <asm/mpspec.h> #include <asm/msr.h> #include <asm/hardirq.h> +#include <asm/io.h> #define ARCH_APICTIMER_STOPS_ON_C3 1
@@ -98,7 +99,7 @@ static inline void native_apic_mem_write(u32 reg, u32 v)static inline u32 native_apic_mem_read (u32 reg) { -return *((volatile u32 *)(APIC_BASE + reg)); +return readl ((void __iomem *)(APIC_BASE + reg)); }static inline void native_apic_mem_eoi (void )
arch/x86/kernel/apic/apic.c +3 -3
@@ -1687,11 +1687,11 @@ static int x2apic_state;static bool x2apic_hw_locked (void ) { -u64 ia32_cap; +u64 x86_arch_cap_msr;u64 msr; - ia32_cap =x86_read_arch_cap_msr (); -if (ia32_cap &ARCH_CAP_XAPIC_DISABLE ) { + x86_arch_cap_msr =x86_read_arch_cap_msr (); +if (x86_arch_cap_msr &ARCH_CAP_XAPIC_DISABLE ) {rdmsrl (MSR_IA32_XAPIC_DISABLE_STATUS , msr);return (msr &LEGACY_XAPIC_DISABLED ); }
arch/x86/kernel/cpu/amd.c +0 -15
@@ -535,7 +535,6 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)static void early_init_amd (struct cpuinfo_x86 *c) { -u64 value;u32 dummy;if (c->x86 >=0xf )
@@ -603,20 +602,6 @@ static void early_init_amd(struct cpuinfo_x86 *c)early_detect_mem_encrypt (c); -/* Re-enable TopologyExtensions if switched off by BIOS */ -if (c->x86 ==0x15 && - (c->x86_model >=0x10 && c->x86_model <=0x6f ) && - !cpu_has (c,X86_FEATURE_TOPOEXT )) { - -if (msr_set_bit (0xc0011005 ,54 ) >0 ) { -rdmsrl (0xc0011005 , value); -if (value &BIT_64 (54 )) { -set_cpu_cap (c,X86_FEATURE_TOPOEXT ); -pr_info_once (FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n" ); - } - } - } -if (!cpu_has (c,X86_FEATURE_HYPERVISOR ) && !cpu_has (c,X86_FEATURE_IBPB_BRTYPE )) {if (c->x86 ==0x17 &&boot_cpu_has (X86_FEATURE_AMD_IBPB ))setup_force_cpu_cap (X86_FEATURE_IBPB_BRTYPE );
arch/x86/kernel/cpu/bugs.c +36 -46
222 lines not on this page · raw message
arch/x86/kernel/cpu/common.c +24 -24
136 lines not on this page · raw message
arch/x86/kernel/cpu/topology.c +5 -2
@@ -123,7 +123,6 @@ static void topo_set_cpuids(unsigned int cpu, u32 apic_id, u32 acpi_id)early_per_cpu (x86_cpu_to_apicid, cpu) = apic_id;early_per_cpu (x86_cpu_to_acpiid, cpu) = acpi_id;#endif -set_cpu_possible (cpu, true);set_cpu_present (cpu, true); }
@@ -210,7 +209,11 @@ static __init void topo_register_apic(u32 apic_id, u32 acpi_id, bool present) topo_info.nr_disabled_cpus++; } -/* Register present and possible CPUs in the domain maps */ +/* +* Register present and possible CPUs in the domain +* maps. cpu_possible_map will be updated in +* topology_init_possible_cpus() after enumeration is done. +*/ for (dom =TOPO_SMT_DOMAIN ; dom <TOPO_MAX_DOMAIN ; dom++)set_bit (topo_apicid (apic_id, dom), apic_maps[dom].map); }
arch/x86/kernel/cpu/topology_amd.c +42 -9
90 lines not on this page · raw message
kernel/cpu.c +2 -1
@@ -3207,7 +3207,8 @@ enum cpu_mitigations { };static enum cpu_mitigations cpu_mitigations__ro_after_init = -CPU_MITIGATIONS_AUTO ; +IS_ENABLED (CONFIG_SPECULATION_MITIGATIONS ) ?CPU_MITIGATIONS_AUTO : +CPU_MITIGATIONS_OFF ;static int __init mitigations_parse_cmdline (char *arg) {
The pull request you sent on Sun, 14 Apr 2024 11:08:17 +0200:
The pull request you sent on Sun, 14 Apr 2024 11:08:17 +0200:
Quoted 1 line
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.gitx86-urgent-2024-04-14
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/27fd80851dc1e47b2facaa11b5b52c7dbc6b0718
Thank you!
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