PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2
Subsystems (5)
RFC PATCH 1/4 PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2
Link Control and Status Register 2 is not present in current pcie-rockchip.h definitions. Add it in preparation for setting it before Gen2 retraining.
--- drivers/pci/controller/pcie-rockchip.h | 3 +++ 1 file changed, 3 insertions(+)
drivers/pci/controller/pcie-rockchip.h +3 -0
@@ -166,6 +166,9 @@#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) +#define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0) +#define PCIE_RC_CONFIG_LCS_2_TLS_25 BIT(0) +#define PCIE_RC_CONFIG_LCS_2_TLS_50 BIT(1)#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
Signature · 1 line
2.49.0
Quoted 14 lines · Geraldo Nascimento
Link Control and Status Register 2 is not present in current
pcie-rockchip.hdefinitions. Add it in preparation for setting it before Gen2 retraining.Signed-off-by Geraldo Nascimento <[email protected]>--- drivers/pci/controller/pcie-rockchip.h | 3 +++ 1 file changed, 3 insertions(+)drivers/pci/controller/pcie-rockchip.h +0
-0
drivers/pci/controller/pcie-rockchip.h line 171
Quoted 6 lines
drivers/pci/controller/pcie-rockchip.h +3
-0@@ -166,6 +166,9 @@#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) +#define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0) +#define PCIE_RC_CONFIG_LCS_2_TLS_25 BIT(0) +#define PCIE_RC_CONFIG_LCS_2_TLS_50 BIT(1)
This stuff:
#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0)
*Looks* like it might be duplicates of:
#define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ #define PCI_EXP_DEVCTL 0x08 /* Device Control */ #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */ #define PCI_EXP_LNKCTL 0x10 /* Link Control */ #define PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */
where the PCIe Capability is at (PCIE_RC_CONFIG_BASE + 0xc0).
If so, can you please rework these to use the existing PCI_EXP_* definitions, including the fields inside?
Quoted 6 lines
drivers/pci/controller/pcie-rockchip.h +0
-0#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)Signature · 1 line
2.49.0
Quoted 16 lines · Bjorn Helgaas
This stuff:
#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0)*Looks* like it might be duplicates of:
#define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ #define PCI_EXP_DEVCTL 0x08 /* Device Control */ #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */ #define PCI_EXP_LNKCTL 0x10 /* Link Control */ #define PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */
Quoted 4 lines
where the PCIe Capability is at (
PCIE_RC_CONFIG_BASE+0xc0).If so, can you please rework these to use the existing PCI_EXP_* definitions, including the fields inside?
Hi Bjorn,
I'll look into it, good catch indeed.
Thank you for your help!
Geraldo Nascimento
Quoted 9 lines · Bjorn Helgaas
On Sat, Jun 07, 2025 at 08:00:54AM -0300, Geraldo Nascimento wrote:
This stuff:#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0)
Quoted 5 lines
*Looks* like it might be duplicates of:
#define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ #define PCI_EXP_DEVCTL 0x08 /* Device Control */ #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */
Hi again Bjorn,
Your message reminded me of something that may be important.
During my debugging I had the mild impression L0s capability is not being cleared from Link Capabilities Register in the presence of "aspm-no-l0s" DT property.
I can't confirm it right now but I might revisit this later on. From what I've seen it can only be cleared from inside the port init in pcie-rockchip.c and does nothing in present form.
Not a clear, confirmable report but something to watch out for...
Regards,
Geraldo Nascimento
Quoted 8 lines · Geraldo Nascimento
Hi again Bjorn,
Your message reminded me of something that may be important.
During my debugging I had the mild impression L0s capability is not being cleared from Link Capabilities Register in the presence of "aspm-no-l0s" DT property.
Quoted 5 lines
I can't confirm it right now but I might revisit this later on. From what I've seen it can only be cleared from inside the port init in
pcie-rockchip.cand does nothing in present form.Not a clear, confirmable report but something to watch out for...
Not correct. ASPM bit for L0s is being properly cleared according to my printk's.
Should have checked before creating noise. Sorry.
Geraldo Nascimento
Quoted 3 lines
Regards,
Geraldo Nascimento