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linux-next: manual merge of the clk tree with the origin tree

PATCH Mark Brown 1 participant 1 message Nov 13

Subsystems (3)
Linux-next tree Common clk Arm/socfpga clock framework support
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Mark Brown

author maintainer
#0 lore raw

Hi all,

Today's linux-next merge of the clk tree got a conflict in:

drivers/clk/socfpga/clk-agilex5.c

between commit:

4dd10fbbeb9c3 ("treewide: Convert devm_kmalloc() family to the devm_kmalloc_obj() family")

from the origin tree and commit:

a13f8c1e4afca ("clk: socfpga: agilex5: register the SP timer clocks early")

from the clk tree.

I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts.

drivers/clk/socfpga/clk-agilex5.c +0 -0
diff --cc drivers/clk/socfpga/clk-agilex5.c
index 572fbb4192845,50dba11ab45ec..0000000000000
@@@ -486,30 -501,29 +501,28 @@@ static int agilex5_clk_register_pll(con
  	return 0;
  }
  
- static int agilex5_clkmgr_init(struct platform_device *pdev)
+ static struct stratix10_clock_data *agilex5_clk_data;
+ 
+ static struct stratix10_clock_data *agilex5_clk_data_alloc(void __iomem *base)
  {
- 	struct device_node *np = pdev->dev.of_node;
- 	struct device *dev = &pdev->dev;
  	struct stratix10_clock_data *clk_data;
- 	void __iomem *base;
- 	int i, num_clks;
+ 	int i;
  
- 	base = devm_platform_ioremap_resource(pdev, 0);
- 	if (IS_ERR(base))
- 		return PTR_ERR(base);
- 
- 	num_clks = AGILEX5_NUM_CLKS;
- 
- 	clk_data = devm_kzalloc_flex(dev, *clk_data, clk_data.hws, num_clks);
 -	clk_data = kzalloc(struct_size(clk_data, clk_data.hws, AGILEX5_NUM_CLKS),
 -			   GFP_KERNEL);
++	clk_data = kzalloc_flex(*clk_data, clk_data.hws, num_clks);
  	if (!clk_data)
- 		return -ENOMEM;
+ 		return NULL;
  
  	clk_data->base = base;
- 	clk_data->clk_data.num = num_clks;
+ 	clk_data->clk_data.num = AGILEX5_NUM_CLKS;
  
- 	for (i = 0; i < num_clks; i++)
- 		clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
+ 	for (i = 0; i < AGILEX5_NUM_CLKS; i++)
+ 		clk_data->clk_data.hws[i] = ERR_PTR(-EPROBE_DEFER);
  
+ 	return clk_data;
+ }
+ 
+ static void agilex5_clk_register_early(struct stratix10_clock_data *clk_data)
+ {
  	agilex5_clk_register_pll(agilex5_pll_clks, ARRAY_SIZE(agilex5_pll_clks),
  				 clk_data);