85xx: Support for XPedite5200

These 2 patches add support for the XPedite5200 SBC - a MPC8548-based PMC card made by Extreme Engineering Solutions.

The patches require the following 2 patches to be applied first:
- pca953x: Add support for PCA953x I2C gpio devices
- XPedite5370 board support

changes since v1:
- Change alignment by spaces to alignment by tabs
- Fixed typos in host_agent_cfg/io_port_cfg
- Fixed variable declaration in code
- Fixed some lines longer than 80 chars
- Cleaned up environment configuration defines
- Fixed multiline comment style

changes since v2:
- Removed CONFIG_L1_INIT_RAM reference

Best,
Peter

Peter Tyser (2):
85xx: Add PORDEVSR_PCI1 define
XPedite5200 board support

 MAINTAINERS                         |    1 +
 MAKEALL                             |    1 +
 Makefile                            |    3 +
 board/xes/common/Makefile           |    3 +-
 board/xes/common/actl_nand.c        |   65 ++++
 board/xes/common/fsl_85xx_pci.c     |  103 +++++++-
 board/xes/xpedite5200/Makefile      |   55 ++++
 board/xes/xpedite5200/config.mk     |   34 +++
 board/xes/xpedite5200/ddr.c         |   91 ++++++
 board/xes/xpedite5200/law.c         |   51 ++++
 board/xes/xpedite5200/tlb.c         |   85 ++++++
 board/xes/xpedite5200/u-boot.lds    |  145 +++++++++
 board/xes/xpedite5200/xpedite5200.c |  125 ++++++++
 include/asm-ppc/immap_85xx.h        |    1 +
 include/configs/XPEDITE5200.h       |  546 +++++++++++++++++++++++++++++++++++
 15 files changed, 1304 insertions(+), 5 deletions(-)
 create mode 100644 board/xes/common/actl_nand.c
 create mode 100644 board/xes/xpedite5200/Makefile
 create mode 100644 board/xes/xpedite5200/config.mk
 create mode 100644 board/xes/xpedite5200/ddr.c
 create mode 100644 board/xes/xpedite5200/law.c
 create mode 100644 board/xes/xpedite5200/tlb.c
 create mode 100644 board/xes/xpedite5200/u-boot.lds
 create mode 100644 board/xes/xpedite5200/xpedite5200.c
 create mode 100644 include/configs/XPEDITE5200.h

Add define used to determine if PCI1 interface is in PCI or PCIX mode.

---
 include/asm-ppc/immap_85xx.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

index 75b451d..cb6e3d8 100644
@@ -1569,6 +1569,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL   0x38000000
+#define MPC85xx_PORDEVSR_PCI1		0x00800000
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000

1.6.0.2.GIT

Initial support for Extreme Engineering Solutions XPedite5200 - a MPC8548-based PMC single board computer.

---
 MAINTAINERS                         |    1 +
 MAKEALL                             |    1 +
 Makefile                            |    3 +
 board/xes/common/Makefile           |    3 +-
 board/xes/common/actl_nand.c        |   65 ++++
 board/xes/common/fsl_85xx_pci.c     |  103 +++++++-
 board/xes/xpedite5200/Makefile      |   55 ++++
 board/xes/xpedite5200/config.mk     |   34 +++
 board/xes/xpedite5200/ddr.c         |   91 ++++++
 board/xes/xpedite5200/law.c         |   51 ++++
 board/xes/xpedite5200/tlb.c         |   85 ++++++
 board/xes/xpedite5200/u-boot.lds    |  145 +++++++++
 board/xes/xpedite5200/xpedite5200.c |  125 ++++++++
 include/configs/XPEDITE5200.h       |  546 +++++++++++++++++++++++++++++++++++
 14 files changed, 1303 insertions(+), 5 deletions(-)
 create mode 100644 board/xes/common/actl_nand.c
 create mode 100644 board/xes/xpedite5200/Makefile
 create mode 100644 board/xes/xpedite5200/config.mk
 create mode 100644 board/xes/xpedite5200/ddr.c
 create mode 100644 board/xes/xpedite5200/law.c
 create mode 100644 board/xes/xpedite5200/tlb.c
 create mode 100644 board/xes/xpedite5200/u-boot.lds
 create mode 100644 board/xes/xpedite5200/xpedite5200.c
 create mode 100644 include/configs/XPEDITE5200.h

index ee98824..551f370 100644
@@ -413,6 +413,7 @@ Rune Torgersen <[email protected]>
 
 Peter Tyser <[email protected]>
 
+	XPEDITE5200	MPC8548
 	XPEDITE5370	MPC8572
 
 David Updegraff <[email protected]>

index 1328514..216e4cd 100755
@@ -376,6 +376,7 @@ LIST_85xx="		\
 	TQM8548		\
 	TQM8555		\
 	TQM8560		\
+	XPEDITE5200	\
 	XPEDITE5370	\
 "
 

index ae3ec22..20e6954 100644
@@ -2454,6 +2454,9 @@ TQM8560_config:		unconfig
 	echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
 	@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
 
+XPEDITE5200_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
+
 XPEDITE5370_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
 

index c5cd633..e7620f4 100644
@@ -29,9 +29,10 @@ endif
 
 LIB	= $(obj)lib$(VENDOR).a
 
+COBJS-$(CONFIG_FSL_PCI_INIT)	+= fsl_85xx_pci.o
 COBJS-$(CONFIG_MPC8572)		+= fsl_8572_clk.o
 COBJS-$(CONFIG_MPC85xx)		+= fsl_85xx_ddr.o
-COBJS-$(CONFIG_FSL_PCI_INIT)	+= fsl_85xx_pci.o
+COBJS-$(CONFIG_NAND_ACTL)	+= actl_nand.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))

new file mode 100644
index 0000000..be5a5c3
@@ -0,0 +1,34 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# xpedite5200 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
+PLATFORM_CPPFLAGS += -mrelocatable

1.6.0.2.GIT

Which define are you referring to? A quick glance looks like these 3 defines are used legitimately. Am I missing something?

If a define should be removed, would it be possible to accept these patches? After they are accepted I'd be happy to submit another patch to clean up the defines for all boards. The boards I've used as references have the similar defines which should also be cleaned up.

Thanks for the feedback,
Peter

Double *sigh*...

I clearly didn't drink enough over the holidays (here).

Ignore me.

Sorry,
jdl

Hi,

I have tried modifying the Start.s of uboot as mentioned below. When I try to link I get an error "`.bootpg' can't be allocated in segment 1".
Can someone guide me on this. I am also attaching the start.o and the linker script that I am using along with this mail.

When I see the dump of start.o I find that it occupies space around 0x1c0, let say max 0x200.
But why then I get this error as this is less than the 4K page mapped. Should I change anything let me know.

Start.S
=========
#----------------------------------------------------------
# Header File for Various constants Related to 85xx
#----------------------------------------------------------
#include "init85xx.h"

.section .bootpg,"ax"

	.globl _start_e500

_start_e500:

	#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
	# setup ccsrbar
	bl      setup_ccsrbar
	#endif

	/* create a temp mapping in AS=1 to the CCSRBAR */
	lis %r6, 0x100c0000 at h
	ori %r6, %r6, 0x100c0000 at l
	lis %r7, 0xC0000500 at h
	ori %r7, %r7, 0xC0000500 at l
	lis %r8, 0xE0000008 at h
	ori %r8, %r8, 0xE0000008 at l
	lis %r9, 0xE0000015 at h
	ori %r9, %r9, 0xE0000015 at l
	
	mtspr   MAS0,%r6
	mtspr   MAS1,%r7
	mtspr   MAS2,%r8
	mtspr   MAS3,%r9
	isync
	msync
	tlbwe
	tlbre
	
	/* clear registers/arrays not reset by hardware */
	
	/* L1 */
	li	%r0,2
	mtspr	L1CSR0,%r0	/* invalidate d-cache */
	mtspr	L1CSR1,%r0	/* invalidate i-cache */

	mfspr	%r1,DBSR
	mtspr	DBSR,%r1		/* Clear all valid bits */

	/* Enable L1 Caches early */

	lis	%r2,L1CSR0_CPE at H	/* enable parity */
	ori	%r2,%r2,L1CSR0_DCE
	mtspr	L1CSR0,%r2	/* enable L1 Dcache */
	isync
	mtspr	L1CSR1,%r2	/* enable L1 Icache */
	isync
	sync

########################################################################
#
# Clear and set up some registers - CCSRBAR use default value
########################################################################
#

	li      %r0,0x0000
	
	lis		%r1,0xffff
	mtspr	DEC, %r0			/* prevent dec
exceptions */
	mttbl	%r0					/* prevent fit &
wdt exceptions */
	mttbu	%r0
	mtspr	TSR, %r1			/* clear all timer
exception status */
	mtspr	TCR, %r0			/* disable all - Disable
WDT */
	mtspr	ESR, %r0			/* clear exception
syndrome register */
	mtspr	MCSR,%r0			/* machine check
syndrome register */
	mtxer	%r0					/* clear integer

exception register */

mtspr MMUCSR0, %r1 /* invalidate all tlb's
*/

	/* Enable Time Base and Select Time Base Clock */
	lis	%r0,HID0_EMCP at h				/* Enable

machine check */

	ori	%r0, %r0, HID0_ENMAS7 at l  	/*Only For e500V2

Processors*/

	ori	%r0, %r0,HID0_TBEN at l		/* Enable Timebase */
	mtspr	HID0, %r0
	
	/* create a temp mapping in AS=1 to the boot window */
	lis %r6, 0x100F0000 at h
	ori %r6, %r6, 0x100F0000 at l
	lis %r7, 0xC0001000 at h
	ori %r7, %r7, 0xC0001700 at l
	lis %r8, 0xFF00000A at h
	ori %r8, %r8, 0xFF00000A at l
	lis %r9, 0xFF000015 at h
	ori %r9, %r9, 0xFF000015 at l
	
	mtspr   MAS0,%r6
	mtspr   MAS1,%r7
	mtspr   MAS2,%r8
	mtspr   MAS3,%r9
	isync
	msync
	tlbwe
	tlbre
	
	/* create a temp mapping in AS=1 to the stack */
	lis %r6, 0x100E0000 at h
	ori %r6, %r6, 0x100E0000 at l
	lis %r7, 0xC0001000 at h
	ori %r7, %r7, 0xC0001200 at l
	lis %r8, 0xE4010000 at h
	ori %r8, %r8, 0xE4010000 at l
	lis %r9, 0XE4010015 at h
	ori %r9, %r9, 0XE4010015 at l

	mtspr   MAS0,%r6
	mtspr   MAS1,%r7
	mtspr   MAS2,%r8
	mtspr   MAS3,%r9
	isync
	msync
	tlbwe

	lis	%r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS at h
	ori	%r6,%r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS at l
	lis	%r7,switch_as at h
	ori	%r7,%r7,switch_as at l

	mtspr	SRR0,%r7
	mtspr	SRR1,%r6
	rfi

switch_as:

	/* L1 DCache is used for initial RAM */

	/* Allocate Initial RAM in data cache. */
	lis	%r3,CONFIG_SYS_INIT_RAM_ADDR at h
	ori	%r3,%r3,CONFIG_SYS_INIT_RAM_ADDR at l
	mfspr	%r2, L1CFG0
	andi.	%r2, %r2, 0x1ff
	
	/* cache size * 1024 / (2 * L1 line size) */
	slwi	%r2, %r2, (10 - 1 - L1_CACHE_SHIFT)
	mtctr	%r2
	li	%r0,0
1:
	dcbz	%r0,%r3
	dcbtls	0,%r0,%r3
	addi	%r3,%r3,CONFIG_SYS_CACHELINE_SIZE
	bdnz	1b

	/* Jump out the last 4K page and continue to 'normal' start */
	/* Calculate absolute address in FLASH and jump there

*/

/*--------------------------------------------------------------*/

	lis	%r3,CONFIG_SYS_MONITOR_BASE at h
	ori	%r3,%r3,CONFIG_SYS_MONITOR_BASE at l
	addi	%r3,%r3,_start_cont - _start + _START_OFFSET
	mtlr	%r3
	blr

#-----------------------------------------------------
# Special sequence needed to update CCSRBAR itself
#-----------------------------------------------------
..globl setup_ccsrbar
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) setup_ccsrbar:

	lis	%r4, CONFIG_SYS_CCSRBAR_DEFAULT at h
	ori	%r4, %r4, CONFIG_SYS_CCSRBAR_DEFAULT at l

	lis	%r5, CONFIG_SYS_CCSRBAR at h
	ori	%r5, %r5, CONFIG_SYS_CCSRBAR at l
	srwi	%r6,%r5,12
	stw	%r6, 0(%r4)
	isync

	lis	%r5, 0xffff
	ori	%r5,%r5,0xf000
	lwz	%r5, 0(%r5)
	isync

	lis	%r3, CONFIG_SYS_CCSRBAR at h
	lwz	%r5, CONFIG_SYS_CCSRBAR at l(%r3)
	isync

	blr

#endif

.text
.globl _start

_start:

	.long	0xDEADBEEF
	
	.align	4
	.globl	_start_cont

_start_cont:

	/* Setup the stack in initial RAM,could be L2-as-SRAM or L1
dcache*/
	lis	%r1,CONFIG_SYS_INIT_RAM_ADDR at h
	ori	%r1,%r1,CONFIG_SYS_INIT_SP_OFFSET at l

	li	%r0,0
	stwu %r0,-4(%r1)
	stwu %r0,-4(%r1)		/* Terminate call chain */

	stwu %r1,-8(%r1)		/* Save back chain and move SP
*/
	lis	%r0,RESET_VECTOR at h	/* Address of reset vector */
	ori	%r0,%r0,RESET_VECTOR at l
	stwu %r1,-8(%r1)		/* Save back chain and move SP
*/
	stw	%r0,+12(%r1)		/* Save return addr (underflow

vect) */

	#switch back to AS = 0
	lis	%r3,(MSR_CE|MSR_ME|MSR_DE)@h
	ori	%r3,%r3,(MSR_CE|MSR_ME|MSR_DE)@l
	mtmsr	%r3
	isync

	bl	main		# Jump to main() 

exit:

b exit # If there is a return from main(), loop
forever

..globl mpc85xx_start_image
mpc85xx_start_image:
#----------------------------------------
# Disable D-cache
#----------------------------------------

	mfspr	%r4,L1CSR0
	lis	    %r5,0
	ori		%r5,%r5,L1CSR0_DCE
	andc	%r4,%r4,%r5
	mtspr	L1CSR0,%r0
	isync

#----------------------------------------
# Jump to image
#----------------------------------------

	mtlr	%r3
	blr

.end # end of text section

Start.o
========
D:\MPC8568\bsp-freescale-cdsmpc8568_cpusub\cpusub\ppc\be\start.o:
file format elf32-powerpc D:\MPC8568\bsp-freescale-cdsmpc8568_cpusub\cpusub\ppc\be\start.o
architecture: powerpc:common, flags 0x00000011:
HAS_RELOC, HAS_SYMS
start address 0x00000000

Sections:

Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         00000070  00000000  00000000  00000040  2**4

CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
1 .data 00000000 00000000 00000000 000000b0 2**0
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000000 00000000 00000000 000000b0 2**0
ALLOC
3 .bootpg 000001c4 00000000 00000000 000000b0 2**0
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
4 .PPC.EMB.apuinfo 00000018 00000000 00000000 00000274 2**0
CONTENTS, READONLY
SYMBOL TABLE:

00000001 l       *ABS*	00000000 PPC_CPUOP_ENABLED
00000001 l       *ABS*	00000000 MPC8280
00000001 l       *ABS*	00000000 BUILDENV_qss
00000001 l       *ABS*	00000000 VARIANT_cpusub
00000001 l       *ABS*	00000000 VARIANT_be
00000000 l    d  .text	00000000 .text
00000000 l    d  .data	00000000 .data
00000000 l    d  .bss	00000000 .bss
00000000 l    d  .bootpg	00000000 .bootpg
00000148 l       .bootpg	00000000 switch_as
0000004c l       .text	00000000 exit
00000000 l    d  .PPC.EMB.apuinfo	00000000 .PPC.EMB.apuinfo
00000000 g       .bootpg	00000000 _start_e500
00000188 g       .bootpg	00000000 setup_ccsrbar
00000010 g       .text	00000000 _start_cont
00000000 g       .text	00000000 _start
00000000         *UND*	00000000 main
00000050 g       .text	00000000 mpc85xx_start_image

Disassembly of section .text:

00000000 <_start>:
0: de ad be ef .long 0xdeadbeef
4: 60 00 00 00 nop
8: 60 00 00 00 nop
c: 60 00 00 00 nop

00000010 <_start_cont>:

  10:	3c 20 e4 01 	lis     r1,-7167
  14:	60 21 3f 80 	ori     r1,r1,16256
  18:	38 00 00 00 	li      r0,0
  1c:	94 01 ff fc 	stwu    r0,-4(r1)
  20:	94 01 ff fc 	stwu    r0,-4(r1)
  24:	94 21 ff f8 	stwu    r1,-8(r1)
  28:	3c 00 ff ff 	lis     r0,-1
  2c:	60 00 ff fc 	ori     r0,r0,65532
  30:	94 21 ff f8 	stwu    r1,-8(r1)
  34:	90 01 00 0c 	stw     r0,12(r1)
  38:	3c 60 00 02 	lis     r3,2
  3c:	60 63 12 00 	ori     r3,r3,4608
  40:	7c 60 01 24 	mtmsr   r3
  44:	4c 00 01 2c 	isync
  48:	48 00 00 01 	bl      48 <_start_cont+0x38>
			48: R_PPC_REL24	main

0000004c <exit>:
4c: 48 00 00 00 b 4c <exit>

00000050 <mpc85xx_start_image>:
50: 7c 92 fa a6 mfdbcr0 r4

  54:	3c a0 00 00 	lis     r5,0
  58:	60 a5 00 01 	ori     r5,r5,1
  5c:	7c 84 28 78 	andc    r4,r4,r5

60: 7c 12 fb a6 mtdbcr0 r0
64: 4c 00 01 2c isync
68: 7c 68 03 a6 mtlr r3
6c: 4e 80 00 20 blr
Disassembly of section .bootpg:

00000000 <_start_e500>:
0: 48 00 00 01 bl 0 <_start_e500>

			0: R_PPC_REL24	setup_ccsrbar
   4:	3c c0 10 0c 	lis     r6,4108
   8:	60 c6 00 00 	ori     r6,r6,0
   c:	3c e0 c0 00 	lis     r7,-16384
  10:	60 e7 05 00 	ori     r7,r7,1280
  14:	3d 00 e0 00 	lis     r8,-8192
  18:	61 08 00 08 	ori     r8,r8,8
  1c:	3d 20 e0 00 	lis     r9,-8192
  20:	61 29 00 15 	ori     r9,r9,21
  24:	7c d0 9b a6 	mtspr   624,r6
  28:	7c f1 9b a6 	mtspr   625,r7
  2c:	7d 12 9b a6 	mtspr   626,r8
  30:	7d 33 9b a6 	mtspr   627,r9
  34:	4c 00 01 2c 	isync
  38:	7c 00 04 ac 	sync    
  3c:	7c 00 07 a4 	tlbwehi r0,r0
  40:	7c 00 07 64 	tlbrehi r0,r0
  44:	38 00 00 02 	li      r0,2
  48:	7c 12 fb a6 	mtdbcr0 r0
  4c:	7c 13 fb a6 	mtspr   1011,r0
  50:	7c 30 4a a6 	mfspr   r1,304
  54:	7c 30 4b a6 	mtspr   304,r1
  58:	3c 40 00 01 	lis     r2,1
  5c:	60 42 00 01 	ori     r2,r2,1
  60:	7c 52 fb a6 	mtdbcr0 r2
  64:	4c 00 01 2c 	isync
  68:	7c 53 fb a6 	mtspr   1011,r2
  6c:	4c 00 01 2c 	isync
  70:	7c 00 04 ac 	sync    
  74:	38 00 00 00 	li      r0,0
  78:	3c 20 ff ff 	lis     r1,-1
  7c:	7c 16 03 a6 	mtdec   r0
  80:	7c 1c 43 a6 	mtsprg  4,r0
  84:	7c 1d 43 a6 	mtsprg  5,r0
  88:	7c 30 53 a6 	mtspr   336,r1
  8c:	7c 14 53 a6 	mtspr   340,r0
  90:	7c 1e 0b a6 	mtspr   62,r0
  94:	7c 1c 8b a6 	mtspr   572,r0
  98:	7c 01 03 a6 	mtxer   r0
  9c:	7c 34 fb a6 	mtiac1  r1
  a0:	3c 00 80 00 	lis     r0,-32768
  a4:	60 00 00 80 	ori     r0,r0,128
  a8:	60 00 40 00 	ori     r0,r0,16384
  ac:	7c 10 fb a6 	mtdbsr  r0
  b0:	3c c0 10 0f 	lis     r6,4111
  b4:	60 c6 00 00 	ori     r6,r6,0
  b8:	3c e0 c0 00 	lis     r7,-16384
  bc:	60 e7 17 00 	ori     r7,r7,5888
  c0:	3d 00 ff 00 	lis     r8,-256
  c4:	61 08 00 0a 	ori     r8,r8,10
  c8:	3d 20 ff 00 	lis     r9,-256
  cc:	61 29 00 15 	ori     r9,r9,21
  d0:	7c d0 9b a6 	mtspr   624,r6
  d4:	7c f1 9b a6 	mtspr   625,r7
  d8:	7d 12 9b a6 	mtspr   626,r8
  dc:	7d 33 9b a6 	mtspr   627,r9
  e0:	4c 00 01 2c 	isync
  e4:	7c 00 04 ac 	sync    
  e8:	7c 00 07 a4 	tlbwehi r0,r0
  ec:	7c 00 07 64 	tlbrehi r0,r0
  f0:	3c c0 10 0e 	lis     r6,4110
  f4:	60 c6 00 00 	ori     r6,r6,0
  f8:	3c e0 c0 00 	lis     r7,-16384
  fc:	60 e7 12 00 	ori     r7,r7,4608
 100:	3d 00 e4 01 	lis     r8,-7167
 104:	61 08 00 00 	ori     r8,r8,0
 108:	3d 20 e4 01 	lis     r9,-7167
 10c:	61 29 00 15 	ori     r9,r9,21
 110:	7c d0 9b a6 	mtspr   624,r6
 114:	7c f1 9b a6 	mtspr   625,r7
 118:	7d 12 9b a6 	mtspr   626,r8
 11c:	7d 33 9b a6 	mtspr   627,r9
 120:	4c 00 01 2c 	isync
 124:	7c 00 04 ac 	sync    
 128:	7c 00 07 a4 	tlbwehi r0,r0
 12c:	3c c0 00 02 	lis     r6,2
 130:	60 c6 12 30 	ori     r6,r6,4656
 134:	3c e0 00 00 	lis     r7,0
			136: R_PPC_ADDR16_HI	.bootpg+0x148
 138:	60 e7 01 48 	ori     r7,r7,328
			13a: R_PPC_ADDR16_LO	.bootpg+0x148

13c: 7c fa 03 a6 mtsrr0 r7
140: 7c db 03 a6 mtsrr1 r6
144: 4c 00 00 64 rfi

00000148 <switch_as>:

 148:	3c 60 e4 01 	lis     r3,-7167
 14c:	60 63 00 00 	ori     r3,r3,0
 150:	7c 43 82 a6 	mfspr   r2,515
 154:	70 42 01 ff 	andi.   r2,r2,511
 158:	54 42 20 36 	rlwinm  r2,r2,4,0,27
 15c:	7c 49 03 a6 	mtctr   r2
 160:	38 00 00 00 	li      r0,0
 164:	7c 00 1f ec 	dcbz    r0,r3
 168:	7c 00 19 4c 	.long 0x7c00194c
 16c:	38 63 00 20 	addi    r3,r3,32
 170:	42 00 ff f4 	bdnz+   164 <switch_as+0x1c>
 174:	3c 60 ff f8 	lis     r3,-8
 178:	60 63 00 00 	ori     r3,r3,0
 17c:	38 63 00 10 	addi    r3,r3,16
 180:	7c 68 03 a6 	mtlr    r3

184: 4e 80 00 20 blr

00000188 <setup_ccsrbar>:

 188:	3c 80 ff 70 	lis     r4,-144
 18c:	60 84 00 00 	ori     r4,r4,0
 190:	3c a0 e0 00 	lis     r5,-8192
 194:	60 a5 00 00 	ori     r5,r5,0
 198:	54 a6 a3 3e 	rlwinm  r6,r5,20,12,31
 19c:	90 c4 00 00 	stw     r6,0(r4)
 1a0:	4c 00 01 2c 	isync
 1a4:	3c a0 ff ff 	lis     r5,-1
 1a8:	60 a5 f0 00 	ori     r5,r5,61440
 1ac:	80 a5 00 00 	lwz     r5,0(r5)

1b0: 4c 00 01 2c isync
1b4: 3c 60 e0 00 lis r3,-8192
1b8: 80 a3 00 00 lwz r5,0(r3)
1bc: 4c 00 01 2c isync
1c0: 4e 80 00 20 blr

Linker Code
===========

OUTPUT_ARCH(powerpc)

SECTIONS
{
.resetvec 0xFFFFFFFC:

  {
    *(.resetvec)

} = 0xffff

  .bootpg 0xFFFFF000:
  {
     start.o     (.bootpg)
  } = 0xffff

  .text 0xFFF80000:
  {
    start.o (.text)
    board.o (.text)
    main.o (.text)
    *(.text)
    *(.fixup)
    *(.got1)
   }

.data :

  {
    *(.data)
    *(.data1)
    *(.sdata)
    *(.sdata2)
    *(.dynamic)
    CONSTRUCTORS

}
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

Thanks & Regards,
Vignesh Kumar B

Disclaimer:
This message and any attachment(s) contained here are information that is confidential, proprietary to HCL Technologies and its customers. Contents may be privileged or otherwise protected by law. The information is solely intended for the individual or the entity it is addressed to. If you are not the intended recipient of this message, you are not authorized to read, forward, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer.

DISCLAIMER:
-----------------------------------------------------------------------------------------------------------------------

The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. It shall not attach any liability on the originator or HCL or its affiliates. Any views or opinions presented in this email are solely those of the author and may not necessarily reflect the opinions of HCL or its affiliates. Any form of reproduction, dissemination, copying, disclosure, modification, distribution and / or publication of this message without the prior written consent of the author of this e-mail is strictly prohibited. If you have received this email in error please delete it and notify the sender immediately. Before opening any mail and attachments please check them for viruses and defect.

-----------------------------------------------------------------------------------------------------------------------

How big is the u-boot image as a whole (if you remove the bootpage stuff so it will link)? What is the diff between a working version and your changes?

-Scott

I thought this already had a constant defined, and I was right. It was PORDEVSR_PCI. However, it wasn't next to the others, and your definition is more consistent with the other code and with the manual.
As such, I converted all the other 8548 systems which checked that
bit to use your definition.

Thanks