Added uncached accelerated CPU feature
cover Added uncached accelerated CPU feature
This patchset adds uncached accelerated CPU feature and handles write_combine parameter in pci_mmap_page_range function.
Zhang Le (3):
MIPS: added cpu_has_uncached_accelerated feature
MIPS: Loongson 2 has cpu_has_uncached_accelerated feature
MIPS: handle write_combine in pci_mmap_page_range
arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 1 + .../asm/mach-lemote/cpu-feature-overrides.h | 1 + arch/mips/kernel/cpu-probe.c | 4 ++-- arch/mips/pci/pci.c | 8 ++++++-- 5 files changed, 14 insertions(+), 4 deletions(-)
PATCH 1/3 MIPS: added cpu_has_uncached_accelerated feature
--- arch/mips/include/asm/cpu-features.h | 4 ++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/kernel/cpu-probe.c | 4 ++-- 3 files changed, 7 insertions(+), 2 deletions(-)
arch/mips/include/asm/cpu-features.h +4 -0
@@ -220,6 +220,10 @@#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)#endif +#ifndef cpu_has_uncached_accelerated +#define cpu_has_uncached_accelerated (cpu_data[0].options & MIPS_CPU_UNCACHED_ACCELERATED) +#endif +#ifndef cpu_dcache_line_size#define cpu_dcache_line_size () cpu_data[0].dcache.linesz#endif
arch/mips/include/asm/cpu.h +1 -0
@@ -265,6 +265,7 @@ enum cpu_type_enum {#define MIPS_CPU_VINT 0x00080000/* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00100000/* CPU supports MIPSR2 external interrupt controller mode */ #define MIPS_CPU_ULRI 0x00200000/* CPU has ULRI feature */ +#define MIPS_CPU_UNCACHED_ACCELERATED 0x00400000/* CPU has uncached accelerated feature */ /* * CPU ASE encodings
arch/mips/kernel/cpu-probe.c +2 -2
@@ -547,7 +547,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->options =MIPS_CPU_TLB |MIPS_CPU_4K_CACHE |MIPS_CPU_4KEX |MIPS_CPU_FPU |MIPS_CPU_32FPR |MIPS_CPU_COUNTER |MIPS_CPU_WATCH | -MIPS_CPU_LLSC ; +MIPS_CPU_LLSC |MIPS_CPU_UNCACHED_ACCELERATED ; c->tlbsize =64 ;break ;case PRID_IMP_R12000 :
@@ -576,7 +576,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) c->isa_level =MIPS_CPU_ISA_III ; c->options =R4K_OPTS |MIPS_CPU_FPU |MIPS_CPU_LLSC | -MIPS_CPU_32FPR ; +MIPS_CPU_32FPR |MIPS_CPU_UNCACHED_ACCELERATED ; c->tlbsize =64 ;break ; }
Signature · 1 line
1.6.2.3
PATCH 2/3 MIPS: Loongson 2 has cpu_has_uncached_accelerated feature
--- .../asm/mach-lemote/cpu-feature-overrides.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h +1 -0
@@ -50,6 +50,7 @@#define cpu_has_tlb 1#define cpu_has_tx39_cache 0#define cpu_has_userlocal 0 +#define cpu_has_uncached_accelerated 1#define cpu_has_vce 0#define cpu_has_vtag_icache 0#define cpu_has_watch 1
Signature · 1 line
1.6.2.3
PATCH 3/3 MIPS: handle write_combine in pci_mmap_page_range
--- arch/mips/pci/pci.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-)
arch/mips/pci/pci.c +6 -2
@@ -346,10 +346,14 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,return -EINVAL ;/* -* Ignore write-combine; for now only return uncached mappings. +* For write-combine, return uncached accelerated mappings if CPU +* supports; otherwise, return uncached mappings. */ prot =pgprot_val (vma->vm_page_prot); - prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; +if (write_combine && cpu_has_uncached_accelerated) + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED_ACCELERATED; +else + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; vma->vm_page_prot =__pgprot (prot); return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
Signature · 1 line
1.6.2.3
Re: [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range
Quoted 14 lines · 在 2009-05-08五的 14:30 +0800，Zhang Le写道：
Signed-off-by Zhang Le <[email protected]>--- arch/mips/pci/pci.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-)arch/mips/pci/pci.c +0
-1@@ -346,10 +346,14 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,return -EINVAL ;/* -* Ignore write-combine; for now only return uncached mappings.
arch/mips/pci/pci.c int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, · line 357
Quoted 10 lines
arch/mips/pci/pci.c +6
-1+* For write-combine, return uncached accelerated mappings if CPU +* supports; otherwise, return uncached mappings. */ prot =pgprot_val (vma->vm_page_prot); - prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; +if (write_combine && cpu_has_uncached_accelerated) + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED_ACCELERATED; +else + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; vma->vm_page_prot =__pgprot (prot);
This should be definietely wrong for MMIOs.
uncache accelleration should only be enabled for addresses which have no side effect when doing write combine such as video memory.
Quoted 2 lines
arch/mips/pci/pci.c +0
-0return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
Re: [PATCH 3/3] MIPS: handle write_combine in pci_mmap_page_range
Quoted 14 lines · yanh
Quoted 12 lines · 在 2009-05-08五的 14:30 +0800，Zhang Le写道：
Signed-off-by Zhang Le <[email protected]>--- arch/mips/pci/pci.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-)arch/mips/pci/pci.c +0
-0@@ -346,10 +346,14 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,return -EINVAL ;
Quoted 15 lines
arch/mips/pci/pci.c int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, · line 357
Quoted 12 lines
arch/mips/pci/pci.c +6
-2/* -* Ignore write-combine; for now only return uncached mappings. +* For write-combine, return uncached accelerated mappings if CPU +* supports; otherwise, return uncached mappings. */ prot =pgprot_val (vma->vm_page_prot); - prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; +if (write_combine && cpu_has_uncached_accelerated) + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED_ACCELERATED; +else + prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED; vma->vm_page_prot =__pgprot (prot);This should be definietely wrong for MMIOs.
uncache accelleration should only be enabled for addresses which have no side effect when doing write combine such as video memory.
Actually, currently write_combine is true only for prefetchable pci memory:
http://lxr.linux.no/linux+v2.6.29/drivers/pci/pci-sysfs.c#L711
And currently on fuloong 2f box, there is only one prefetchable pci memory region, which just belongs to video card:
zhangle@2f /sys/devices/pci0000:00 (n32) $ find -name "*wc" -exec ls -l {} \; -rw------- 1 root root 256M 2009-05-08 03:25 ./0000:00:08.0/resource0_wc
So, are we talking about the same thing?
Also, I have observed that this region is larger than the actual video ram size 32M. However, libpciaccess only mapped 32M into X's address space:
zhangle@2f ~ (n32) $ sudo cat /proc/$(pidof X)/maps | grep wc$ 2b354000-2d354000 rw-s 50000000 00:00 1882 /sys/devices/pci0000:00/0000:00:08.0/resource0_wc
So, I guess this should be just ok, right?
Any other risks?
Quoted 3 lines
Quoted 2 lines
arch/mips/pci/pci.c +0
-0return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
Signature · 4 lines
Zhang, Le Gentoo/Loongson Developer http://zhangle.is-a-geek.org 0260 C902 B8F8 6506 6586 2B90 BC51 C808 1E4E 2973