piix_pci cleanup

PATCH In review Juan Quintela 1 participant 18 messages Aug 28, 2009 Kbuild

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Juan Quintela

author

2009-08-28 13:30 UTC #0 lore raw

v4 cover piix_pci cleanup

v4:
- rebase to today git. conflicted with now init functions return int.
- moved to new vmstate infrastructure
- fix vmstate to work well with substructures (we need subsections to do it right).

Later, Juan.

v3:
- rebase to today git. Fix conflicts with avi pic/isa cleanup.

v2:
- bit the bullet, change irq_opaque to void *, instead of qemu_irq * that allows us to pass anything there.
- Rearrange piix_pci to be able to add piix3_dev to the irq_state
- Once rearrangmente is fixed, make sane SaveVM *_load/_save() functions. We can still load old state, but we only write the sane one.

mips_malta can do a similar cleanup, it is not difficult to do. But I can't test it.

About irq_state in i440fx_init(). It would have been easier, if there were a way to create i440FX-pcihost giving it the already allocated variable. Basically:

pci_bus = pci_register_bus() -> needs irq_state
i440fx = pci_create_simple(pci_bus, ..) -> needs pci_bus piix3 = pci_create_simple (pci_bus, ...) -> needs pci_bus

irq_state -> needs piix3

We have a nice circular dependency here. to fix it, I just create an empty irq_state, passed it to pci_register_bus() and fill it later.

It would have been a bit cleaner if there were a finction like i440fx = pci_create_simple_here(..., &i440fx).

Later, Juan.

v1:
- split piix4 from piix_pci. The only shared code where piix_save/load, i.e. almost nothing. Once there, compile piix4.o only for mips (it was not used anywhere else).
- Move global variables to PCII440FXState. Nice and clean until....
- pci_irq_levels: This is great:
* it is saved/loaded from i440fx
* it is cleaned during reset in piix3
* it is used in piix3_set_irq, that don't receive neither i440fx nor piix state, it needs to be a global variable. (created a global link until a better solution appear).

I looked where to "hide" pci_irq_levels and piix3_dev (both needed in piix3_set_irq), and didn't found where to pass them, out of:
- hack i8259 to hide it into PicState2 (that one got passed through the pic) ugly for words, but will work
- try to add <something> at setup_irq time, but at that point we have:
* opaque -> pci_dev of device that we are working with
* from there we can get to the bus that the device is attached to, but no way to go from there to the Host bridge (that is what we wanted in the 1st place)

Later, Juan.

Juan Quintela (16):
piix4 don't use pci_irq_levels at all
Split piix4 support from piix_pci.c
low_set_irq is not used anywhere
Use PCII440FXState instead of generic PCIDevice Move smm_enabled and isa_memory_mappings to PCII440FXState We want the argument pass to set_irq to be opaque Create PIIX3State instead of using PCIDevice for PIIX3 Introduce PIIX3IrqState for piix3 irq's state Fold piix3_init() intto i440fx_init
We can add piix3_dev now to PIIX3IrqState
Save irq_state into PCII440FXState pci_irq_levels[] belong to PIIX3State
Update SaveVM versions
VMState: Fix sub-structs versioning
i440fx: use new vmstate infrastructure
piix3: use new vmstate infrastructure

 Makefile.target    |    2 +-
 hw/apb_pci.c       |    4 +-
 hw/grackle_pci.c   |    4 +-
 hw/gt64xxx.c       |    3 +-
 hw/pc.c            |    5 +-
 hw/pc.h            |   11 ++-
 hw/pci.c           |    8 +-
 hw/pci.h           |    6 +-
 hw/piix4.c         |  128 ++++++++++++++++++++++++
 hw/piix_pci.c      |  275 +++++++++++++++++++++-------------------------------
 hw/ppc4xx_pci.c    |    4 +-
 hw/ppce500_pci.c   |    4 +-
 hw/prep_pci.c      |    4 +-
 hw/r2d.c           |    4 +-
 hw/sh_pci.c        |    4 +-
 hw/unin_pci.c      |    4 +-
 hw/versatile_pci.c |    4 +-
 savevm.c           |    2 +-
 18 files changed, 284 insertions(+), 192 deletions(-)
 create mode 100644 hw/piix4.c

Juan Quintela

author

2009-08-28 13:31 UTC #1 lore raw

PATCH v4 1/16 piix4 don't use pci_irq_levels at all

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

hw/piix_pci.c +0 -2

index c9fef92..ad85eba 100644
@@ -323,8 +323,6 @@ static void piix4_reset(void *opaque)
     pci_conf[0xab] = 0x00;
     pci_conf[0xac] = 0x00;
     pci_conf[0xae] = 0x00;
-
-    memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
 }
 
 static void piix_save(QEMUFile* f, void *opaque)

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #2 lore raw

PATCH v4 2/16 Split piix4 support from piix_pci.c

In reply to Juan Quintela

Now mips_malta uses piix4 and pc's use piix_pci definitions

Signed-off-by Juan Quintela <[email protected]>

---
 Makefile.target |    2 +-
 hw/pc.h         |    1 +
 hw/piix4.c      |  128 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/piix_pci.c   |   72 -------------------------------
 4 files changed, 130 insertions(+), 73 deletions(-)
 create mode 100644 hw/piix4.c

Makefile.target +1 -1

index f7d1919..67bd4d7 100644
@@ -214,7 +214,7 @@ obj-mips-y += mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc403
 obj-mips-y += g364fb.o jazz_led.o dp8393x.o
 obj-mips-y += ide/core.o ide/isa.o ide/pci.o
 obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
-obj-mips-y += piix_pci.o parallel.o cirrus_vga.o isa-bus.o pcspk.o $(sound-obj-y)
+obj-mips-y += piix4.o parallel.o cirrus_vga.o isa-bus.o pcspk.o $(sound-obj-y)
 obj-mips-y += mipsnet.o
 obj-mips-y += pflash_cfi01.o
 obj-mips-y += vmware_vga.o

hw/pc.h +1 -0

index 7ac2849..3c46290 100644
@@ -122,6 +122,7 @@ void i440fx_set_smm(PCIDevice *d, int val);
 int piix3_init(PCIBus *bus, int devfn);
 void i440fx_init_memory_mappings(PCIDevice *d);
 
+/* piix4.c */
 extern PCIDevice *piix4_dev;
 int piix4_init(PCIBus *bus, int devfn);

hw/piix4.c new file +128 -0

128 lines not on this page · raw message

hw/piix_pci.c +0 ~~-72~~

102 lines not on this page · raw message

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #3 lore raw

PATCH v4 3/16 low_set_irq is not used anywhere

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/pci.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

hw/pci.c +0 -2

index 41e99a9..a9034a7 100644
@@ -41,8 +41,6 @@ struct PCIBus {
     pci_set_irq_fn set_irq;
     pci_map_irq_fn map_irq;
     uint32_t config_reg; /* XXX: suppress */
-    /* low level pic */
-    SetIRQFunc *low_set_irq;
     qemu_irq *irq_opaque;
     PCIDevice *devices[256];
     PCIDevice *parent_dev;

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #4 lore raw

PATCH v4 4/16 Use PCII440FXState instead of generic PCIDevice

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/pc.c       |    2 +-
 hw/pc.h       |    9 ++++++---
 hw/piix_pci.c |   54 +++++++++++++++++++++++++++++++-----------------------
 3 files changed, 38 insertions(+), 27 deletions(-)

hw/pc.c +1 -1

index 32713b4..6477b41 100644
@@ -62,7 +62,7 @@
 static fdctrl_t *floppy_controller;
 static RTCState *rtc_state;
 static PITState *pit;
-static PCIDevice *i440fx_state;
+static PCII440FXState *i440fx_state;
 
 typedef struct rom_reset_data {
     uint8_t *data;

hw/pc.h +6 -3

index 3c46290..3572165 100644
@@ -117,10 +117,13 @@ void pcspk_init(PITState *);
 int pcspk_audio_init(qemu_irq *pic);
 
 /* piix_pci.c */
-PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
-void i440fx_set_smm(PCIDevice *d, int val);
+struct PCII440FXState;
+typedef struct PCII440FXState PCII440FXState;
+
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic);
+void i440fx_set_smm(PCII440FXState *d, int val);
 int piix3_init(PCIBus *bus, int devfn);
-void i440fx_init_memory_mappings(PCIDevice *d);
+void i440fx_init_memory_mappings(PCII440FXState *d);
 
 /* piix4.c */
 extern PCIDevice *piix4_dev;

hw/piix_pci.c +31 ~~-23~~

143 lines not on this page · raw message

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #5 lore raw

PATCH v4 5/16 Move smm_enabled and isa_memory_mappings to PCII440FXState

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |   20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

hw/piix_pci.c +10 ~~-10~~

index e4409d8..378b7bf 100644
@@ -35,6 +35,8 @@ typedef PCIHostState I440FXState;
 
 struct PCII440FXState {
     PCIDevice dev;
+    target_phys_addr_t isa_page_descs[384 / 4];
+    uint8_t smm_enabled;
 };
 
 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)

@@ -61,8 +63,6 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
     return (irq_num + slot_addend) & 3;
 }
 
-static target_phys_addr_t isa_page_descs[384 / 4];
-static uint8_t smm_enabled;
 static int pci_irq_levels[4];
 
 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)

@@ -86,7 +86,7 @@ static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
         /* XXX: should distinguish read/write cases */
         for(addr = start; addr < end; addr += 4096) {
             cpu_register_physical_memory(addr, 4096,
-                                         isa_page_descs[(addr - 0xa0000) >> 12]);
+                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
         }
         break;
     }

@@ -103,12 +103,12 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
     }
     smram = d->dev.config[0x72];
-    if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
+    if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
     } else {
         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
             cpu_register_physical_memory(addr, 4096,
-                                         isa_page_descs[(addr - 0xa0000) >> 12]);
+                                         d->isa_page_descs[(addr - 0xa0000) >> 12]);
         }
     }
 }

@@ -116,8 +116,8 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
 void i440fx_set_smm(PCII440FXState *d, int val)
 {
     val = (val != 0);
-    if (smm_enabled != val) {
-        smm_enabled = val;
+    if (d->smm_enabled != val) {
+        d->smm_enabled = val;
         i440fx_update_memory_mappings(d);
     }
 }

@@ -130,7 +130,7 @@ void i440fx_init_memory_mappings(PCII440FXState *d)
 {
     int i;
     for(i = 0; i < 96; i++) {
-        isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
+        d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
     }
 }

@@ -151,7 +151,7 @@ static void i440fx_save(QEMUFile* f, void *opaque)
     int i;
 
     pci_device_save(&d->dev, f);
-    qemu_put_8s(f, &smm_enabled);
+    qemu_put_8s(f, &d->smm_enabled);
 
     for (i = 0; i < 4; i++)
         qemu_put_be32(f, pci_irq_levels[i]);

@@ -168,7 +168,7 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
     if (ret < 0)
         return ret;
     i440fx_update_memory_mappings(d);
-    qemu_get_8s(f, &smm_enabled);
+    qemu_get_8s(f, &d->smm_enabled);
 
     if (version_id >= 2)
         for (i = 0; i < 4; i++)

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #6 lore raw

PATCH v4 6/16 We want the argument pass to set_irq to be opaque

In reply to Juan Quintela

piix_pci want to pass more things that the pic

Signed-off-by Juan Quintela <[email protected]>

---
 hw/apb_pci.c       |    4 +++-
 hw/grackle_pci.c   |    4 +++-
 hw/gt64xxx.c       |    3 ++-
 hw/pci.c           |    6 +++---
 hw/pci.h           |    6 +++---
 hw/piix_pci.c      |    5 +++--
 hw/ppc4xx_pci.c    |    4 +++-
 hw/ppce500_pci.c   |    4 +++-
 hw/prep_pci.c      |    4 +++-
 hw/r2d.c           |    4 +++-
 hw/sh_pci.c        |    4 ++--
 hw/unin_pci.c      |    4 +++-
 hw/versatile_pci.c |    4 +++-
 13 files changed, 37 insertions(+), 19 deletions(-)

hw/apb_pci.c +3 -1

index d114e55..f1088aa 100644
@@ -218,8 +218,10 @@ static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
     return bus_offset + irq_num;
 }
 
-static void pci_apb_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_apb_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pic = opaque;
+
     /* PCI IRQ map onto the first 32 INO.  */
     qemu_set_irq(pic[irq_num], level);
 }

hw/grackle_pci.c +3 -1

index 38e2fe4..177c888 100644
@@ -102,8 +102,10 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
     return (irq_num + (pci_dev->devfn >> 3)) & 3;
 }
 
-static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pic = opaque;
+
     GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
     qemu_set_irq(pic[irq_num + 0x15], level);
 }

hw/gt64xxx.c +2 -1

index 2115130..8f9ae4a 100644
@@ -893,9 +893,10 @@ static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num)
 
 static int pci_irq_levels[4];
 
-static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_gt64120_set_irq(void *opaque, int irq_num, int level)
 {
     int i, pic_irq, pic_level;
+    qemu_irq *pic = opaque;
 
     pci_irq_levels[irq_num] = level;

hw/pci.c +3 -3

index a9034a7..c12b0be 100644
@@ -41,7 +41,7 @@ struct PCIBus {
     pci_set_irq_fn set_irq;
     pci_map_irq_fn map_irq;
     uint32_t config_reg; /* XXX: suppress */
-    qemu_irq *irq_opaque;
+    void *irq_opaque;
     PCIDevice *devices[256];
     PCIDevice *parent_dev;
     PCIBus *next;

@@ -100,7 +100,7 @@ static void pci_bus_reset(void *opaque)
 
 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
-                         qemu_irq *pic, int devfn_min, int nirq)
+                         void *irq_opaque, int devfn_min, int nirq)
 {
     PCIBus *bus;
     static int nbus = 0;

@@ -108,7 +108,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char *name,
     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
     bus->set_irq = set_irq;
     bus->map_irq = map_irq;
-    bus->irq_opaque = pic;
+    bus->irq_opaque = irq_opaque;
     bus->devfn_min = devfn_min;
     bus->nirq = nirq;
     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));

hw/pci.h +3 -3

index fd1d35c..5340bbb 100644
@@ -239,11 +239,11 @@ void pci_default_write_config(PCIDevice *d,
 void pci_device_save(PCIDevice *s, QEMUFile *f);
 int pci_device_load(PCIDevice *s, QEMUFile *f);
 
-typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
+typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
-                         qemu_irq *pic, int devfn_min, int nirq);
+                         void *irq_opaque, int devfn_min, int nirq);
 
 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
                         const char *default_devaddr);

@@ -353,6 +353,6 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
 
 /* sh_pci.c */
 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
-                            qemu_irq *pic, int devfn_min, int nirq);
+                            void *pic, int devfn_min, int nirq);
 
 #endif

hw/piix_pci.c +3 -2

index 378b7bf..1a51ec5 100644
@@ -51,7 +51,7 @@ static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
     return s->config_reg;
 }
 
-static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
+static void piix3_set_irq(void *opaque, int irq_num, int level);
 
 /* return the global irq number corresponding to a given device irq
    pin. We could also use the bus number to have a more precise

@@ -233,9 +233,10 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
 
 static PCIDevice *piix3_dev;
 
-static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
+static void piix3_set_irq(void *opaque, int irq_num, int level)
 {
     int i, pic_irq, pic_level;
+    qemu_irq *pic = opaque;
 
     pci_irq_levels[irq_num] = level;

hw/ppc4xx_pci.c +3 -1

index 98877cf..655fe86 100644
@@ -304,8 +304,10 @@ static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
     return slot - 1;
 }
 
-static void ppc4xx_pci_set_irq(qemu_irq *pci_irqs, int irq_num, int level)
+static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pci_irqs = opaque;
+
     DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
     qemu_set_irq(pci_irqs[irq_num], level);
 }

hw/ppce500_pci.c +3 -1

index 6328f73..64fccfd 100644
@@ -253,8 +253,10 @@ static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
     return ret;
 }
 
-static void mpc85xx_pci_set_irq(qemu_irq *pic, int irq_num, int level)
+static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pic = opaque;
+
     pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
 
     qemu_set_irq(pic[irq_num], level);

hw/prep_pci.c +3 -1

index 2a1d0f9..2d8a0fa 100644
@@ -124,8 +124,10 @@ static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 }
 
-static void prep_set_irq(qemu_irq *pic, int irq_num, int level)
+static void prep_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pic = opaque;
+
     qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
 }

hw/r2d.c +3 -1

index 4667a5d..6ce556e 100644
@@ -183,8 +183,10 @@ static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 }
 
-static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
+static void r2d_pci_set_irq(void *opaque, int n, int l)
 {
+    qemu_irq *p = opaque;
+
     qemu_set_irq(p[n], l);
 }

hw/sh_pci.c +2 -2

index 659935f..ea8635d 100644
@@ -168,14 +168,14 @@ static MemOp sh_pci_iop = {
 };
 
 PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
-                            qemu_irq *pic, int devfn_min, int nirq)
+                            void *opaque, int devfn_min, int nirq)
 {
     SHPCIC *p;
     int mem, reg, iop;
 
     p = qemu_mallocz(sizeof(SHPCIC));
     p->bus = pci_register_bus(NULL, "pci",
-                              set_irq, map_irq, pic, devfn_min, nirq);
+                              set_irq, map_irq, opaque, devfn_min, nirq);
 
     p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
                                  -1, NULL, NULL);

hw/unin_pci.c +3 -1

index 9b5b8c8..e6d9a70 100644
@@ -141,8 +141,10 @@ static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
     return (irq_num + (pci_dev->devfn >> 3)) & 3;
 }
 
-static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_unin_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pic = opaque;
+
     qemu_set_irq(pic[irq_num + 8], level);
 }

hw/versatile_pci.c +3 -1

index 6f9151c..a0d7d07 100644
@@ -90,8 +90,10 @@ static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
     return irq_num;
 }
 
-static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level)
+static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
 {
+    qemu_irq *pic = opaque;
+
     qemu_set_irq(pic[irq_num], level);
 }

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #7 lore raw

PATCH v4 7/16 Create PIIX3State instead of using PCIDevice for PIIX3

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |   23 ++++++++++++++---------
 1 files changed, 14 insertions(+), 9 deletions(-)

hw/piix_pci.c +14 -9

index 1a51ec5..b08b063 100644
@@ -33,6 +33,10 @@ typedef uint32_t pci_addr_t;
 
 typedef PCIHostState I440FXState;
 
+typedef struct PIIX3State {
+    PCIDevice dev;
+} PIIX3State;
+
 struct PCII440FXState {
     PCIDevice dev;
     target_phys_addr_t isa_page_descs[384 / 4];

@@ -231,7 +235,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
 
 /* PIIX3 PCI to ISA bridge */
 
-static PCIDevice *piix3_dev;
+static PIIX3State *piix3_dev;
 
 static void piix3_set_irq(void *opaque, int irq_num, int level)
 {

@@ -242,13 +246,13 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
 
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */
-    pic_irq = piix3_dev->config[0x60 + irq_num];
+    pic_irq = piix3_dev->dev.config[0x60 + irq_num];
     if (pic_irq < 16) {
         /* The pic level is the logical OR of all the PCI irqs mapped
            to it */
         pic_level = 0;
         for (i = 0; i < 4; i++) {
-            if (pic_irq == piix3_dev->config[0x60 + i])
+            if (pic_irq == piix3_dev->dev.config[0x60 + i])
                 pic_level |= pci_irq_levels[i];
         }
         qemu_set_irq(pic[pic_irq], pic_level);

@@ -257,8 +261,8 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
 
 static void piix3_reset(void *opaque)
 {
-    PCIDevice *d = opaque;
-    uint8_t *pci_conf = d->config;
+    PIIX3State *d = opaque;
+    uint8_t *pci_conf = d->dev.config;
 
     pci_conf[0x04] = 0x07; // master, memory and I/O
     pci_conf[0x05] = 0x00;

@@ -309,14 +313,15 @@ static int piix_load(QEMUFile* f, void *opaque, int version_id)
     return pci_device_load(d, f);
 }
 
-static int piix3_initfn(PCIDevice *d)
+static int piix3_initfn(PCIDevice *dev)
 {
+    PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
     uint8_t *pci_conf;
 
-    isa_bus_new(&d->qdev);
+    isa_bus_new(&d->dev.qdev);
     register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
 
-    pci_conf = d->config;
+    pci_conf = d->dev.config;
     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);

@@ -348,7 +353,7 @@ static PCIDeviceInfo i440fx_info[] = {
     },{
         .qdev.name    = "PIIX3",
         .qdev.desc    = "ISA bridge",
-        .qdev.size    = sizeof(PCIDevice),
+        .qdev.size    = sizeof(PIIX3State),
         .qdev.no_user = 1,
         .init         = piix3_initfn,
     },{

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #9 lore raw

PATCH v4 9/16 Fold piix3_init() intto i440fx_init

In reply to Juan Quintela

i440fx_init will now work properly if we don't setup piix3

Signed-off-by Juan Quintela <[email protected]>

---
 hw/pc.c       |    3 +--
 hw/pc.h       |    3 +--
 hw/piix_pci.c |   18 ++++++------------
 3 files changed, 8 insertions(+), 16 deletions(-)

hw/pc.c +1 -2

index 6477b41..e771170 100644
@@ -1279,8 +1279,7 @@ static void pc_init1(ram_addr_t ram_size,
     isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
 
     if (pci_enabled) {
-        pci_bus = i440fx_init(&i440fx_state, isa_irq);
-        piix3_devfn = piix3_init(pci_bus, -1);
+        pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
     } else {
         pci_bus = NULL;
         isa_bus_new(NULL);

hw/pc.h +1 -2

index 3572165..ec5735b 100644
@@ -120,9 +120,8 @@ int pcspk_audio_init(qemu_irq *pic);
 struct PCII440FXState;
 typedef struct PCII440FXState PCII440FXState;
 
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic);
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic);
 void i440fx_set_smm(PCII440FXState *d, int val);
-int piix3_init(PCIBus *bus, int devfn);
 void i440fx_init_memory_mappings(PCII440FXState *d);
 
 /* piix4.c */

hw/piix_pci.c +6 ~~-12~~

index b931f84..86582fe 100644
@@ -217,7 +217,9 @@ static int i440fx_initfn(PCIDevice *dev)
     return 0;
 }
 
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
+static PIIX3State *piix3_dev;
+
+PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
 {
     DeviceState *dev;
     PCIBus *b;

@@ -236,13 +238,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
     d = pci_create_simple(b, 0, "i440FX");
     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 
+    piix3_dev = DO_UPCAST(PIIX3State, dev, pci_create_simple(b, -1, "PIIX3"));
+    *piix3_devfn = piix3_dev->dev.devfn;
+
     return b;
 }
 
 /* PIIX3 PCI to ISA bridge */
 
-static PIIX3State *piix3_dev;
-
 static void piix3_set_irq(void *opaque, int irq_num, int level)
 {
     int i, pic_irq, pic_level;

@@ -334,20 +337,11 @@ static int piix3_initfn(PCIDevice *dev)
     pci_conf[PCI_HEADER_TYPE] =
         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 
-    piix3_dev = d;
     piix3_reset(d);
     qemu_register_reset(piix3_reset, d);
     return 0;
 }
 
-int piix3_init(PCIBus *bus, int devfn)
-{
-    PCIDevice *d;
-
-    d = pci_create_simple(bus, devfn, "PIIX3");
-    return d->devfn;
-}
-
 static PCIDeviceInfo i440fx_info[] = {
     {
         .qdev.name    = "i440FX",

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #10 lore raw

PATCH v4 10/16 We can add piix3_dev now to PIIX3IrqState

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

hw/piix_pci.c +6 -6

index 86582fe..92884d9 100644
@@ -38,6 +38,7 @@ typedef struct PIIX3State {
 } PIIX3State;
 
 typedef struct PIIX3IrqState {
+    PIIX3State *piix3;
     qemu_irq *pic;
 } PIIX3IrqState;

@@ -217,8 +218,6 @@ static int i440fx_initfn(PCIDevice *dev)
     return 0;
 }
 
-static PIIX3State *piix3_dev;
-
 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
 {
     DeviceState *dev;

@@ -238,8 +237,9 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *
     d = pci_create_simple(b, 0, "i440FX");
     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 
-    piix3_dev = DO_UPCAST(PIIX3State, dev, pci_create_simple(b, -1, "PIIX3"));
-    *piix3_devfn = piix3_dev->dev.devfn;
+    irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
+                                 pci_create_simple(b, -1, "PIIX3"));
+    *piix3_devfn = irq_state->piix3->dev.devfn;
 
     return b;
 }

@@ -255,13 +255,13 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
 
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */
-    pic_irq = piix3_dev->dev.config[0x60 + irq_num];
+    pic_irq = irq_state->piix3->dev.config[0x60 + irq_num];
     if (pic_irq < 16) {
         /* The pic level is the logical OR of all the PCI irqs mapped
            to it */
         pic_level = 0;
         for (i = 0; i < 4; i++) {
-            if (pic_irq == piix3_dev->dev.config[0x60 + i])
+            if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
                 pic_level |= pci_irq_levels[i];
         }
         qemu_set_irq(irq_state->pic[pic_irq], pic_level);

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #8 lore raw

PATCH v4 8/16 Introduce PIIX3IrqState for piix3 irq's state

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

hw/piix_pci.c +9 -3

index b08b063..b931f84 100644
@@ -37,6 +37,10 @@ typedef struct PIIX3State {
     PCIDevice dev;
 } PIIX3State;
 
+typedef struct PIIX3IrqState {
+    qemu_irq *pic;
+} PIIX3IrqState;
+
 struct PCII440FXState {
     PCIDevice dev;
     target_phys_addr_t isa_page_descs[384 / 4];

@@ -219,11 +223,13 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, qemu_irq *pic)
     PCIBus *b;
     PCIDevice *d;
     I440FXState *s;
+    PIIX3IrqState *irq_state = qemu_malloc(sizeof(*irq_state));
 
+    irq_state->pic = pic;
     dev = qdev_create(NULL, "i440FX-pcihost");
     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
     b = pci_register_bus(&s->busdev.qdev, "pci.0",
-                         piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
+                         piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4);
     s->bus = b;
     qdev_init(dev);

@@ -240,7 +246,7 @@ static PIIX3State *piix3_dev;
 static void piix3_set_irq(void *opaque, int irq_num, int level)
 {
     int i, pic_irq, pic_level;
-    qemu_irq *pic = opaque;
+    PIIX3IrqState *irq_state = opaque;
 
     pci_irq_levels[irq_num] = level;

@@ -255,7 +261,7 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
             if (pic_irq == piix3_dev->dev.config[0x60 + i])
                 pic_level |= pci_irq_levels[i];
         }
-        qemu_set_irq(pic[pic_irq], pic_level);
+        qemu_set_irq(irq_state->pic[pic_irq], pic_level);
     }
 }

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #11 lore raw

PATCH v4 11/16 Save irq_state into PCII440FXState

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

hw/piix_pci.c +2 -0

index 92884d9..5f34678 100644
@@ -46,6 +46,7 @@ struct PCII440FXState {
     PCIDevice dev;
     target_phys_addr_t isa_page_descs[384 / 4];
     uint8_t smm_enabled;
+    PIIX3IrqState *irq_state;
 };
 
 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)

@@ -236,6 +237,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *
 
     d = pci_create_simple(b, 0, "i440FX");
     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
+    (*pi440fx_state)->irq_state = irq_state;
 
     irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
                                  pci_create_simple(b, -1, "PIIX3"));

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #12 lore raw

PATCH v4 12/16 pci_irq_levels[] belong to PIIX3State

In reply to Juan Quintela

With previous cleanups, now it is possible to put it where it belongs

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |   13 ++++++-------
 1 files changed, 6 insertions(+), 7 deletions(-)

hw/piix_pci.c +6 -7

index 5f34678..80296ac 100644
@@ -35,6 +35,7 @@ typedef PCIHostState I440FXState;
 
 typedef struct PIIX3State {
     PCIDevice dev;
+    int pci_irq_levels[4];
 } PIIX3State;
 
 typedef struct PIIX3IrqState {

@@ -73,8 +74,6 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
     return (irq_num + slot_addend) & 3;
 }
 
-static int pci_irq_levels[4];
-
 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
 {
     uint32_t addr;

@@ -164,7 +163,7 @@ static void i440fx_save(QEMUFile* f, void *opaque)
     qemu_put_8s(f, &d->smm_enabled);
 
     for (i = 0; i < 4; i++)
-        qemu_put_be32(f, pci_irq_levels[i]);
+        qemu_put_be32(f, d->irq_state->piix3->pci_irq_levels[i]);
 }
 
 static int i440fx_load(QEMUFile* f, void *opaque, int version_id)

@@ -182,7 +181,7 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
 
     if (version_id >= 2)
         for (i = 0; i < 4; i++)
-            pci_irq_levels[i] = qemu_get_be32(f);
+            d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);
 
     return 0;
 }

@@ -253,7 +252,7 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
     int i, pic_irq, pic_level;
     PIIX3IrqState *irq_state = opaque;
 
-    pci_irq_levels[irq_num] = level;
+    irq_state->piix3->pci_irq_levels[irq_num] = level;
 
     /* now we change the pic irq level according to the piix irq mappings */
     /* XXX: optimize */

@@ -264,7 +263,7 @@ static void piix3_set_irq(void *opaque, int irq_num, int level)
         pic_level = 0;
         for (i = 0; i < 4; i++) {
             if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
-                pic_level |= pci_irq_levels[i];
+                pic_level |= irq_state->piix3->pci_irq_levels[i];
         }
         qemu_set_irq(irq_state->pic[pic_irq], pic_level);
     }

@@ -307,7 +306,7 @@ static void piix3_reset(void *opaque)
     pci_conf[0xac] = 0x00;
     pci_conf[0xae] = 0x00;
 
-    memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
+    memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 }
 
 static void piix_save(QEMUFile* f, void *opaque)

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #13 lore raw

PATCH v4 13/16 Update SaveVM versions

In reply to Juan Quintela

Now that we have all fields belonging to a PCIDevice, save each field on the device that it belongs. This means moving pci_irq_levels from PCII440FXState to PIIX3State.
Old formats are loaded, but we only save on the new saner format.

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |   40 +++++++++++++++++++++++++---------------
 1 files changed, 25 insertions(+), 15 deletions(-)

hw/piix_pci.c +25 ~~-15~~

index 80296ac..a044883 100644
@@ -157,13 +157,9 @@ static void i440fx_write_config(PCIDevice *dev,
 static void i440fx_save(QEMUFile* f, void *opaque)
 {
     PCII440FXState *d = opaque;
-    int i;
 
     pci_device_save(&d->dev, f);
     qemu_put_8s(f, &d->smm_enabled);
-
-    for (i = 0; i < 4; i++)
-        qemu_put_be32(f, d->irq_state->piix3->pci_irq_levels[i]);
 }
 
 static int i440fx_load(QEMUFile* f, void *opaque, int version_id)

@@ -171,7 +167,7 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
     PCII440FXState *d = opaque;
     int ret, i;
 
-    if (version_id > 2)
+    if (version_id > 3)
         return -EINVAL;
     ret = pci_device_load(&d->dev, f);
     if (ret < 0)

@@ -179,7 +175,7 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
     i440fx_update_memory_mappings(d);
     qemu_get_8s(f, &d->smm_enabled);
 
-    if (version_id >= 2)
+    if (version_id == 2)
         for (i = 0; i < 4; i++)
             d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);

@@ -214,7 +210,7 @@ static int i440fx_initfn(PCIDevice *dev)
 
     d->dev.config[0x72] = 0x02; /* SMRAM */
 
-    register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
+    register_savevm("I440FX", 0, 3, i440fx_save, i440fx_load, d);
     return 0;
 }

@@ -309,18 +305,32 @@ static void piix3_reset(void *opaque)
     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 }
 
-static void piix_save(QEMUFile* f, void *opaque)
+static void piix3_save(QEMUFile* f, void *opaque)
 {
-    PCIDevice *d = opaque;
-    pci_device_save(d, f);
+    PIIX3State *d = opaque;
+    int i;
+
+    pci_device_save(&d->dev, f);
+
+    for (i = 0; i < 4; i++)
+        qemu_put_be32(f, d->pci_irq_levels[i]);
 }
 
-static int piix_load(QEMUFile* f, void *opaque, int version_id)
+static int piix3_load(QEMUFile* f, void *opaque, int version_id)
 {
-    PCIDevice *d = opaque;
-    if (version_id != 2)
+    PIIX3State *d = opaque;
+    int i, ret;
+
+    if (version_id > 3 || version_id < 2)
         return -EINVAL;
-    return pci_device_load(d, f);
+    ret = pci_device_load(&d->dev, f);
+    if (ret < 0)
+        return ret;
+    if (version_id >= 3) {
+        for (i = 0; i < 4; i++)
+            d->pci_irq_levels[i] = qemu_get_be32(f);
+    }
+    return 0;
 }
 
 static int piix3_initfn(PCIDevice *dev)

@@ -329,7 +339,7 @@ static int piix3_initfn(PCIDevice *dev)
     uint8_t *pci_conf;
 
     isa_bus_new(&d->dev.qdev);
-    register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
+    register_savevm("PIIX3", 0, 3, piix3_save, piix3_load, d);
 
     pci_conf = d->dev.config;
     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #14 lore raw

PATCH v4 14/16 VMState: Fix sub-structs versioning

In reply to Juan Quintela

We can't check the version in a substruct, it is not stored anywhere

Signed-off-by Juan Quintela <[email protected]>

---
 savevm.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

savevm.c +1 -1

index 2b4054a..99fad79 100644
@@ -1048,7 +1048,7 @@ int vmstate_load_state(QEMUFile *f, const VMStateDescription *vmsd,
                 void *addr = base_addr + field->size * i;
 
                 if (field->flags & VMS_STRUCT) {
-                    ret = vmstate_load_state(f, field->vmsd, addr, version_id);
+                    ret = vmstate_load_state(f, field->vmsd, addr, field->vmsd->version_id);
                 } else {
                     ret = field->info->get(f, addr, field->size);

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #15 lore raw

PATCH v4 15/16 i440fx: use new vmstate infrastructure

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |   36 ++++++++++++++++++++++++------------
 1 files changed, 24 insertions(+), 12 deletions(-)

hw/piix_pci.c +24 ~~-12~~

index a044883..5c33741 100644
@@ -154,21 +154,11 @@ static void i440fx_write_config(PCIDevice *dev,
         i440fx_update_memory_mappings(d);
 }
 
-static void i440fx_save(QEMUFile* f, void *opaque)
-{
-    PCII440FXState *d = opaque;
-
-    pci_device_save(&d->dev, f);
-    qemu_put_8s(f, &d->smm_enabled);
-}
-
-static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
+static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 {
     PCII440FXState *d = opaque;
     int ret, i;
 
-    if (version_id > 3)
-        return -EINVAL;
     ret = pci_device_load(&d->dev, f);
     if (ret < 0)
         return ret;

@@ -182,6 +172,28 @@ static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
     return 0;
 }
 
+static int i440fx_after_load(void *opaque)
+{
+    PCII440FXState *d = opaque;
+
+    i440fx_update_memory_mappings(d);
+    return 0;
+}
+
+static const VMStateDescription vmstate_i440fx = {
+    .name = "I440FX",
+    .version_id = 3,
+    .minimum_version_id = 3,
+    .minimum_version_id_old = 1,
+    .load_state_old = i440fx_load_old,
+    .run_after_load = i440fx_after_load,
+    .fields      = (VMStateField []) {
+        VMSTATE_PCI_DEVICE(dev, PCII440FXState),
+        VMSTATE_UINT8(smm_enabled, PCII440FXState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 {
     I440FXState *s = FROM_SYSBUS(I440FXState, dev);

@@ -210,7 +222,7 @@ static int i440fx_initfn(PCIDevice *dev)
 
     d->dev.config[0x72] = 0x02; /* SMRAM */
 
-    register_savevm("I440FX", 0, 3, i440fx_save, i440fx_load, d);
+    vmstate_register(0, &vmstate_i440fx, d);
     return 0;
 }

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:31 UTC #16 lore raw

PATCH v4 16/16 piix3: use new vmstate infrastructure

In reply to Juan Quintela

Signed-off-by Juan Quintela <[email protected]>

---
 hw/piix_pci.c |   38 +++++++++++---------------------------
 1 files changed, 11 insertions(+), 27 deletions(-)

hw/piix_pci.c +11 ~~-27~~

index 5c33741..ef3463b 100644
@@ -317,33 +317,17 @@ static void piix3_reset(void *opaque)
     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 }
 
-static void piix3_save(QEMUFile* f, void *opaque)
-{
-    PIIX3State *d = opaque;
-    int i;
-
-    pci_device_save(&d->dev, f);
-
-    for (i = 0; i < 4; i++)
-        qemu_put_be32(f, d->pci_irq_levels[i]);
-}
-
-static int piix3_load(QEMUFile* f, void *opaque, int version_id)
-{
-    PIIX3State *d = opaque;
-    int i, ret;
-
-    if (version_id > 3 || version_id < 2)
-        return -EINVAL;
-    ret = pci_device_load(&d->dev, f);
-    if (ret < 0)
-        return ret;
-    if (version_id >= 3) {
-        for (i = 0; i < 4; i++)
-            d->pci_irq_levels[i] = qemu_get_be32(f);
+static const VMStateDescription vmstate_piix3 = {
+    .name = "PIIX3",
+    .version_id = 3,
+    .minimum_version_id = 2,
+    .minimum_version_id_old = 2,
+    .fields      = (VMStateField []) {
+        VMSTATE_PCI_DEVICE(dev, PIIX3State),
+        VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
+        VMSTATE_END_OF_LIST()
     }
-    return 0;
-}
+};
 
 static int piix3_initfn(PCIDevice *dev)
 {

@@ -351,7 +335,7 @@ static int piix3_initfn(PCIDevice *dev)
     uint8_t *pci_conf;
 
     isa_bus_new(&d->dev.qdev);
-    register_savevm("PIIX3", 0, 3, piix3_save, piix3_load, d);
+    vmstate_register(0, &vmstate_piix3, d);
 
     pci_conf = d->dev.config;
     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);

Signature · 1 line

1.6.2.5

Juan Quintela

author

2009-08-28 13:35 UTC #17 lore raw

[Qemu-devel] Re: [PATCH 00/16] *** SUBJECT HERE ***

In reply to Juan Quintela

Quoted 1 line · Juan Quintela

*** BLURB HERE ***

for (i=0; i < 100000; i++)
I will rememeber to remove *~ flags before using the git-send-mail command

Sorry, Juan.

Quoted 38 lines

Juan Quintela (16):
piix4 don't use pci_irq_levels at all
Split piix4 support from piix_pci.c
low_set_irq is not used anywhere
Use PCII440FXState instead of generic PCIDevice Move smm_enabled and isa_memory_mappings to PCII440FXState We want the argument pass to set_irq to be opaque Create PIIX3State instead of using PCIDevice for PIIX3 Introduce PIIX3IrqState for piix3 irq's state Fold piix3_init() intto i440fx_init
We can add piix3_dev now to PIIX3IrqState
Save irq_state into PCII440FXState pci_irq_levels[] belong to PIIX3State
Update SaveVM versions
VMState: Fix sub-structs versioning
i440fx: use new vmstate infrastructure
piix3: use new vmstate infrastructure
 Makefile.target    |    2 +-
 hw/apb_pci.c       |    4 +-
 hw/grackle_pci.c   |    4 +-
 hw/gt64xxx.c       |    3 +-
 hw/pc.c            |    5 +-
 hw/pc.h            |   11 ++-
 hw/pci.c           |    8 +-
 hw/pci.h           |    6 +-
 hw/piix4.c         |  128 ++++++++++++++++++++++++
 hw/piix_pci.c      |  275 +++++++++++++++++++++-------------------------------
 hw/ppc4xx_pci.c    |    4 +-
 hw/ppce500_pci.c   |    4 +-
 hw/prep_pci.c      |    4 +-
 hw/r2d.c           |    4 +-
 hw/sh_pci.c        |    4 +-
 hw/unin_pci.c      |    4 +-
 hw/versatile_pci.c |    4 +-
 savevm.c           |    2 +-
 18 files changed, 284 insertions(+), 192 deletions(-)
 create mode 100644 hw/piix4.c