unicore32: resend patches after machine related files

new file mode 100644
index 0000000..fa11eba
@@ -0,0 +1,104 @@
+/*
+ * linux/arch/unicore32/include/mach/PKUnity.h
+ *
+ * Code specific to PKUnity SoC and UniCore ISA
+ *
+ * Copyright (C) 2001-2010 GUAN Xue-tao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* Be sure that virtual mapping is defined right */
+#ifndef __MACH_PUV3_HARDWARE_H__
+#error You must include hardware.h not PKUnity.h
+#endif
+
+#include "bitfield.h"
+
+/*
+ * Memory Definitions
+ */
+#define PKUNITY_SDRAM_BASE		0x00000000 /* 0x00000000 - 0x7FFFFFFF 2GB */
+#define PKUNITY_IOSPACE_BASE            0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */
+#define PKUNITY_PCI_BASE		0x80000000 /* 0x80000000 - 0xBFFFFFFF 1GB */
+#include "regs-pci.h"
+#define PKUNITY_BOOT_ROM2_BASE		0xF4000000 /* 0xF4000000 - 0xF7FFFFFF 64MB */
+#define PKUNITY_BOOT_SRAM2_BASE		0xF8000000 /* 0xF8000000 - 0xFBFFFFFF 64MB */
+#define PKUNITY_BOOT_FLASH_BASE		0xFC000000 /* 0xFC000000 - 0xFFFFFFFF 64MB */
+
+/*
+ * PKUNITY Memory Map Addresses: 0x0D000000 - 0x0EFFFFFF (32MB)
+ */
+#define PKUNITY_UVC_MMAP_BASE		0x0D000000 /* 0x0D000000 - 0x0DFFFFFF 16MB */
+#define PKUNITY_UVC_MMAP_SIZE		0x01000000 /* 16MB */
+#define PKUNITY_UNIGFX_MMAP_BASE        0x0E000000 /* 0x0E000000 - 0x0EFFFFFF 16MB */
+#define PKUNITY_UNIGFX_MMAP_SIZE        0x01000000 /* 16MB */
+
+/*
+ * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB)
+ */
+/* PCI Configuration regs */
+#define PKUNITY_PCICFG_BASE             0x80000000 /* 0x80000000 - 0x8000000B 12B */
+/* PCI Bridge Base */
+#define PKUNITY_PCIBRI_BASE             0x80010000 /* 0x80010000 - 0x80010250 592B */
+/* PCI Legacy IO */
+#define PKUNITY_PCILIO_BASE             0x80030000 /* 0x80030000 - 0x8003FFFF 64KB */
+/* PCI AHB-PCI MEM-mapping */
+#define PKUNITY_PCIMEM_BASE             0x90000000 /* 0x90000000 - 0x97FFFFFF 128MB */
+/* PCI PCI-AHB MEM-mapping */
+#define PKUNITY_PCIAHB_BASE             0x98000000 /* 0x98000000 - 0x9FFFFFFF 128MB */
+
+/*
+ * PKUNITY System Bus Addresses (AHB): 0xC0000000 - 0xEDFFFFFF (640MB)
+ */
+/* AHB-0 is DDR2 SDRAM */
+/* AHB-1 is PCI Space */
+#define PKUNITY_ARBITER_BASE		0xC0000000 /* AHB-2 */
+#define PKUNITY_DDR2CTRL_BASE		0xC0100000 /* AHB-3 */
+#define PKUNITY_DMAC_BASE		0xC0200000 /* AHB-4 */
+#include "regs-dmac.h"
+#define PKUNITY_UMAL_BASE		0xC0300000 /* AHB-5 */
+#include "regs-umal.h"
+#define PKUNITY_USB_BASE		0xC0400000 /* AHB-6 */
+#define PKUNITY_SATA_BASE		0xC0500000 /* AHB-7 */
+#define PKUNITY_SMC_BASE		0xC0600000 /* AHB-8 */
+/* AHB-9 is for APB bridge */
+#define PKUNITY_MME_BASE		0xC0700000 /* AHB-10 */
+#define PKUNITY_UNIGFX_BASE		0xC0800000 /* AHB-11 */
+#include "regs-unigfx.h"
+#define PKUNITY_NAND_BASE		0xC0900000 /* AHB-12 */
+#include "regs-nand.h"
+#define PKUNITY_H264D_BASE		0xC0A00000 /* AHB-13 */
+#define PKUNITY_H264E_BASE		0xC0B00000 /* AHB-14 */
+
+/*
+ * PKUNITY Peripheral Bus Addresses (APB): 0xEE000000 - 0xEFFFFFFF (128MB)
+ */
+#define PKUNITY_UART0_BASE		0xEE000000 /* APB-0 */
+#define PKUNITY_UART1_BASE		0xEE100000 /* APB-1 */
+#include "regs-uart.h"
+#define PKUNITY_I2C_BASE		0xEE200000 /* APB-2 */
+#include "regs-i2c.h"
+#define PKUNITY_SPI_BASE		0xEE300000 /* APB-3 */
+#include "regs-spi.h"
+#define PKUNITY_AC97_BASE		0xEE400000 /* APB-4 */
+#include "regs-ac97.h"
+#define PKUNITY_GPIO_BASE		0xEE500000 /* APB-5 */
+#include "regs-gpio.h"
+#define PKUNITY_INTC_BASE		0xEE600000 /* APB-6 */
+#include "regs-intc.h"
+#define PKUNITY_RTC_BASE		0xEE700000 /* APB-7 */
+#include "regs-rtc.h"
+#define PKUNITY_OST_BASE		0xEE800000 /* APB-8 */
+#include "regs-ost.h"
+#define PKUNITY_RESETC_BASE		0xEE900000 /* APB-9 */
+#include "regs-resetc.h"
+#define PKUNITY_PM_BASE			0xEEA00000 /* APB-10 */
+#include "regs-pm.h"
+#define PKUNITY_PS2_BASE		0xEEB00000 /* APB-11 */
+#include "regs-ps2.h"
+#define PKUNITY_SDC_BASE		0xEEC00000 /* APB-12 */
+#include "regs-sdc.h"
+

new file mode 100644
index 0000000..128a702
@@ -0,0 +1,24 @@
+/*
+ * linux/arch/unicore32/include/mach/bitfield.h
+ *
+ * Code specific to PKUnity SoC and UniCore ISA
+ *
+ * Copyright (C) 2001-2010 GUAN Xue-tao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_PUV3_BITFIELD_H__
+#define __MACH_PUV3_BITFIELD_H__
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+#define FIELD(val, vmask, vshift)	(((val) & ((UData(1) << (vmask)) - 1)) << (vshift))
+#define FMASK(vmask, vshift)		(((UData(1) << (vmask)) - 1) << (vshift))
+
+#endif /* __MACH_PUV3_BITFIELD_H__ */

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new file mode 100644
index 0000000..ce299bf
@@ -0,0 +1,32 @@
+/*
+ * PKUnity AC97 Registers
+ */
+
+#define PKUNITY_AC97_CONR		__REG(PKUNITY_AC97_BASE + 0x0000)
+#define PKUNITY_AC97_OCR		__REG(PKUNITY_AC97_BASE + 0x0004)
+#define PKUNITY_AC97_ICR		__REG(PKUNITY_AC97_BASE + 0x0008)
+#define PKUNITY_AC97_CRAC		__REG(PKUNITY_AC97_BASE + 0x000C)
+#define PKUNITY_AC97_INTR		__REG(PKUNITY_AC97_BASE + 0x0010)
+#define PKUNITY_AC97_INTRSTAT		__REG(PKUNITY_AC97_BASE + 0x0014)
+#define PKUNITY_AC97_INTRCLEAR		__REG(PKUNITY_AC97_BASE + 0x0018)
+#define PKUNITY_AC97_ENABLE		__REG(PKUNITY_AC97_BASE + 0x001C)
+#define PKUNITY_AC97_OUT_FIFO		__REG(PKUNITY_AC97_BASE + 0x0020)
+#define PKUNITY_AC97_IN_FIFO		__REG(PKUNITY_AC97_BASE + 0x0030)
+
+#define AC97_CODEC_REG(v)               FIELD((v), 7, 16)
+#define AC97_CODEC_VAL(v)               FIELD((v), 16, 0)
+#define AC97_CODEC_WRITECOMPLETE        FIELD(1, 1, 2)
+
+/*
+ * VAR PLAY SAMPLE RATE
+ */
+#define AC97_CMD_VPSAMPLE		(FIELD(3, 2, 16) | FIELD(3, 2, 0))
+
+/*
+ * FIX CAPTURE SAMPLE RATE
+ */
+#define AC97_CMD_FCSAMPLE		FIELD(7, 3, 0)
+
+#define AC97_CMD_RESET			FIELD(1, 1, 0)
+#define AC97_CMD_ENABLE			FIELD(1, 1, 0)
+#define AC97_CMD_DISABLE		FIELD(0, 1, 0)

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new file mode 100644
index 0000000..409ae47
@@ -0,0 +1,28 @@
+/*
+ * PKUNITY Interrupt Controller (INTC) Registers
+ */
+/*
+ * INTC Level Reg INTC_ICLR.
+ */
+#define INTC_ICLR	__REG(PKUNITY_INTC_BASE + 0x0000)
+/*
+ * INTC Mask Reg INTC_ICMR.
+ */
+#define INTC_ICMR	__REG(PKUNITY_INTC_BASE + 0x0004)
+/*
+ * INTC Pending Reg INTC_ICPR.
+ */
+#define INTC_ICPR	__REG(PKUNITY_INTC_BASE + 0x0008)
+/*
+ * INTC IRQ Pending Reg INTC_ICIP.
+ */
+#define INTC_ICIP	__REG(PKUNITY_INTC_BASE + 0x000C)
+/*
+ * INTC REAL Pending Reg INTC_ICFP.
+ */
+#define INTC_ICFP	__REG(PKUNITY_INTC_BASE + 0x0010)
+/*
+ * INTC Control Reg INTC_ICCR.
+ */
+#define INTC_ICCR	__REG(PKUNITY_INTC_BASE + 0x0014)
+

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new file mode 100644
index 0000000..7da2071
@@ -0,0 +1,20 @@
+/*
+ * PKUnity PS2 Controller Registers
+ */
+/*
+ * the same as I8042_DATA_REG PS2_DATA
+ */
+#define PS2_DATA	__REG(PKUNITY_PS2_BASE + 0x0060)
+/*
+ * the same as I8042_COMMAND_REG PS2_COMMAND
+ */
+#define PS2_COMMAND	__REG(PKUNITY_PS2_BASE + 0x0064)
+/*
+ * the same as I8042_STATUS_REG PS2_STATUS
+ */
+#define PS2_STATUS	__REG(PKUNITY_PS2_BASE + 0x0064)
+/*
+ * counter reg PS2_CNT
+ */
+#define PS2_CNT		__REG(PKUNITY_PS2_BASE + 0x0068)
+

new file mode 100644
index 0000000..1763989
@@ -0,0 +1,34 @@
+/*
+ * PKUnity Reset Controller (RC) Registers
+ */
+/*
+ * Software Reset Register
+ */
+#define RESETC_SWRR	__REG(PKUNITY_RESETC_BASE + 0x0000)
+/*
+ * Reset Status Register
+ */
+#define RESETC_RSSR	__REG(PKUNITY_RESETC_BASE + 0x0004)
+
+/*
+ * Software Reset Bit
+ */
+#define RESETC_SWRR_SRB		FIELD(1, 1, 0)
+
+/*
+ * Hardware Reset
+ */
+#define RESETC_RSSR_HWR		FIELD(1, 1, 0)
+/*
+ * Software Reset
+ */
+#define RESETC_RSSR_SWR		FIELD(1, 1, 1)
+/*
+ * Watchdog Reset
+ */
+#define RESETC_RSSR_WDR		FIELD(1, 1, 2)
+/*
+ * Sleep Mode Reset
+ */
+#define RESETC_RSSR_SMR		FIELD(1, 1, 3)
+

new file mode 100644
index 0000000..155e3875
@@ -0,0 +1,37 @@
+/*
+ * PKUnity Real-Time Clock (RTC) control registers
+ */
+/*
+ * RTC Alarm Reg RTC_RTAR
+ */
+#define RTC_RTAR	__REG(PKUNITY_RTC_BASE + 0x0000)
+/*
+ * RTC Count Reg RTC_RCNR
+ */
+#define RTC_RCNR	__REG(PKUNITY_RTC_BASE + 0x0004)
+/*
+ * RTC Trim Reg RTC_RTTR
+ */
+#define RTC_RTTR	__REG(PKUNITY_RTC_BASE + 0x0008)
+/*
+ * RTC Status Reg RTC_RTSR
+ */
+#define RTC_RTSR	__REG(PKUNITY_RTC_BASE + 0x0010)
+
+/*
+ * ALarm detected RTC_RTSR_AL
+ */
+#define RTC_RTSR_AL		FIELD(1, 1, 0)
+/*
+ * 1 Hz clock detected RTC_RTSR_HZ
+ */
+#define RTC_RTSR_HZ		FIELD(1, 1, 1)
+/*
+ * ALarm interrupt Enable RTC_RTSR_ALE
+ */
+#define RTC_RTSR_ALE		FIELD(1, 1, 2)
+/*
+ * 1 Hz clock interrupt Enable RTC_RTSR_HZE
+ */
+#define RTC_RTSR_HZE		FIELD(1, 1, 3)
+

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new file mode 100644
index 0000000..9fa6b19
@@ -0,0 +1,3 @@
+/*
+ * PKUnity Universal Asynchronous Receiver/Transmitter (UART) Registers
+ */

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new file mode 100644
index 0000000..6a7e8b3
@@ -0,0 +1,70 @@
+/*
+ * Code specific to PKUnity SoC and UniCore ISA
+ *
+ *	Maintained by GUAN Xue-tao <[email protected]>
+ *	Copyright (C) 2001-2011 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _I8042_UNICORE32_H
+#define _I8042_UNICORE32_H
+
+#include <mach/hardware.h>
+
+/*
+ * Names.
+ */
+#define I8042_KBD_PHYS_DESC "isa0060/serio0"
+#define I8042_AUX_PHYS_DESC "isa0060/serio1"
+#define I8042_MUX_PHYS_DESC "isa0060/serio%d"
+
+/*
+ * IRQs.
+ */
+#define I8042_KBD_IRQ           IRQ_PS2_KBD
+#define I8042_AUX_IRQ           IRQ_PS2_AUX
+
+/*
+ * Register numbers.
+ */
+#define I8042_COMMAND_REG	((unsigned long)&PS2_COMMAND)
+#define I8042_STATUS_REG	((unsigned long)&PS2_STATUS)
+#define I8042_DATA_REG		((unsigned long)&PS2_DATA)
+
+static inline int i8042_read_data(void)
+{
+	return inb(I8042_DATA_REG);
+}
+
+static inline int i8042_read_status(void)
+{
+	return inb(I8042_STATUS_REG);
+}
+
+static inline void i8042_write_data(int val)
+{
+	outb(val, I8042_DATA_REG);
+}
+
+static inline void i8042_write_command(int val)
+{
+	outb(val, I8042_COMMAND_REG);
+}
+
+static inline int i8042_platform_init(void)
+{
+	if (!request_region(I8042_DATA_REG, 16, "i8042"))
+		return -EBUSY;
+
+	i8042_reset = 1;
+	return 0;
+}
+
+static inline void i8042_platform_exit(void)
+{
+	release_region(I8042_DATA_REG, 16);
+}
+
+#endif /* _I8042_UNICORE32_H */

index ac1d759..3452708 100644
@@ -26,6 +26,8 @@
 #include "i8042-sparcio.h"
 #elif defined(CONFIG_X86) || defined(CONFIG_IA64)
 #include "i8042-x86ia64io.h"
+#elif defined(CONFIG_UNICORE32)
+#include "i8042-unicore32io.h"
 #else
 #include "i8042-io.h"
 #endif

index 8090d76..8bb4b81 100644
@@ -66,11 +66,6 @@ puv3_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
 static struct clock_event_device ckevt_puv3_osmr0 = {
 	.name		= "osmr0",
 	.features	= CLOCK_EVT_FEAT_ONESHOT,
-#ifdef CONFIG_ARCH_FPGA
-	.shift		= 18, /* correct shift val: 16, but warn_on_slowpath */
-#else
-	.shift          = 30,
-#endif
 	.rating		= 200,
 	.set_next_event	= puv3_osmr0_set_next_event,
 	.set_mode	= puv3_osmr0_set_mode,

@@ -101,8 +96,8 @@ void __init time_init(void)
 	OST_OIER = 0;		/* disable any timer interrupts */
 	OST_OSSR = 0;		/* clear status on all timers */
 
-	ckevt_puv3_osmr0.mult =
-		div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_puv3_osmr0.shift);
+	clockevents_calc_mult_shift(&ckevt_puv3_osmr0, CLOCK_TICK_RATE, 5);
+
 	ckevt_puv3_osmr0.max_delta_ns =
 		clockevent_delta2ns(0x7fffffff, &ckevt_puv3_osmr0);
 	ckevt_puv3_osmr0.min_delta_ns =

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index 6a7e8b3..2cdd872 100644
@@ -29,33 +29,36 @@
 /*
  * Register numbers.
  */
-#define I8042_COMMAND_REG	((unsigned long)&PS2_COMMAND)
-#define I8042_STATUS_REG	((unsigned long)&PS2_STATUS)
-#define I8042_DATA_REG		((unsigned long)&PS2_DATA)
+#define I8042_COMMAND_REG	((volatile void __iomem *)&PS2_COMMAND)
+#define I8042_STATUS_REG	((volatile void __iomem *)&PS2_STATUS)
+#define I8042_DATA_REG		((volatile void __iomem *)&PS2_DATA)
+
+#define I8042_REGION_START	(resource_size_t)(&PS2_DATA)
+#define I8042_REGION_SIZE	(resource_size_t)(16)
 
 static inline int i8042_read_data(void)
 {
-	return inb(I8042_DATA_REG);
+	return readb(I8042_DATA_REG);
 }
 
 static inline int i8042_read_status(void)
 {
-	return inb(I8042_STATUS_REG);
+	return readb(I8042_STATUS_REG);
 }
 
 static inline void i8042_write_data(int val)
 {
-	outb(val, I8042_DATA_REG);
+	writeb(val, I8042_DATA_REG);
 }
 
 static inline void i8042_write_command(int val)
 {
-	outb(val, I8042_COMMAND_REG);
+	writeb(val, I8042_COMMAND_REG);
 }
 
 static inline int i8042_platform_init(void)
 {
-	if (!request_region(I8042_DATA_REG, 16, "i8042"))
+	if (!request_region(I8042_REGION_START, I8042_REGION_SIZE, "i8042"))
 		return -EBUSY;
 
 	i8042_reset = 1;

@@ -64,7 +67,7 @@ static inline int i8042_platform_init(void)
 
 static inline void i8042_platform_exit(void)
 {
-	release_region(I8042_DATA_REG, 16);
+	release_region(I8042_REGION_START, I8042_REGION_SIZE);
 }
 
 #endif /* _I8042_UNICORE32_H */

index 632cef7..08b8d42 100644
@@ -54,7 +54,7 @@ pgd_t *get_pgd_slow(struct mm_struct *mm)
 		if (!new_pmd)
 			goto no_pmd;
 
-		new_pte = pte_alloc_map(mm, new_pmd, 0);
+		new_pte = pte_alloc_map(mm, NULL, new_pmd, 0);
 		if (!new_pte)
 			goto no_pte;
 

index 2cdd872..620b040 100644
@@ -58,7 +58,7 @@ static inline void i8042_write_command(int val)
 
 static inline int i8042_platform_init(void)
 {
-	if (!request_region(I8042_REGION_START, I8042_REGION_SIZE, "i8042"))
+	if (!request_mem_region(I8042_REGION_START, I8042_REGION_SIZE, "i8042"))
 		return -EBUSY;
 
 	i8042_reset = 1;

@@ -67,7 +67,7 @@ static inline int i8042_platform_init(void)
 
 static inline void i8042_platform_exit(void)
 {
-	release_region(I8042_REGION_START, I8042_REGION_SIZE);
+	release_mem_region(I8042_REGION_START, I8042_REGION_SIZE);
 }
 
 #endif /* _I8042_UNICORE32_H */

index 3aaa41e..2716f14 100644
@@ -13,6 +13,7 @@
 #ifndef __UNICORE_GPIO_H__
 #define __UNICORE_GPIO_H__
 
+#include <linux/io.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
 #include <asm-generic/gpio.h>

@@ -66,7 +67,7 @@
 static inline int gpio_get_value(unsigned gpio)
 {
 	if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
-		return GPIO_GPLR & GPIO_GPIO(gpio);
+		return readl(GPIO_GPLR) & GPIO_GPIO(gpio);
 	else
 		return __gpio_get_value(gpio);
 }

@@ -75,9 +76,9 @@ static inline void gpio_set_value(unsigned gpio, int value)
 {
 	if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
 		if (value)
-			GPIO_GPSR = GPIO_GPIO(gpio);
+			writel(GPIO_GPIO(gpio), GPIO_GPSR);
 		else
-			GPIO_GPCR = GPIO_GPIO(gpio);
+			writel(GPIO_GPIO(gpio), GPIO_GPCR);
 	else
 		__gpio_set_value(gpio, value);
 }

@@ -86,7 +87,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
 
 static inline unsigned gpio_to_irq(unsigned gpio)
 {
-	if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & GPIO_GPIR))
+	if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & readl(GPIO_GPIR)))
 		return IRQ_GPIOLOW0 + gpio;
 	else
 		return IRQ_GPIO0 + gpio;

index 3e3224a..d655c1b 100644
@@ -35,7 +35,14 @@ extern int puv3_request_dma(char *name,
 
 extern void puv3_free_dma(int dma_ch);
 
-#define puv3_stop_dma(ch)		(DMAC_CONFIG(ch) &= ~DMAC_CONFIG_EN)
-#define puv3_resume_dma(ch)             (DMAC_CONFIG(ch) |= DMAC_CONFIG_EN)
+static inline void puv3_stop_dma(int ch)
+{
+	writel(readl(DMAC_CONFIG(ch)) & ~DMAC_CONFIG_EN, DMAC_CONFIG(ch));
+}
+
+static inline void puv3_resume_dma(int ch)
+{
+	writel(readl(DMAC_CONFIG(ch)) | DMAC_CONFIG_EN, DMAC_CONFIG(ch));
+}
 
 #endif /* __MACH_PUV3_DMA_H__ */

index c7d3dd6..b71405a 100644
@@ -22,13 +22,7 @@
 
 #ifndef __ASSEMBLY__
 
-# define __REG(x)	(*((volatile unsigned long *)io_p2v(x)))
-# define __PREG(x)	(io_v2p((unsigned long)&(x)))
-
-#else
-
-# define __REG(x)	io_p2v(x)
-# define __PREG(x)	io_v2p(x)
+# define __REG(x)	(void __iomem *)io_p2v(x)
 
 #endif
 

index 80323db..18d4563 100644
@@ -20,6 +20,7 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 #include <linux/delay.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 

@@ -152,28 +153,29 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 		if (ret)
 			return ret;
 
-		if (PM_PLLVGACFG == pll_vgacfg)
+		if (readl(PM_PLLVGACFG) == pll_vgacfg)
 			return 0;
 
 		/* set pll vga cfg reg. */
-		PM_PLLVGACFG = pll_vgacfg;
+		writel(pll_vgacfg, PM_PLLVGACFG);
 
-		PM_PMCR = PM_PMCR_CFBVGA;
-		while ((PM_PLLDFCDONE & PM_PLLDFCDONE_VGADFC)
+		writel(PM_PMCR_CFBVGA, PM_PMCR);
+		while ((readl(PM_PLLDFCDONE) & PM_PLLDFCDONE_VGADFC)
 				!= PM_PLLDFCDONE_VGADFC)
 			udelay(100); /* about 1ms */
 
 		/* set div cfg reg. */
-		PM_PCGR |= PM_PCGR_VGACLK;
+		writel(readl(PM_PCGR) | PM_PCGR_VGACLK, PM_PCGR);
 
-		PM_DIVCFG = (PM_DIVCFG & ~PM_DIVCFG_VGACLK_MASK)
-				| PM_DIVCFG_VGACLK(pll_vgadiv);
+		writel((readl(PM_DIVCFG) & ~PM_DIVCFG_VGACLK_MASK)
+				| PM_DIVCFG_VGACLK(pll_vgadiv), PM_DIVCFG);
 
-		PM_SWRESET |= PM_SWRESET_VGADIV;
-		while ((PM_SWRESET & PM_SWRESET_VGADIV) == PM_SWRESET_VGADIV)
+		writel(readl(PM_SWRESET) | PM_SWRESET_VGADIV, PM_SWRESET);
+		while ((readl(PM_SWRESET) & PM_SWRESET_VGADIV)
+				== PM_SWRESET_VGADIV)
 			udelay(100); /* 65536 bclk32, about 320us */
 
-		PM_PCGR &= ~PM_PCGR_VGACLK;
+		writel(readl(PM_PCGR) & ~PM_PCGR_VGACLK, PM_PCGR);
 	}
 #ifdef CONFIG_CPU_FREQ
 	if (clk == &clk_mclk_clk) {

@@ -323,15 +325,15 @@ struct {
 static int __init clk_init(void)
 {
 #ifdef CONFIG_PUV3_PM
-	u32 pllrate, divstatus = PM_DIVSTATUS;
-	u32 pcgr_val = PM_PCGR;
+	u32 pllrate, divstatus = readl(PM_DIVSTATUS);
+	u32 pcgr_val = readl(PM_PCGR);
 	int i;
 
 	pcgr_val |= PM_PCGR_BCLKMME | PM_PCGR_BCLKH264E | PM_PCGR_BCLKH264D
 			| PM_PCGR_HECLK | PM_PCGR_HDCLK;
-	PM_PCGR = pcgr_val;
+	writel(pcgr_val, PM_PCGR);
 
-	pllrate = PM_PLLSYSSTATUS;
+	pllrate = readl(PM_PLLSYSSTATUS);
 
 	/* lookup pmclk_table */
 	clk_mclk_clk.rate = 0;

@@ -346,7 +348,7 @@ static int __init clk_init(void)
 		clk_bclk32_clk.rate = clk_mclk_clk.rate /
 			(((divstatus & 0x0000f000) >> 12) + 1);
 
-	pllrate = PM_PLLDDRSTATUS;
+	pllrate = readl(PM_PLLDDRSTATUS);
 
 	/* lookup pddr_table */
 	clk_ddr_clk.rate = 0;

@@ -357,7 +359,7 @@ static int __init clk_init(void)
 		}
 	}
 
-	pllrate = PM_PLLVGASTATUS;
+	pllrate = readl(PM_PLLVGASTATUS);
 
 	/* lookup pvga_table */
 	clk_vga_clk.rate = 0;

index b8dcc25..ae441bc 100644
@@ -16,6 +16,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/errno.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
 #include <asm/irq.h>

@@ -94,15 +95,16 @@ EXPORT_SYMBOL(puv3_free_dma);
 
 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
-	int i, dint = DMAC_ITCSR;
+	int i, dint;
 
+	dint = readl(DMAC_ITCSR);
 	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 		if (dint & DMAC_CHANNEL(i)) {
 			struct dma_channel *channel = &dma_channels[i];
 
 			/* Clear TC interrupt of channel i */
-			DMAC_ITCCR = DMAC_CHANNEL(i);
-			DMAC_ITCCR = 0;
+			writel(DMAC_CHANNEL(i), DMAC_ITCCR);
+			writel(0, DMAC_ITCCR);
 
 			if (channel->name && channel->irq_handler) {
 				channel->irq_handler(i, channel->data);

@@ -121,15 +123,16 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 
 static irqreturn_t dma_err_handler(int irq, void *dev_id)
 {
-	int i, dint = DMAC_IESR;
+	int i, dint;
 
+	dint = readl(DMAC_IESR);
 	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
 		if (dint & DMAC_CHANNEL(i)) {
 			struct dma_channel *channel = &dma_channels[i];
 
 			/* Clear Err interrupt of channel i */
-			DMAC_IECR = DMAC_CHANNEL(i);
-			DMAC_IECR = 0;
+			writel(DMAC_CHANNEL(i), DMAC_IECR);
+			writel(0, DMAC_IECR);
 
 			if (channel->name && channel->err_handler) {
 				channel->err_handler(i, channel->data);

index 4cb2830..cb12ec3 100644
@@ -52,15 +52,15 @@ device_initcall(puv3_gpio_leds_init);
 
 static int puv3_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-	return GPIO_GPLR & GPIO_GPIO(offset);
+	return readl(GPIO_GPLR) & GPIO_GPIO(offset);
 }
 
 static void puv3_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
 	if (value)
-		GPIO_GPSR = GPIO_GPIO(offset);
+		writel(GPIO_GPIO(offset), GPIO_GPSR);
 	else
-		GPIO_GPCR = GPIO_GPIO(offset);
+		writel(GPIO_GPIO(offset), GPIO_GPCR);
 }
 
 static int puv3_direction_input(struct gpio_chip *chip, unsigned offset)

@@ -68,7 +68,7 @@ static int puv3_direction_input(struct gpio_chip *chip, unsigned offset)
 	unsigned long flags;
 
 	local_irq_save(flags);
-	GPIO_GPDR &= ~GPIO_GPIO(offset);
+	writel(readl(GPIO_GPDR) & ~GPIO_GPIO(offset), GPIO_GPDR);
 	local_irq_restore(flags);
 	return 0;
 }

@@ -80,7 +80,7 @@ static int puv3_direction_output(struct gpio_chip *chip, unsigned offset,
 
 	local_irq_save(flags);
 	puv3_gpio_set(chip, offset, value);
-	GPIO_GPDR |= GPIO_GPIO(offset);
+	writel(readl(GPIO_GPDR) | GPIO_GPIO(offset), GPIO_GPDR);
 	local_irq_restore(flags);
 	return 0;
 }

@@ -97,7 +97,7 @@ static struct gpio_chip puv3_gpio_chip = {
 
 void __init puv3_init_gpio(void)
 {
-	GPIO_GPDR = GPIO_DIR;
+	writel(GPIO_DIR, GPIO_GPDR);
 #if	defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919)	\
 	|| defined(CONFIG_PUV3_DB0913)
 	gpio_set_value(GPO_WIFI_EN, 1);

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index 8d4a273..ba401df 100644
@@ -125,9 +125,9 @@ void machine_restart(char *cmd)
 		/* Jump into ROM at address 0xffff0000 */
 		cpu_reset(VECTORS_BASE);
 	} else {
-		PM_PLLSYSCFG = 0x00002001; /* cpu clk = 250M */
-		PM_PLLDDRCFG = 0x00100800; /* ddr clk =  44M */
-		PM_PLLVGACFG = 0x00002001; /* vga clk = 250M */
+		writel(0x00002001, PM_PLLSYSCFG); /* cpu clk = 250M */
+		writel(0x00100800, PM_PLLDDRCFG); /* ddr clk =  44M */
+		writel(0x00002001, PM_PLLVGACFG); /* vga clk = 250M */
 
 		/* Use on-chip reset capability */
 		/* following instructions must be in one icache line */

@@ -141,10 +141,10 @@ void machine_restart(char *cmd)
 			"	nop; nop; nop\n\t"
 			/* prefetch 3 instructions at most */
 			:
-			: "r" ((unsigned long)&PM_PMCR),
+			: "r" (PM_PMCR),
 			  "r" (PM_PMCR_CFBSYS | PM_PMCR_CFBDDR
 				| PM_PMCR_CFBVGA),
-			  "r" ((unsigned long)&RESETC_SWRR),
+			  "r" (RESETC_SWRR),
 			  "r" (RESETC_SWRR_SRB)
 			: "r0", "memory");
 	}

index 26cc52b..6edf928 100644
@@ -36,7 +36,7 @@
  */
 unsigned long long sched_clock(void)
 {
-	unsigned long long v = cnt32_to_63(OST_OSCR);
+	unsigned long long v = cnt32_to_63(readl(OST_OSCR));
 
 	/* original conservative method, but overflow frequently
 	 * v *= NSEC_PER_SEC >> 12;

@@ -187,15 +187,15 @@ static void puv3_cpu_pm_restore(unsigned long *sleep_save)
 static int puv3_cpu_pm_prepare(void)
 {
 	/* set resume return address */
-	PM_DIVCFG = virt_to_phys(puv3_cpu_resume);
+	writel(virt_to_phys(puv3_cpu_resume), PM_DIVCFG);
 	return 0;
 }
 
 static void puv3_cpu_pm_enter(suspend_state_t state)
 {
 	/* Clear reset status */
-	RESETC_RSSR = RESETC_RSSR_HWR | RESETC_RSSR_WDR
-			| RESETC_RSSR_SMR | RESETC_RSSR_SWR;
+	writel(RESETC_RSSR_HWR | RESETC_RSSR_WDR
+			| RESETC_RSSR_SMR | RESETC_RSSR_SWR, RESETC_RSSR);
 
 	switch (state) {
 /*	case PM_SUSPEND_ON:

@@ -242,7 +242,7 @@ void puv3_ps2_init(void)
 	struct clk *bclk32;
 
 	bclk32 = clk_get(NULL, "BUS32_CLK");
-	PS2_CNT = clk_get_rate(bclk32) / 200000; /* should > 5us */
+	writel(clk_get_rate(bclk32) / 200000, PS2_CNT); /* should > 5us */
 }
 
 void __init puv3_core_init(void)

index 5e4db41..c5f0682 100644
@@ -41,7 +41,7 @@ static irqreturn_t puv3_rtc_alarmirq(int irq, void *id)
 {
 	struct rtc_device *rdev = id;
 
-	RTC_RTSR |= RTC_RTSR_AL;
+	writel(readl(RTC_RTSR) | RTC_RTSR_AL, RTC_RTSR);
 	rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
 	return IRQ_HANDLED;
 }

@@ -50,7 +50,7 @@ static irqreturn_t puv3_rtc_tickirq(int irq, void *id)
 {
 	struct rtc_device *rdev = id;
 
-	RTC_RTSR |= RTC_RTSR_HZ;
+	writel(readl(RTC_RTSR) | RTC_RTSR_HZ, RTC_RTSR);
 	rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
 	return IRQ_HANDLED;
 }

@@ -62,12 +62,12 @@ static void puv3_rtc_setaie(int to)
 
 	pr_debug("%s: aie=%d\n", __func__, to);
 
-	tmp = RTC_RTSR & ~RTC_RTSR_ALE;
+	tmp = readl(RTC_RTSR) & ~RTC_RTSR_ALE;
 
 	if (to)
 		tmp |= RTC_RTSR_ALE;
 
-	RTC_RTSR = tmp;
+	writel(tmp, RTC_RTSR);
 }
 
 static int puv3_rtc_setpie(struct device *dev, int enabled)

@@ -77,12 +77,12 @@ static int puv3_rtc_setpie(struct device *dev, int enabled)
 	pr_debug("%s: pie=%d\n", __func__, enabled);
 
 	spin_lock_irq(&puv3_rtc_pie_lock);
-	tmp = RTC_RTSR & ~RTC_RTSR_HZE;
+	tmp = readl(RTC_RTSR) & ~RTC_RTSR_HZE;
 
 	if (enabled)
 		tmp |= RTC_RTSR_HZE;
 
-	RTC_RTSR = tmp;
+	writel(tmp, RTC_RTSR);
 	spin_unlock_irq(&puv3_rtc_pie_lock);
 
 	return 0;

@@ -97,7 +97,7 @@ static int puv3_rtc_setfreq(struct device *dev, int freq)
 
 static int puv3_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
 {
-	rtc_time_to_tm(RTC_RCNR, rtc_tm);
+	rtc_time_to_tm(readl(RTC_RCNR), rtc_tm);
 
 	pr_debug("read time %02x.%02x.%02x %02x/%02x/%02x\n",
 		 rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,

@@ -115,7 +115,7 @@ static int puv3_rtc_settime(struct device *dev, struct rtc_time *tm)
 		 tm->tm_hour, tm->tm_min, tm->tm_sec);
 
 	rtc_tm_to_time(tm, &rtc_count);
-	RTC_RCNR = rtc_count;
+	writel(rtc_count, RTC_RCNR);
 
 	return 0;
 }

@@ -124,9 +124,9 @@ static int puv3_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
 {
 	struct rtc_time *alm_tm = &alrm->time;
 
-	rtc_time_to_tm(RTC_RTAR, alm_tm);
+	rtc_time_to_tm(readl(RTC_RTAR), alm_tm);
 
-	alrm->enabled = RTC_RTSR & RTC_RTSR_ALE;
+	alrm->enabled = readl(RTC_RTSR) & RTC_RTSR_ALE;
 
 	pr_debug("read alarm %02x %02x.%02x.%02x %02x/%02x/%02x\n",
 		 alrm->enabled,

@@ -147,7 +147,7 @@ static int puv3_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 		 tm->tm_hour & 0xff, tm->tm_min & 0xff, tm->tm_sec);
 
 	rtc_tm_to_time(tm, &rtcalarm_count);
-	RTC_RTAR = rtcalarm_count;
+	writel(rtcalarm_count, RTC_RTAR);
 
 	puv3_rtc_setaie(alrm->enabled);
 

@@ -162,7 +162,7 @@ static int puv3_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 static int puv3_rtc_proc(struct device *dev, struct seq_file *seq)
 {
 	seq_printf(seq, "periodic_IRQ\t: %s\n",
-		     (RTC_RTSR & RTC_RTSR_HZE) ? "yes" : "no");
+		     (readl(RTC_RTSR) & RTC_RTSR_HZE) ? "yes" : "no");
 	return 0;
 }
 

@@ -222,13 +222,13 @@ static const struct rtc_class_ops puv3_rtcops = {
 static void puv3_rtc_enable(struct platform_device *pdev, int en)
 {
 	if (!en) {
-		RTC_RTSR &= ~RTC_RTSR_HZE;
+		writel(readl(RTC_RTSR) & ~RTC_RTSR_HZE, RTC_RTSR);
 	} else {
 		/* re-enable the device, and check it is ok */
 
-		if ((RTC_RTSR & RTC_RTSR_HZE) == 0) {
+		if ((readl(RTC_RTSR) & RTC_RTSR_HZE) == 0) {
 			dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
-			RTC_RTSR |= RTC_RTSR_HZE;
+			writel(readl(RTC_RTSR) | RTC_RTSR_HZE, RTC_RTSR);
 		}
 	}
 }

@@ -331,7 +331,7 @@ static int ticnt_save;
 static int puv3_rtc_suspend(struct platform_device *pdev, pm_message_t state)
 {
 	/* save RTAR for anyone using periodic interrupts */
-	ticnt_save = RTC_RTAR;
+	ticnt_save = readl(RTC_RTAR);
 	puv3_rtc_enable(pdev, 0);
 	return 0;
 }

@@ -339,7 +339,7 @@ static int puv3_rtc_suspend(struct platform_device *pdev, pm_message_t state)
 static int puv3_rtc_resume(struct platform_device *pdev)
 {
 	puv3_rtc_enable(pdev, 1);
-	RTC_RTAR = ticnt_save;
+	writel(ticnt_save, RTC_RTAR);
 	return 0;
 }
 #else

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index 620b040..73f5cc1 100644
@@ -29,11 +29,11 @@
 /*
  * Register numbers.
  */
-#define I8042_COMMAND_REG	((volatile void __iomem *)&PS2_COMMAND)
-#define I8042_STATUS_REG	((volatile void __iomem *)&PS2_STATUS)
-#define I8042_DATA_REG		((volatile void __iomem *)&PS2_DATA)
+#define I8042_COMMAND_REG	PS2_COMMAND
+#define I8042_STATUS_REG	PS2_STATUS
+#define I8042_DATA_REG		PS2_DATA
 
-#define I8042_REGION_START	(resource_size_t)(&PS2_DATA)
+#define I8042_REGION_START	(resource_size_t)(PS2_DATA)
 #define I8042_REGION_SIZE	(resource_size_t)(16)
 
 static inline int i8042_read_data(void)

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new file mode 100644
index 0000000..c5b28b4
@@ -0,0 +1,46 @@
+/*
+ * linux/arch/unicore32/include/asm/pci.h
+ *
+ * Code specific to PKUnity SoC and UniCore ISA
+ *
+ * Copyright (C) 2001-2010 GUAN Xue-tao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __UNICORE_PCI_H__
+#define __UNICORE_PCI_H__
+
+#ifdef __KERNEL__
+#include <asm-generic/pci-dma-compat.h>
+#include <asm-generic/pci.h>
+#include <mach/hardware.h> /* for PCIBIOS_MIN_* */
+
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+	/* No special bus mastering setup handling */
+}
+
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+	/* We don't do dynamic PCI IRQ allocation */
+}
+
+#ifdef CONFIG_PCI
+static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+					enum pci_dma_burst_strategy *strat,
+					unsigned long *strategy_parameter)
+{
+	*strat = PCI_DMA_BURST_INFINITY;
+	*strategy_parameter = ~0UL;
+}
+#endif
+
+#define HAVE_PCI_MMAP
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+	enum pci_mmap_state mmap_state, int write_combine);
+
+#endif /* __KERNEL__ */
+
+#endif

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index ade8bb8..baea93e 100644
@@ -95,9 +95,7 @@
 #define IRQ_SD_CD               IRQ_GPIO6 /* falling or rising trigger */
 
 #ifndef __ASSEMBLY__
-struct irqaction;
 struct pt_regs;
-extern void migrate_irqs(void);
 
 extern void asm_do_IRQ(unsigned int, struct pt_regs *);
 

index fa11eba..940e9ed 100644
@@ -21,7 +21,7 @@
  * Memory Definitions
  */
 #define PKUNITY_SDRAM_BASE		0x00000000 /* 0x00000000 - 0x7FFFFFFF 2GB */
-#define PKUNITY_IOSPACE_BASE            0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */
+#define PKUNITY_MMIO_BASE		0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */
 #define PKUNITY_PCI_BASE		0x80000000 /* 0x80000000 - 0xBFFFFFFF 1GB */
 #include "regs-pci.h"
 #define PKUNITY_BOOT_ROM2_BASE		0xF4000000 /* 0xF4000000 - 0xF7FFFFFF 64MB */

index 3fb7236..c7d3dd6 100644
@@ -17,8 +17,8 @@
 
 #include "PKUnity.h"
 
-#define io_p2v(x)	((x) - PKUNITY_IOSPACE_BASE)
-#define io_v2p(x)	((x) + PKUNITY_IOSPACE_BASE)
+#define io_p2v(x)	((x) - PKUNITY_MMIO_BASE)
+#define io_v2p(x)	((x) + PKUNITY_MMIO_BASE)
 
 #ifndef __ASSEMBLY__
 

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index 541949d..b774eff 100644
@@ -50,7 +50,7 @@ void puv3_pci_adjust_zones(unsigned long *size, unsigned long *holes);
 
 /* kuser area */
 #define KUSER_VECPAGE_BASE	(KUSER_BASE + UL(0x3fff0000))
-#define KUSER_UNIGFX_BASE	(KUSER_BASE + PKUNITY_UNIGFX_MMAP_BASE)
+#define KUSER_UNIGFX_BASE	(PAGE_OFFSET + PKUNITY_UNIGFX_MMAP_BASE)
 /* kuser_vecpage (0xbfff0000) is ro, and vectors page (0xffff0000) is rw */
 #define kuser_vecpage_to_vectors(x)	((x) - (KUSER_VECPAGE_BASE)	\
 					+ (VECTORS_BASE))

index 6edf928..7d10e7b 100644
@@ -93,6 +93,19 @@ static struct resource puv3_mmc_resources[] = {
 	},
 };
 
+static struct resource puv3_unigfx_resources[] = {
+	[0] = {
+		.start	= PKUNITY_UNIGFX_BASE,
+		.end	= PKUNITY_UNIGFX_BASE + 0xfff,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= PKUNITY_UNIGFX_MMAP_BASE,
+		.end	= PKUNITY_UNIGFX_MMAP_BASE + PKUNITY_UNIGFX_MMAP_SIZE,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
 static struct resource puv3_rtc_resources[] = {
 	[0] = {
 		.start = PKUNITY_RTC_BASE,

@@ -256,6 +269,8 @@ void __init puv3_core_init(void)
 			puv3_umal_resources, ARRAY_SIZE(puv3_umal_resources));
 	platform_device_register_simple("PKUnity-v3-MMC", -1,
 			puv3_mmc_resources, ARRAY_SIZE(puv3_mmc_resources));
+	platform_device_register_simple("PKUnity-v3-UNIGFX", -1,
+			puv3_unigfx_resources, ARRAY_SIZE(puv3_unigfx_resources));
 	platform_device_register_simple("PKUnity-v3-PWM", -1,
 			puv3_pwm_resources, ARRAY_SIZE(puv3_pwm_resources));
 	platform_device_register_simple("PKUnity-v3-UART", 0,

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index 68ba85a..b2a3639 100644
@@ -152,6 +152,8 @@
 #define FB_ACCEL_PROSAVAGE_DDR  0x8d	/* S3 ProSavage DDR             */
 #define FB_ACCEL_PROSAVAGE_DDRK 0x8e	/* S3 ProSavage DDR-K           */
 
+#define FB_ACCEL_PUV3_UNIGFX	0xa0	/* PKUnity-v3 Unigfx		*/
+
 struct fb_fix_screeninfo {
 	char id[16];			/* identification string eg "TT Builtin" */
 	unsigned long smem_start;	/* Start of frame buffer mem */

index b71405a..b197b0b 100644
@@ -17,13 +17,10 @@
 
 #include "PKUnity.h"
 
-#define io_p2v(x)	((x) - PKUNITY_MMIO_BASE)
-#define io_v2p(x)	((x) + PKUNITY_MMIO_BASE)
-
 #ifndef __ASSEMBLY__
-
-# define __REG(x)	(void __iomem *)io_p2v(x)
-
+#define io_p2v(x)	(void __iomem *)((x) - PKUNITY_MMIO_BASE)
+#else
+#define io_p2v(x)	((x) - PKUNITY_MMIO_BASE)
 #endif
 
 #define PCIBIOS_MIN_IO			0x4000 /* should lower than 64KB */

index ce299bf..2d76cc3 100644
@@ -2,16 +2,16 @@
  * PKUnity AC97 Registers
  */
 
-#define PKUNITY_AC97_CONR		__REG(PKUNITY_AC97_BASE + 0x0000)
-#define PKUNITY_AC97_OCR		__REG(PKUNITY_AC97_BASE + 0x0004)
-#define PKUNITY_AC97_ICR		__REG(PKUNITY_AC97_BASE + 0x0008)
-#define PKUNITY_AC97_CRAC		__REG(PKUNITY_AC97_BASE + 0x000C)
-#define PKUNITY_AC97_INTR		__REG(PKUNITY_AC97_BASE + 0x0010)
-#define PKUNITY_AC97_INTRSTAT		__REG(PKUNITY_AC97_BASE + 0x0014)
-#define PKUNITY_AC97_INTRCLEAR		__REG(PKUNITY_AC97_BASE + 0x0018)
-#define PKUNITY_AC97_ENABLE		__REG(PKUNITY_AC97_BASE + 0x001C)
-#define PKUNITY_AC97_OUT_FIFO		__REG(PKUNITY_AC97_BASE + 0x0020)
-#define PKUNITY_AC97_IN_FIFO		__REG(PKUNITY_AC97_BASE + 0x0030)
+#define PKUNITY_AC97_CONR		io_p2v(PKUNITY_AC97_BASE + 0x0000)
+#define PKUNITY_AC97_OCR		io_p2v(PKUNITY_AC97_BASE + 0x0004)
+#define PKUNITY_AC97_ICR		io_p2v(PKUNITY_AC97_BASE + 0x0008)
+#define PKUNITY_AC97_CRAC		io_p2v(PKUNITY_AC97_BASE + 0x000C)
+#define PKUNITY_AC97_INTR		io_p2v(PKUNITY_AC97_BASE + 0x0010)
+#define PKUNITY_AC97_INTRSTAT		io_p2v(PKUNITY_AC97_BASE + 0x0014)
+#define PKUNITY_AC97_INTRCLEAR		io_p2v(PKUNITY_AC97_BASE + 0x0018)
+#define PKUNITY_AC97_ENABLE		io_p2v(PKUNITY_AC97_BASE + 0x001C)
+#define PKUNITY_AC97_OUT_FIFO		io_p2v(PKUNITY_AC97_BASE + 0x0020)
+#define PKUNITY_AC97_IN_FIFO		io_p2v(PKUNITY_AC97_BASE + 0x0030)
 
 #define AC97_CODEC_REG(v)               FIELD((v), 7, 16)
 #define AC97_CODEC_VAL(v)               FIELD((v), 16, 0)

index 09fce9d..3553243 100644
@@ -5,27 +5,27 @@
 /*
  * Interrupt Status Reg DMAC_ISR.
  */
-#define DMAC_ISR		__REG(PKUNITY_DMAC_BASE + 0x0020)
+#define DMAC_ISR		io_p2v(PKUNITY_DMAC_BASE + 0x0020)
 /*
  * Interrupt Transfer Complete Status Reg DMAC_ITCSR.
  */
-#define DMAC_ITCSR		__REG(PKUNITY_DMAC_BASE + 0x0050)
+#define DMAC_ITCSR		io_p2v(PKUNITY_DMAC_BASE + 0x0050)
 /*
  * Interrupt Transfer Complete Clear Reg DMAC_ITCCR.
  */
-#define DMAC_ITCCR		__REG(PKUNITY_DMAC_BASE + 0x0060)
+#define DMAC_ITCCR		io_p2v(PKUNITY_DMAC_BASE + 0x0060)
 /*
  * Interrupt Error Status Reg DMAC_IESR.
  */
-#define DMAC_IESR		__REG(PKUNITY_DMAC_BASE + 0x0080)
+#define DMAC_IESR		io_p2v(PKUNITY_DMAC_BASE + 0x0080)
 /*
  * Interrupt Error Clear Reg DMAC_IECR.
  */
-#define DMAC_IECR		__REG(PKUNITY_DMAC_BASE + 0x0090)
+#define DMAC_IECR		io_p2v(PKUNITY_DMAC_BASE + 0x0090)
 /*
  * Enable Channels Reg DMAC_ENCH.
  */
-#define DMAC_ENCH		__REG(PKUNITY_DMAC_BASE + 0x00B0)
+#define DMAC_ENCH		io_p2v(PKUNITY_DMAC_BASE + 0x00B0)
 
 /*
  * DMA control reg. Space [byte]

@@ -35,19 +35,19 @@
 /*
  * Source Addr DMAC_SRCADDR(ch).
  */
-#define DMAC_SRCADDR(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
+#define DMAC_SRCADDR(ch)	io_p2v(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
 /*
  * Destination Addr DMAC_DESTADDR(ch).
  */
-#define DMAC_DESTADDR(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
+#define DMAC_DESTADDR(ch)	io_p2v(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
 /*
  * Control Reg DMAC_CONTROL(ch).
  */
-#define DMAC_CONTROL(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
+#define DMAC_CONTROL(ch)	io_p2v(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
 /*
  * Configuration Reg DMAC_CONFIG(ch).
  */
-#define DMAC_CONFIG(ch)		__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
+#define DMAC_CONFIG(ch)		io_p2v(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
 
 #define DMAC_IR_MASK            FMASK(6, 0)
 /*

index 5dd99d4..241a473 100644
@@ -5,35 +5,35 @@
 /*
  * Voltage Status Reg GPIO_GPLR.
  */
-#define GPIO_GPLR	__REG(PKUNITY_GPIO_BASE + 0x0000)
+#define GPIO_GPLR	io_p2v(PKUNITY_GPIO_BASE + 0x0000)
 /*
  * Pin Direction Reg GPIO_GPDR.
  */
-#define GPIO_GPDR	__REG(PKUNITY_GPIO_BASE + 0x0004)
+#define GPIO_GPDR	io_p2v(PKUNITY_GPIO_BASE + 0x0004)
 /*
  * Output Pin Set Reg GPIO_GPSR.
  */
-#define GPIO_GPSR	__REG(PKUNITY_GPIO_BASE + 0x0008)
+#define GPIO_GPSR	io_p2v(PKUNITY_GPIO_BASE + 0x0008)
 /*
  * Output Pin Clear Reg GPIO_GPCR.
  */
-#define GPIO_GPCR	__REG(PKUNITY_GPIO_BASE + 0x000C)
+#define GPIO_GPCR	io_p2v(PKUNITY_GPIO_BASE + 0x000C)
 /*
  * Raise Edge Detect Reg GPIO_GRER.
  */
-#define GPIO_GRER	__REG(PKUNITY_GPIO_BASE + 0x0010)
+#define GPIO_GRER	io_p2v(PKUNITY_GPIO_BASE + 0x0010)
 /*
  * Fall Edge Detect Reg GPIO_GFER.
  */
-#define GPIO_GFER	__REG(PKUNITY_GPIO_BASE + 0x0014)
+#define GPIO_GFER	io_p2v(PKUNITY_GPIO_BASE + 0x0014)
 /*
  * Edge Status Reg GPIO_GEDR.
  */
-#define GPIO_GEDR	__REG(PKUNITY_GPIO_BASE + 0x0018)
+#define GPIO_GEDR	io_p2v(PKUNITY_GPIO_BASE + 0x0018)
 /*
  * Sepcial Voltage Detect Reg GPIO_GPIR.
  */
-#define GPIO_GPIR	__REG(PKUNITY_GPIO_BASE + 0x0020)
+#define GPIO_GPIR	io_p2v(PKUNITY_GPIO_BASE + 0x0020)
 
 #define GPIO_MIN	(0)
 #define GPIO_MAX	(27)

index 70b704f..a1fe882 100644
@@ -5,35 +5,35 @@
 /*
  * Control Reg I2C_CON.
  */
-#define I2C_CON		__REG(PKUNITY_I2C_BASE + 0x0000)
+#define I2C_CON		io_p2v(PKUNITY_I2C_BASE + 0x0000)
 /*
  * Target Address Reg I2C_TAR.
  */
-#define I2C_TAR		__REG(PKUNITY_I2C_BASE + 0x0004)
+#define I2C_TAR		io_p2v(PKUNITY_I2C_BASE + 0x0004)
 /*
  * Data buffer and command Reg I2C_DATACMD.
  */
-#define I2C_DATACMD	__REG(PKUNITY_I2C_BASE + 0x0010)
+#define I2C_DATACMD	io_p2v(PKUNITY_I2C_BASE + 0x0010)
 /*
  * Enable Reg I2C_ENABLE.
  */
-#define I2C_ENABLE	__REG(PKUNITY_I2C_BASE + 0x006C)
+#define I2C_ENABLE	io_p2v(PKUNITY_I2C_BASE + 0x006C)
 /*
  * Status Reg I2C_STATUS.
  */
-#define I2C_STATUS	__REG(PKUNITY_I2C_BASE + 0x0070)
+#define I2C_STATUS	io_p2v(PKUNITY_I2C_BASE + 0x0070)
 /*
  * Tx FIFO Length Reg I2C_TXFLR.
  */
-#define I2C_TXFLR	__REG(PKUNITY_I2C_BASE + 0x0074)
+#define I2C_TXFLR	io_p2v(PKUNITY_I2C_BASE + 0x0074)
 /*
  * Rx FIFO Length Reg I2C_RXFLR.
  */
-#define I2C_RXFLR	__REG(PKUNITY_I2C_BASE + 0x0078)
+#define I2C_RXFLR	io_p2v(PKUNITY_I2C_BASE + 0x0078)
 /*
  * Enable Status Reg I2C_ENSTATUS.
  */
-#define I2C_ENSTATUS	__REG(PKUNITY_I2C_BASE + 0x009C)
+#define I2C_ENSTATUS	io_p2v(PKUNITY_I2C_BASE + 0x009C)
 
 #define I2C_CON_MASTER          FIELD(1, 1, 0)
 #define I2C_CON_SPEED_STD       FIELD(1, 2, 1)

index 409ae47..de828d0 100644
@@ -4,25 +4,25 @@
 /*
  * INTC Level Reg INTC_ICLR.
  */
-#define INTC_ICLR	__REG(PKUNITY_INTC_BASE + 0x0000)
+#define INTC_ICLR	io_p2v(PKUNITY_INTC_BASE + 0x0000)
 /*
  * INTC Mask Reg INTC_ICMR.
  */
-#define INTC_ICMR	__REG(PKUNITY_INTC_BASE + 0x0004)
+#define INTC_ICMR	io_p2v(PKUNITY_INTC_BASE + 0x0004)
 /*
  * INTC Pending Reg INTC_ICPR.
  */
-#define INTC_ICPR	__REG(PKUNITY_INTC_BASE + 0x0008)
+#define INTC_ICPR	io_p2v(PKUNITY_INTC_BASE + 0x0008)
 /*
  * INTC IRQ Pending Reg INTC_ICIP.
  */
-#define INTC_ICIP	__REG(PKUNITY_INTC_BASE + 0x000C)
+#define INTC_ICIP	io_p2v(PKUNITY_INTC_BASE + 0x000C)
 /*
  * INTC REAL Pending Reg INTC_ICFP.
  */
-#define INTC_ICFP	__REG(PKUNITY_INTC_BASE + 0x0010)
+#define INTC_ICFP	io_p2v(PKUNITY_INTC_BASE + 0x0010)
 /*
  * INTC Control Reg INTC_ICCR.
  */
-#define INTC_ICCR	__REG(PKUNITY_INTC_BASE + 0x0014)
+#define INTC_ICCR	io_p2v(PKUNITY_INTC_BASE + 0x0014)
 

index 0c33fe8..92578df 100644
@@ -4,67 +4,67 @@
 /*
  * ID Reg. 0 NAND_IDR0
  */
-#define NAND_IDR0	__REG(PKUNITY_NAND_BASE + 0x0000)
+#define NAND_IDR0	io_p2v(PKUNITY_NAND_BASE + 0x0000)
 /*
  * ID Reg. 1 NAND_IDR1
  */
-#define NAND_IDR1	__REG(PKUNITY_NAND_BASE + 0x0004)
+#define NAND_IDR1	io_p2v(PKUNITY_NAND_BASE + 0x0004)
 /*
  * ID Reg. 2 NAND_IDR2
  */
-#define NAND_IDR2	__REG(PKUNITY_NAND_BASE + 0x0008)
+#define NAND_IDR2	io_p2v(PKUNITY_NAND_BASE + 0x0008)
 /*
  * ID Reg. 3 NAND_IDR3
  */
-#define NAND_IDR3	__REG(PKUNITY_NAND_BASE + 0x000C)
+#define NAND_IDR3	io_p2v(PKUNITY_NAND_BASE + 0x000C)
 /*
  * Page Address Reg 0 NAND_PAR0
  */
-#define NAND_PAR0	__REG(PKUNITY_NAND_BASE + 0x0010)
+#define NAND_PAR0	io_p2v(PKUNITY_NAND_BASE + 0x0010)
 /*
  * Page Address Reg 1 NAND_PAR1
  */
-#define NAND_PAR1	__REG(PKUNITY_NAND_BASE + 0x0014)
+#define NAND_PAR1	io_p2v(PKUNITY_NAND_BASE + 0x0014)
 /*
  * Page Address Reg 2 NAND_PAR2
  */
-#define NAND_PAR2	__REG(PKUNITY_NAND_BASE + 0x0018)
+#define NAND_PAR2	io_p2v(PKUNITY_NAND_BASE + 0x0018)
 /*
  * ECC Enable Reg NAND_ECCEN
  */
-#define NAND_ECCEN	__REG(PKUNITY_NAND_BASE + 0x001C)
+#define NAND_ECCEN	io_p2v(PKUNITY_NAND_BASE + 0x001C)
 /*
  * Buffer Reg NAND_BUF
  */
-#define NAND_BUF	__REG(PKUNITY_NAND_BASE + 0x0020)
+#define NAND_BUF	io_p2v(PKUNITY_NAND_BASE + 0x0020)
 /*
  * ECC Status Reg NAND_ECCSR
  */
-#define NAND_ECCSR	__REG(PKUNITY_NAND_BASE + 0x0024)
+#define NAND_ECCSR	io_p2v(PKUNITY_NAND_BASE + 0x0024)
 /*
  * Command Reg NAND_CMD
  */
-#define NAND_CMD	__REG(PKUNITY_NAND_BASE + 0x0028)
+#define NAND_CMD	io_p2v(PKUNITY_NAND_BASE + 0x0028)
 /*
  * DMA Configure Reg NAND_DMACR
  */
-#define NAND_DMACR	__REG(PKUNITY_NAND_BASE + 0x002C)
+#define NAND_DMACR	io_p2v(PKUNITY_NAND_BASE + 0x002C)
 /*
  * Interrupt Reg NAND_IR
  */
-#define NAND_IR		__REG(PKUNITY_NAND_BASE + 0x0030)
+#define NAND_IR		io_p2v(PKUNITY_NAND_BASE + 0x0030)
 /*
  * Interrupt Mask Reg NAND_IMR
  */
-#define NAND_IMR	__REG(PKUNITY_NAND_BASE + 0x0034)
+#define NAND_IMR	io_p2v(PKUNITY_NAND_BASE + 0x0034)
 /*
  * Chip Enable Reg NAND_CHIPEN
  */
-#define NAND_CHIPEN	__REG(PKUNITY_NAND_BASE + 0x0038)
+#define NAND_CHIPEN	io_p2v(PKUNITY_NAND_BASE + 0x0038)
 /*
  * Address Reg NAND_ADDR
  */
-#define NAND_ADDR	__REG(PKUNITY_NAND_BASE + 0x003C)
+#define NAND_ADDR	io_p2v(PKUNITY_NAND_BASE + 0x003C)
 
 /*
  * Command bits NAND_CMD_CMD_MASK

index 33049a8..72b586a 100644
@@ -4,47 +4,47 @@
 /*
  * Match Reg 0 OST_OSMR0
  */
-#define OST_OSMR0	__REG(PKUNITY_OST_BASE + 0x0000)
+#define OST_OSMR0	io_p2v(PKUNITY_OST_BASE + 0x0000)
 /*
  * Match Reg 1 OST_OSMR1
  */
-#define OST_OSMR1	__REG(PKUNITY_OST_BASE + 0x0004)
+#define OST_OSMR1	io_p2v(PKUNITY_OST_BASE + 0x0004)
 /*
  * Match Reg 2 OST_OSMR2
  */
-#define OST_OSMR2	__REG(PKUNITY_OST_BASE + 0x0008)
+#define OST_OSMR2	io_p2v(PKUNITY_OST_BASE + 0x0008)
 /*
  * Match Reg 3 OST_OSMR3
  */
-#define OST_OSMR3	__REG(PKUNITY_OST_BASE + 0x000C)
+#define OST_OSMR3	io_p2v(PKUNITY_OST_BASE + 0x000C)
 /*
  * Counter Reg OST_OSCR
  */
-#define OST_OSCR	__REG(PKUNITY_OST_BASE + 0x0010)
+#define OST_OSCR	io_p2v(PKUNITY_OST_BASE + 0x0010)
 /*
  * Status Reg OST_OSSR
  */
-#define OST_OSSR	__REG(PKUNITY_OST_BASE + 0x0014)
+#define OST_OSSR	io_p2v(PKUNITY_OST_BASE + 0x0014)
 /*
  * Watchdog Enable Reg OST_OWER
  */
-#define OST_OWER	__REG(PKUNITY_OST_BASE + 0x0018)
+#define OST_OWER	io_p2v(PKUNITY_OST_BASE + 0x0018)
 /*
  * Interrupt Enable Reg OST_OIER
  */
-#define OST_OIER	__REG(PKUNITY_OST_BASE + 0x001C)
+#define OST_OIER	io_p2v(PKUNITY_OST_BASE + 0x001C)
 /*
  * PWM Pulse Width Control Reg OST_PWMPWCR
  */
-#define OST_PWMPWCR	__REG(PKUNITY_OST_BASE + 0x0080)
+#define OST_PWMPWCR	io_p2v(PKUNITY_OST_BASE + 0x0080)
 /*
  * PWM Duty Cycle Control Reg OST_PWMDCCR
  */
-#define OST_PWMDCCR	__REG(PKUNITY_OST_BASE + 0x0084)
+#define OST_PWMDCCR	io_p2v(PKUNITY_OST_BASE + 0x0084)
 /*
  * PWM Period Control Reg OST_PWMPCR
  */
-#define OST_PWMPCR	__REG(PKUNITY_OST_BASE + 0x0088)
+#define OST_PWMPCR	io_p2v(PKUNITY_OST_BASE + 0x0088)
 
 /*
  * Match detected 0 OST_OSSR_M0

140 lines not on this page · raw message

index ed2d2fc..8274b87 100644
@@ -4,75 +4,75 @@
 /*
  * PM Control Reg PM_PMCR
  */
-#define PM_PMCR                 __REG(PKUNITY_PM_BASE + 0x0000)
+#define PM_PMCR                 io_p2v(PKUNITY_PM_BASE + 0x0000)
 /*
  * PM General Conf. Reg PM_PGCR
  */
-#define PM_PGCR                 __REG(PKUNITY_PM_BASE + 0x0004)
+#define PM_PGCR                 io_p2v(PKUNITY_PM_BASE + 0x0004)
 /*
  * PM PLL Conf. Reg PM_PPCR
  */
-#define PM_PPCR                 __REG(PKUNITY_PM_BASE + 0x0008)
+#define PM_PPCR                 io_p2v(PKUNITY_PM_BASE + 0x0008)
 /*
  * PM Wakeup Enable Reg PM_PWER
  */
-#define PM_PWER                 __REG(PKUNITY_PM_BASE + 0x000C)
+#define PM_PWER                 io_p2v(PKUNITY_PM_BASE + 0x000C)
 /*
  * PM GPIO Sleep Status Reg PM_PGSR
  */
-#define PM_PGSR                 __REG(PKUNITY_PM_BASE + 0x0010)
+#define PM_PGSR                 io_p2v(PKUNITY_PM_BASE + 0x0010)
 /*
  * PM Clock Gate Reg PM_PCGR
  */
-#define PM_PCGR                 __REG(PKUNITY_PM_BASE + 0x0014)
+#define PM_PCGR                 io_p2v(PKUNITY_PM_BASE + 0x0014)
 /*
  * PM SYS PLL Conf. Reg PM_PLLSYSCFG
  */
-#define PM_PLLSYSCFG            __REG(PKUNITY_PM_BASE + 0x0018)
+#define PM_PLLSYSCFG            io_p2v(PKUNITY_PM_BASE + 0x0018)
 /*
  * PM DDR PLL Conf. Reg PM_PLLDDRCFG
  */
-#define PM_PLLDDRCFG            __REG(PKUNITY_PM_BASE + 0x001C)
+#define PM_PLLDDRCFG            io_p2v(PKUNITY_PM_BASE + 0x001C)
 /*
  * PM VGA PLL Conf. Reg PM_PLLVGACFG
  */
-#define PM_PLLVGACFG            __REG(PKUNITY_PM_BASE + 0x0020)
+#define PM_PLLVGACFG            io_p2v(PKUNITY_PM_BASE + 0x0020)
 /*
  * PM Div Conf. Reg PM_DIVCFG
  */
-#define PM_DIVCFG               __REG(PKUNITY_PM_BASE + 0x0024)
+#define PM_DIVCFG               io_p2v(PKUNITY_PM_BASE + 0x0024)
 /*
  * PM SYS PLL Status Reg PM_PLLSYSSTATUS
  */
-#define PM_PLLSYSSTATUS         __REG(PKUNITY_PM_BASE + 0x0028)
+#define PM_PLLSYSSTATUS         io_p2v(PKUNITY_PM_BASE + 0x0028)
 /*
  * PM DDR PLL Status Reg PM_PLLDDRSTATUS
  */
-#define PM_PLLDDRSTATUS         __REG(PKUNITY_PM_BASE + 0x002C)
+#define PM_PLLDDRSTATUS         io_p2v(PKUNITY_PM_BASE + 0x002C)
 /*
  * PM VGA PLL Status Reg PM_PLLVGASTATUS
  */
-#define PM_PLLVGASTATUS         __REG(PKUNITY_PM_BASE + 0x0030)
+#define PM_PLLVGASTATUS         io_p2v(PKUNITY_PM_BASE + 0x0030)
 /*
  * PM Div Status Reg PM_DIVSTATUS
  */
-#define PM_DIVSTATUS            __REG(PKUNITY_PM_BASE + 0x0034)
+#define PM_DIVSTATUS            io_p2v(PKUNITY_PM_BASE + 0x0034)
 /*
  * PM Software Reset Reg PM_SWRESET
  */
-#define PM_SWRESET              __REG(PKUNITY_PM_BASE + 0x0038)
+#define PM_SWRESET              io_p2v(PKUNITY_PM_BASE + 0x0038)
 /*
  * PM DDR2 PAD Start Reg PM_DDR2START
  */
-#define PM_DDR2START            __REG(PKUNITY_PM_BASE + 0x003C)
+#define PM_DDR2START            io_p2v(PKUNITY_PM_BASE + 0x003C)
 /*
  * PM DDR2 PAD Status Reg PM_DDR2CAL0
  */
-#define PM_DDR2CAL0             __REG(PKUNITY_PM_BASE + 0x0040)
+#define PM_DDR2CAL0             io_p2v(PKUNITY_PM_BASE + 0x0040)
 /*
  * PM PLL DFC Done Reg PM_PLLDFCDONE
  */
-#define PM_PLLDFCDONE           __REG(PKUNITY_PM_BASE + 0x0044)
+#define PM_PLLDFCDONE           io_p2v(PKUNITY_PM_BASE + 0x0044)
 
 #define PM_PMCR_SFB             FIELD(1, 1, 0)
 #define PM_PMCR_IFB             FIELD(1, 1, 1)

index 7da2071..725841e 100644
@@ -4,17 +4,17 @@
 /*
  * the same as I8042_DATA_REG PS2_DATA
  */
-#define PS2_DATA	__REG(PKUNITY_PS2_BASE + 0x0060)
+#define PS2_DATA	io_p2v(PKUNITY_PS2_BASE + 0x0060)
 /*
  * the same as I8042_COMMAND_REG PS2_COMMAND
  */
-#define PS2_COMMAND	__REG(PKUNITY_PS2_BASE + 0x0064)
+#define PS2_COMMAND	io_p2v(PKUNITY_PS2_BASE + 0x0064)
 /*
  * the same as I8042_STATUS_REG PS2_STATUS
  */
-#define PS2_STATUS	__REG(PKUNITY_PS2_BASE + 0x0064)
+#define PS2_STATUS	io_p2v(PKUNITY_PS2_BASE + 0x0064)
 /*
  * counter reg PS2_CNT
  */
-#define PS2_CNT		__REG(PKUNITY_PS2_BASE + 0x0068)
+#define PS2_CNT		io_p2v(PKUNITY_PS2_BASE + 0x0068)
 

index 1763989..8b0629c 100644
@@ -4,11 +4,11 @@
 /*
  * Software Reset Register
  */
-#define RESETC_SWRR	__REG(PKUNITY_RESETC_BASE + 0x0000)
+#define RESETC_SWRR	io_p2v(PKUNITY_RESETC_BASE + 0x0000)
 /*
  * Reset Status Register
  */
-#define RESETC_RSSR	__REG(PKUNITY_RESETC_BASE + 0x0004)
+#define RESETC_RSSR	io_p2v(PKUNITY_RESETC_BASE + 0x0004)
 
 /*
  * Software Reset Bit

index 155e3875..b70bc16 100644
@@ -4,19 +4,19 @@
 /*
  * RTC Alarm Reg RTC_RTAR
  */
-#define RTC_RTAR	__REG(PKUNITY_RTC_BASE + 0x0000)
+#define RTC_RTAR	io_p2v(PKUNITY_RTC_BASE + 0x0000)
 /*
  * RTC Count Reg RTC_RCNR
  */
-#define RTC_RCNR	__REG(PKUNITY_RTC_BASE + 0x0004)
+#define RTC_RCNR	io_p2v(PKUNITY_RTC_BASE + 0x0004)
 /*
  * RTC Trim Reg RTC_RTTR
  */
-#define RTC_RTTR	__REG(PKUNITY_RTC_BASE + 0x0008)
+#define RTC_RTTR	io_p2v(PKUNITY_RTC_BASE + 0x0008)
 /*
  * RTC Status Reg RTC_RTSR
  */
-#define RTC_RTSR	__REG(PKUNITY_RTC_BASE + 0x0010)
+#define RTC_RTSR	io_p2v(PKUNITY_RTC_BASE + 0x0010)
 
 /*
  * ALarm detected RTC_RTSR_AL

index 3457b88..47f56e5 100644
@@ -4,67 +4,67 @@
 /*
  * Clock Control Reg SDC_CCR
  */
-#define SDC_CCR		__REG(PKUNITY_SDC_BASE + 0x0000)
+#define SDC_CCR		io_p2v(PKUNITY_SDC_BASE + 0x0000)
 /*
  * Software Reset Reg SDC_SRR
  */
-#define SDC_SRR		__REG(PKUNITY_SDC_BASE + 0x0004)
+#define SDC_SRR		io_p2v(PKUNITY_SDC_BASE + 0x0004)
 /*
  * Argument Reg SDC_ARGUMENT
  */
-#define SDC_ARGUMENT	__REG(PKUNITY_SDC_BASE + 0x0008)
+#define SDC_ARGUMENT	io_p2v(PKUNITY_SDC_BASE + 0x0008)
 /*
  * Command Reg SDC_COMMAND
  */
-#define SDC_COMMAND	__REG(PKUNITY_SDC_BASE + 0x000C)
+#define SDC_COMMAND	io_p2v(PKUNITY_SDC_BASE + 0x000C)
 /*
  * Block Size Reg SDC_BLOCKSIZE
  */
-#define SDC_BLOCKSIZE	__REG(PKUNITY_SDC_BASE + 0x0010)
+#define SDC_BLOCKSIZE	io_p2v(PKUNITY_SDC_BASE + 0x0010)
 /*
  * Block Cound Reg SDC_BLOCKCOUNT
  */
-#define SDC_BLOCKCOUNT	__REG(PKUNITY_SDC_BASE + 0x0014)
+#define SDC_BLOCKCOUNT	io_p2v(PKUNITY_SDC_BASE + 0x0014)
 /*
  * Transfer Mode Reg SDC_TMR
  */
-#define SDC_TMR		__REG(PKUNITY_SDC_BASE + 0x0018)
+#define SDC_TMR		io_p2v(PKUNITY_SDC_BASE + 0x0018)
 /*
  * Response Reg. 0 SDC_RES0
  */
-#define SDC_RES0	__REG(PKUNITY_SDC_BASE + 0x001C)
+#define SDC_RES0	io_p2v(PKUNITY_SDC_BASE + 0x001C)
 /*
  * Response Reg. 1 SDC_RES1
  */
-#define SDC_RES1	__REG(PKUNITY_SDC_BASE + 0x0020)
+#define SDC_RES1	io_p2v(PKUNITY_SDC_BASE + 0x0020)
 /*
  * Response Reg. 2 SDC_RES2
  */
-#define SDC_RES2	__REG(PKUNITY_SDC_BASE + 0x0024)
+#define SDC_RES2	io_p2v(PKUNITY_SDC_BASE + 0x0024)
 /*
  * Response Reg. 3 SDC_RES3
  */
-#define SDC_RES3	__REG(PKUNITY_SDC_BASE + 0x0028)
+#define SDC_RES3	io_p2v(PKUNITY_SDC_BASE + 0x0028)
 /*
  * Read Timeout Control Reg SDC_RTCR
  */
-#define SDC_RTCR	__REG(PKUNITY_SDC_BASE + 0x002C)
+#define SDC_RTCR	io_p2v(PKUNITY_SDC_BASE + 0x002C)
 /*
  * Interrupt Status Reg SDC_ISR
  */
-#define SDC_ISR		__REG(PKUNITY_SDC_BASE + 0x0030)
+#define SDC_ISR		io_p2v(PKUNITY_SDC_BASE + 0x0030)
 /*
  * Interrupt Status Mask Reg SDC_ISMR
  */
-#define SDC_ISMR	__REG(PKUNITY_SDC_BASE + 0x0034)
+#define SDC_ISMR	io_p2v(PKUNITY_SDC_BASE + 0x0034)
 /*
  * RX FIFO SDC_RXFIFO
  */
-#define SDC_RXFIFO	__REG(PKUNITY_SDC_BASE + 0x0038)
+#define SDC_RXFIFO	io_p2v(PKUNITY_SDC_BASE + 0x0038)
 /*
  * TX FIFO SDC_TXFIFO
  */
-#define SDC_TXFIFO	__REG(PKUNITY_SDC_BASE + 0x003C)
+#define SDC_TXFIFO	io_p2v(PKUNITY_SDC_BASE + 0x003C)
 
 /*
  * SD Clock Enable SDC_CCR_CLKEN

index cadc713..6afe263 100644
@@ -4,27 +4,27 @@
 /*
  * Control reg. 0 SPI_CR0
  */
-#define SPI_CR0		__REG(PKUNITY_SPI_BASE + 0x0000)
+#define SPI_CR0		io_p2v(PKUNITY_SPI_BASE + 0x0000)
 /*
  * Control reg. 1 SPI_CR1
  */
-#define SPI_CR1		__REG(PKUNITY_SPI_BASE + 0x0004)
+#define SPI_CR1		io_p2v(PKUNITY_SPI_BASE + 0x0004)
 /*
  * Enable reg SPI_SSIENR
  */
-#define SPI_SSIENR	__REG(PKUNITY_SPI_BASE + 0x0008)
+#define SPI_SSIENR	io_p2v(PKUNITY_SPI_BASE + 0x0008)
 /*
  * Status reg SPI_SR
  */
-#define SPI_SR		__REG(PKUNITY_SPI_BASE + 0x0028)
+#define SPI_SR		io_p2v(PKUNITY_SPI_BASE + 0x0028)
 /*
  * Interrupt Mask reg SPI_IMR
  */
-#define SPI_IMR		__REG(PKUNITY_SPI_BASE + 0x002C)
+#define SPI_IMR		io_p2v(PKUNITY_SPI_BASE + 0x002C)
 /*
  * Interrupt Status reg SPI_ISR
  */
-#define SPI_ISR		__REG(PKUNITY_SPI_BASE + 0x0030)
+#define SPI_ISR		io_p2v(PKUNITY_SPI_BASE + 0x0030)
 
 /*
  * Enable SPI Controller SPI_SSIENR_EN

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233 lines not on this page · raw message

index d73457c..2483fcb 100644
@@ -18,6 +18,7 @@
 #include <asm/memory.h>
 #include <asm/system.h>
 
+#define PCI_IOBASE	io_p2v(PKUNITY_PCILIO_BASE)
 #include <asm-generic/io.h>
 
 /*

@@ -38,9 +39,6 @@ extern void __uc32_iounmap(volatile void __iomem *addr);
 #define ioremap_cached(cookie, size)	__uc32_ioremap_cached(cookie, size)
 #define iounmap(cookie)			__uc32_iounmap(cookie)
 
-extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
-extern void ioport_unmap(void __iomem *addr);
-
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  * access

@@ -48,5 +46,10 @@ extern void ioport_unmap(void __iomem *addr);
 #undef xlate_dev_mem_ptr
 #define xlate_dev_mem_ptr(p)	__va(p)
 
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET		(unsigned int)(PCI_IOBASE)
+#define PIO_MASK		(unsigned int)(IO_SPACE_LIMIT)
+#define PIO_RESERVED		(PIO_OFFSET + PIO_MASK + 1)
+
 #endif	/* __KERNEL__ */
 #endif	/* __UNICORE_IO_H__ */

56 lines not on this page · raw message

index 2483fcb..4bd87f3 100644
@@ -18,7 +18,7 @@
 #include <asm/memory.h>
 #include <asm/system.h>
 
-#define PCI_IOBASE	io_p2v(PKUNITY_PCILIO_BASE)
+#define PCI_IOBASE	PKUNITY_PCILIO_BASE
 #include <asm-generic/io.h>
 
 /*

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index b71405a..930bea6 100644
@@ -17,17 +17,16 @@
 
 #include "PKUnity.h"
 
+#ifndef __ASSEMBLY__
+#define io_p2v(x)	(void __iomem *)((x) - PKUNITY_MMIO_BASE)
+#define io_v2p(x)	(phys_addr_t)((x) + PKUNITY_MMIO_BASE)
+#else
 #define io_p2v(x)	((x) - PKUNITY_MMIO_BASE)
 #define io_v2p(x)	((x) + PKUNITY_MMIO_BASE)
-
-#ifndef __ASSEMBLY__
-
-# define __REG(x)	(void __iomem *)io_p2v(x)
-
 #endif
 
 #define PCIBIOS_MIN_IO			0x4000 /* should lower than 64KB */
-#define PCIBIOS_MIN_MEM			PKUNITY_PCIMEM_BASE
+#define PCIBIOS_MIN_MEM			io_v2p(PKUNITY_PCIMEM_BASE)
 
 /*
  * We override the standard dma-mask routines for bouncing.

index b774eff..0bf21c9 100644
@@ -45,8 +45,8 @@ void puv3_pci_adjust_zones(unsigned long *size, unsigned long *holes);
 #define is_pcibus_device(dev)	(dev &&			\
 				(strncmp(dev->bus->name, "pci", 3) == 0))
 
-#define __virt_to_pcibus(x)     (__virt_to_phys(x) + PKUNITY_PCIAHB_BASE)
-#define __pcibus_to_virt(x)     __phys_to_virt((x) - PKUNITY_PCIAHB_BASE)
+#define __virt_to_pcibus(x)     (__virt_to_phys((x) + PKUNITY_PCIAHB_BASE))
+#define __pcibus_to_virt(x)     (__phys_to_virt(x) - PKUNITY_PCIAHB_BASE)
 
 /* kuser area */
 #define KUSER_VECPAGE_BASE	(KUSER_BASE + UL(0x3fff0000))

index ce299bf..b7563e9 100644
@@ -2,16 +2,16 @@
  * PKUnity AC97 Registers
  */
 
-#define PKUNITY_AC97_CONR		__REG(PKUNITY_AC97_BASE + 0x0000)
-#define PKUNITY_AC97_OCR		__REG(PKUNITY_AC97_BASE + 0x0004)
-#define PKUNITY_AC97_ICR		__REG(PKUNITY_AC97_BASE + 0x0008)
-#define PKUNITY_AC97_CRAC		__REG(PKUNITY_AC97_BASE + 0x000C)
-#define PKUNITY_AC97_INTR		__REG(PKUNITY_AC97_BASE + 0x0010)
-#define PKUNITY_AC97_INTRSTAT		__REG(PKUNITY_AC97_BASE + 0x0014)
-#define PKUNITY_AC97_INTRCLEAR		__REG(PKUNITY_AC97_BASE + 0x0018)
-#define PKUNITY_AC97_ENABLE		__REG(PKUNITY_AC97_BASE + 0x001C)
-#define PKUNITY_AC97_OUT_FIFO		__REG(PKUNITY_AC97_BASE + 0x0020)
-#define PKUNITY_AC97_IN_FIFO		__REG(PKUNITY_AC97_BASE + 0x0030)
+#define PKUNITY_AC97_CONR		(PKUNITY_AC97_BASE + 0x0000)
+#define PKUNITY_AC97_OCR		(PKUNITY_AC97_BASE + 0x0004)
+#define PKUNITY_AC97_ICR		(PKUNITY_AC97_BASE + 0x0008)
+#define PKUNITY_AC97_CRAC		(PKUNITY_AC97_BASE + 0x000C)
+#define PKUNITY_AC97_INTR		(PKUNITY_AC97_BASE + 0x0010)
+#define PKUNITY_AC97_INTRSTAT		(PKUNITY_AC97_BASE + 0x0014)
+#define PKUNITY_AC97_INTRCLEAR		(PKUNITY_AC97_BASE + 0x0018)
+#define PKUNITY_AC97_ENABLE		(PKUNITY_AC97_BASE + 0x001C)
+#define PKUNITY_AC97_OUT_FIFO		(PKUNITY_AC97_BASE + 0x0020)
+#define PKUNITY_AC97_IN_FIFO		(PKUNITY_AC97_BASE + 0x0030)
 
 #define AC97_CODEC_REG(v)               FIELD((v), 7, 16)
 #define AC97_CODEC_VAL(v)               FIELD((v), 16, 0)

index 09fce9d..66de9e7 100644
@@ -5,27 +5,27 @@
 /*
  * Interrupt Status Reg DMAC_ISR.
  */
-#define DMAC_ISR		__REG(PKUNITY_DMAC_BASE + 0x0020)
+#define DMAC_ISR		(PKUNITY_DMAC_BASE + 0x0020)
 /*
  * Interrupt Transfer Complete Status Reg DMAC_ITCSR.
  */
-#define DMAC_ITCSR		__REG(PKUNITY_DMAC_BASE + 0x0050)
+#define DMAC_ITCSR		(PKUNITY_DMAC_BASE + 0x0050)
 /*
  * Interrupt Transfer Complete Clear Reg DMAC_ITCCR.
  */
-#define DMAC_ITCCR		__REG(PKUNITY_DMAC_BASE + 0x0060)
+#define DMAC_ITCCR		(PKUNITY_DMAC_BASE + 0x0060)
 /*
  * Interrupt Error Status Reg DMAC_IESR.
  */
-#define DMAC_IESR		__REG(PKUNITY_DMAC_BASE + 0x0080)
+#define DMAC_IESR		(PKUNITY_DMAC_BASE + 0x0080)
 /*
  * Interrupt Error Clear Reg DMAC_IECR.
  */
-#define DMAC_IECR		__REG(PKUNITY_DMAC_BASE + 0x0090)
+#define DMAC_IECR		(PKUNITY_DMAC_BASE + 0x0090)
 /*
  * Enable Channels Reg DMAC_ENCH.
  */
-#define DMAC_ENCH		__REG(PKUNITY_DMAC_BASE + 0x00B0)
+#define DMAC_ENCH		(PKUNITY_DMAC_BASE + 0x00B0)
 
 /*
  * DMA control reg. Space [byte]

@@ -35,19 +35,19 @@
 /*
  * Source Addr DMAC_SRCADDR(ch).
  */
-#define DMAC_SRCADDR(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
+#define DMAC_SRCADDR(ch)	(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
 /*
  * Destination Addr DMAC_DESTADDR(ch).
  */
-#define DMAC_DESTADDR(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
+#define DMAC_DESTADDR(ch)	(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
 /*
  * Control Reg DMAC_CONTROL(ch).
  */
-#define DMAC_CONTROL(ch)	__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
+#define DMAC_CONTROL(ch)	(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
 /*
  * Configuration Reg DMAC_CONFIG(ch).
  */
-#define DMAC_CONFIG(ch)		__REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
+#define DMAC_CONFIG(ch)		(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
 
 #define DMAC_IR_MASK            FMASK(6, 0)
 /*

index 5dd99d4..0273b86 100644
@@ -5,35 +5,35 @@
 /*
  * Voltage Status Reg GPIO_GPLR.
  */
-#define GPIO_GPLR	__REG(PKUNITY_GPIO_BASE + 0x0000)
+#define GPIO_GPLR	(PKUNITY_GPIO_BASE + 0x0000)
 /*
  * Pin Direction Reg GPIO_GPDR.
  */
-#define GPIO_GPDR	__REG(PKUNITY_GPIO_BASE + 0x0004)
+#define GPIO_GPDR	(PKUNITY_GPIO_BASE + 0x0004)
 /*
  * Output Pin Set Reg GPIO_GPSR.
  */
-#define GPIO_GPSR	__REG(PKUNITY_GPIO_BASE + 0x0008)
+#define GPIO_GPSR	(PKUNITY_GPIO_BASE + 0x0008)
 /*
  * Output Pin Clear Reg GPIO_GPCR.
  */
-#define GPIO_GPCR	__REG(PKUNITY_GPIO_BASE + 0x000C)
+#define GPIO_GPCR	(PKUNITY_GPIO_BASE + 0x000C)
 /*
  * Raise Edge Detect Reg GPIO_GRER.
  */
-#define GPIO_GRER	__REG(PKUNITY_GPIO_BASE + 0x0010)
+#define GPIO_GRER	(PKUNITY_GPIO_BASE + 0x0010)
 /*
  * Fall Edge Detect Reg GPIO_GFER.
  */
-#define GPIO_GFER	__REG(PKUNITY_GPIO_BASE + 0x0014)
+#define GPIO_GFER	(PKUNITY_GPIO_BASE + 0x0014)
 /*
  * Edge Status Reg GPIO_GEDR.
  */
-#define GPIO_GEDR	__REG(PKUNITY_GPIO_BASE + 0x0018)
+#define GPIO_GEDR	(PKUNITY_GPIO_BASE + 0x0018)
 /*
  * Sepcial Voltage Detect Reg GPIO_GPIR.
  */
-#define GPIO_GPIR	__REG(PKUNITY_GPIO_BASE + 0x0020)
+#define GPIO_GPIR	(PKUNITY_GPIO_BASE + 0x0020)
 
 #define GPIO_MIN	(0)
 #define GPIO_MAX	(27)

index 70b704f..463d108 100644
@@ -5,35 +5,35 @@
 /*
  * Control Reg I2C_CON.
  */
-#define I2C_CON		__REG(PKUNITY_I2C_BASE + 0x0000)
+#define I2C_CON		(PKUNITY_I2C_BASE + 0x0000)
 /*
  * Target Address Reg I2C_TAR.
  */
-#define I2C_TAR		__REG(PKUNITY_I2C_BASE + 0x0004)
+#define I2C_TAR		(PKUNITY_I2C_BASE + 0x0004)
 /*
  * Data buffer and command Reg I2C_DATACMD.
  */
-#define I2C_DATACMD	__REG(PKUNITY_I2C_BASE + 0x0010)
+#define I2C_DATACMD	(PKUNITY_I2C_BASE + 0x0010)
 /*
  * Enable Reg I2C_ENABLE.
  */
-#define I2C_ENABLE	__REG(PKUNITY_I2C_BASE + 0x006C)
+#define I2C_ENABLE	(PKUNITY_I2C_BASE + 0x006C)
 /*
  * Status Reg I2C_STATUS.
  */
-#define I2C_STATUS	__REG(PKUNITY_I2C_BASE + 0x0070)
+#define I2C_STATUS	(PKUNITY_I2C_BASE + 0x0070)
 /*
  * Tx FIFO Length Reg I2C_TXFLR.
  */
-#define I2C_TXFLR	__REG(PKUNITY_I2C_BASE + 0x0074)
+#define I2C_TXFLR	(PKUNITY_I2C_BASE + 0x0074)
 /*
  * Rx FIFO Length Reg I2C_RXFLR.
  */
-#define I2C_RXFLR	__REG(PKUNITY_I2C_BASE + 0x0078)
+#define I2C_RXFLR	(PKUNITY_I2C_BASE + 0x0078)
 /*
  * Enable Status Reg I2C_ENSTATUS.
  */
-#define I2C_ENSTATUS	__REG(PKUNITY_I2C_BASE + 0x009C)
+#define I2C_ENSTATUS	(PKUNITY_I2C_BASE + 0x009C)
 
 #define I2C_CON_MASTER          FIELD(1, 1, 0)
 #define I2C_CON_SPEED_STD       FIELD(1, 2, 1)

index 409ae47..25648f8 100644
@@ -4,25 +4,25 @@
 /*
  * INTC Level Reg INTC_ICLR.
  */
-#define INTC_ICLR	__REG(PKUNITY_INTC_BASE + 0x0000)
+#define INTC_ICLR	(PKUNITY_INTC_BASE + 0x0000)
 /*
  * INTC Mask Reg INTC_ICMR.
  */
-#define INTC_ICMR	__REG(PKUNITY_INTC_BASE + 0x0004)
+#define INTC_ICMR	(PKUNITY_INTC_BASE + 0x0004)
 /*
  * INTC Pending Reg INTC_ICPR.
  */
-#define INTC_ICPR	__REG(PKUNITY_INTC_BASE + 0x0008)
+#define INTC_ICPR	(PKUNITY_INTC_BASE + 0x0008)
 /*
  * INTC IRQ Pending Reg INTC_ICIP.
  */
-#define INTC_ICIP	__REG(PKUNITY_INTC_BASE + 0x000C)
+#define INTC_ICIP	(PKUNITY_INTC_BASE + 0x000C)
 /*
  * INTC REAL Pending Reg INTC_ICFP.
  */
-#define INTC_ICFP	__REG(PKUNITY_INTC_BASE + 0x0010)
+#define INTC_ICFP	(PKUNITY_INTC_BASE + 0x0010)
 /*
  * INTC Control Reg INTC_ICCR.
  */
-#define INTC_ICCR	__REG(PKUNITY_INTC_BASE + 0x0014)
+#define INTC_ICCR	(PKUNITY_INTC_BASE + 0x0014)
 

index 0c33fe8..a7c5563 100644
@@ -4,67 +4,67 @@
 /*
  * ID Reg. 0 NAND_IDR0
  */
-#define NAND_IDR0	__REG(PKUNITY_NAND_BASE + 0x0000)
+#define NAND_IDR0	(PKUNITY_NAND_BASE + 0x0000)
 /*
  * ID Reg. 1 NAND_IDR1
  */
-#define NAND_IDR1	__REG(PKUNITY_NAND_BASE + 0x0004)
+#define NAND_IDR1	(PKUNITY_NAND_BASE + 0x0004)
 /*
  * ID Reg. 2 NAND_IDR2
  */
-#define NAND_IDR2	__REG(PKUNITY_NAND_BASE + 0x0008)
+#define NAND_IDR2	(PKUNITY_NAND_BASE + 0x0008)
 /*
  * ID Reg. 3 NAND_IDR3
  */
-#define NAND_IDR3	__REG(PKUNITY_NAND_BASE + 0x000C)
+#define NAND_IDR3	(PKUNITY_NAND_BASE + 0x000C)
 /*
  * Page Address Reg 0 NAND_PAR0
  */
-#define NAND_PAR0	__REG(PKUNITY_NAND_BASE + 0x0010)
+#define NAND_PAR0	(PKUNITY_NAND_BASE + 0x0010)
 /*
  * Page Address Reg 1 NAND_PAR1
  */
-#define NAND_PAR1	__REG(PKUNITY_NAND_BASE + 0x0014)
+#define NAND_PAR1	(PKUNITY_NAND_BASE + 0x0014)
 /*
  * Page Address Reg 2 NAND_PAR2
  */
-#define NAND_PAR2	__REG(PKUNITY_NAND_BASE + 0x0018)
+#define NAND_PAR2	(PKUNITY_NAND_BASE + 0x0018)
 /*
  * ECC Enable Reg NAND_ECCEN
  */
-#define NAND_ECCEN	__REG(PKUNITY_NAND_BASE + 0x001C)
+#define NAND_ECCEN	(PKUNITY_NAND_BASE + 0x001C)
 /*
  * Buffer Reg NAND_BUF
  */
-#define NAND_BUF	__REG(PKUNITY_NAND_BASE + 0x0020)
+#define NAND_BUF	(PKUNITY_NAND_BASE + 0x0020)
 /*
  * ECC Status Reg NAND_ECCSR
  */
-#define NAND_ECCSR	__REG(PKUNITY_NAND_BASE + 0x0024)
+#define NAND_ECCSR	(PKUNITY_NAND_BASE + 0x0024)
 /*
  * Command Reg NAND_CMD
  */
-#define NAND_CMD	__REG(PKUNITY_NAND_BASE + 0x0028)
+#define NAND_CMD	(PKUNITY_NAND_BASE + 0x0028)
 /*
  * DMA Configure Reg NAND_DMACR
  */
-#define NAND_DMACR	__REG(PKUNITY_NAND_BASE + 0x002C)
+#define NAND_DMACR	(PKUNITY_NAND_BASE + 0x002C)
 /*
  * Interrupt Reg NAND_IR
  */
-#define NAND_IR		__REG(PKUNITY_NAND_BASE + 0x0030)
+#define NAND_IR		(PKUNITY_NAND_BASE + 0x0030)
 /*
  * Interrupt Mask Reg NAND_IMR
  */
-#define NAND_IMR	__REG(PKUNITY_NAND_BASE + 0x0034)
+#define NAND_IMR	(PKUNITY_NAND_BASE + 0x0034)
 /*
  * Chip Enable Reg NAND_CHIPEN
  */
-#define NAND_CHIPEN	__REG(PKUNITY_NAND_BASE + 0x0038)
+#define NAND_CHIPEN	(PKUNITY_NAND_BASE + 0x0038)
 /*
  * Address Reg NAND_ADDR
  */
-#define NAND_ADDR	__REG(PKUNITY_NAND_BASE + 0x003C)
+#define NAND_ADDR	(PKUNITY_NAND_BASE + 0x003C)
 
 /*
  * Command bits NAND_CMD_CMD_MASK

index 33049a8..7b91fe6 100644
@@ -4,47 +4,47 @@
 /*
  * Match Reg 0 OST_OSMR0
  */
-#define OST_OSMR0	__REG(PKUNITY_OST_BASE + 0x0000)
+#define OST_OSMR0	(PKUNITY_OST_BASE + 0x0000)
 /*
  * Match Reg 1 OST_OSMR1
  */
-#define OST_OSMR1	__REG(PKUNITY_OST_BASE + 0x0004)
+#define OST_OSMR1	(PKUNITY_OST_BASE + 0x0004)
 /*
  * Match Reg 2 OST_OSMR2
  */
-#define OST_OSMR2	__REG(PKUNITY_OST_BASE + 0x0008)
+#define OST_OSMR2	(PKUNITY_OST_BASE + 0x0008)
 /*
  * Match Reg 3 OST_OSMR3
  */
-#define OST_OSMR3	__REG(PKUNITY_OST_BASE + 0x000C)
+#define OST_OSMR3	(PKUNITY_OST_BASE + 0x000C)
 /*
  * Counter Reg OST_OSCR
  */
-#define OST_OSCR	__REG(PKUNITY_OST_BASE + 0x0010)
+#define OST_OSCR	(PKUNITY_OST_BASE + 0x0010)
 /*
  * Status Reg OST_OSSR
  */
-#define OST_OSSR	__REG(PKUNITY_OST_BASE + 0x0014)
+#define OST_OSSR	(PKUNITY_OST_BASE + 0x0014)
 /*
  * Watchdog Enable Reg OST_OWER
  */
-#define OST_OWER	__REG(PKUNITY_OST_BASE + 0x0018)
+#define OST_OWER	(PKUNITY_OST_BASE + 0x0018)
 /*
  * Interrupt Enable Reg OST_OIER
  */
-#define OST_OIER	__REG(PKUNITY_OST_BASE + 0x001C)
+#define OST_OIER	(PKUNITY_OST_BASE + 0x001C)
 /*
  * PWM Pulse Width Control Reg OST_PWMPWCR
  */
-#define OST_PWMPWCR	__REG(PKUNITY_OST_BASE + 0x0080)
+#define OST_PWMPWCR	(PKUNITY_OST_BASE + 0x0080)
 /*
  * PWM Duty Cycle Control Reg OST_PWMDCCR
  */
-#define OST_PWMDCCR	__REG(PKUNITY_OST_BASE + 0x0084)
+#define OST_PWMDCCR	(PKUNITY_OST_BASE + 0x0084)
 /*
  * PWM Period Control Reg OST_PWMPCR
  */
-#define OST_PWMPCR	__REG(PKUNITY_OST_BASE + 0x0088)
+#define OST_PWMPCR	(PKUNITY_OST_BASE + 0x0088)
 
 /*
  * Match detected 0 OST_OSSR_M0

140 lines not on this page · raw message

index ed2d2fc..854844a 100644
@@ -4,75 +4,75 @@
 /*
  * PM Control Reg PM_PMCR
  */
-#define PM_PMCR                 __REG(PKUNITY_PM_BASE + 0x0000)
+#define PM_PMCR                 (PKUNITY_PM_BASE + 0x0000)
 /*
  * PM General Conf. Reg PM_PGCR
  */
-#define PM_PGCR                 __REG(PKUNITY_PM_BASE + 0x0004)
+#define PM_PGCR                 (PKUNITY_PM_BASE + 0x0004)
 /*
  * PM PLL Conf. Reg PM_PPCR
  */
-#define PM_PPCR                 __REG(PKUNITY_PM_BASE + 0x0008)
+#define PM_PPCR                 (PKUNITY_PM_BASE + 0x0008)
 /*
  * PM Wakeup Enable Reg PM_PWER
  */
-#define PM_PWER                 __REG(PKUNITY_PM_BASE + 0x000C)
+#define PM_PWER                 (PKUNITY_PM_BASE + 0x000C)
 /*
  * PM GPIO Sleep Status Reg PM_PGSR
  */
-#define PM_PGSR                 __REG(PKUNITY_PM_BASE + 0x0010)
+#define PM_PGSR                 (PKUNITY_PM_BASE + 0x0010)
 /*
  * PM Clock Gate Reg PM_PCGR
  */
-#define PM_PCGR                 __REG(PKUNITY_PM_BASE + 0x0014)
+#define PM_PCGR                 (PKUNITY_PM_BASE + 0x0014)
 /*
  * PM SYS PLL Conf. Reg PM_PLLSYSCFG
  */
-#define PM_PLLSYSCFG            __REG(PKUNITY_PM_BASE + 0x0018)
+#define PM_PLLSYSCFG            (PKUNITY_PM_BASE + 0x0018)
 /*
  * PM DDR PLL Conf. Reg PM_PLLDDRCFG
  */
-#define PM_PLLDDRCFG            __REG(PKUNITY_PM_BASE + 0x001C)
+#define PM_PLLDDRCFG            (PKUNITY_PM_BASE + 0x001C)
 /*
  * PM VGA PLL Conf. Reg PM_PLLVGACFG
  */
-#define PM_PLLVGACFG            __REG(PKUNITY_PM_BASE + 0x0020)
+#define PM_PLLVGACFG            (PKUNITY_PM_BASE + 0x0020)
 /*
  * PM Div Conf. Reg PM_DIVCFG
  */
-#define PM_DIVCFG               __REG(PKUNITY_PM_BASE + 0x0024)
+#define PM_DIVCFG               (PKUNITY_PM_BASE + 0x0024)
 /*
  * PM SYS PLL Status Reg PM_PLLSYSSTATUS
  */
-#define PM_PLLSYSSTATUS         __REG(PKUNITY_PM_BASE + 0x0028)
+#define PM_PLLSYSSTATUS         (PKUNITY_PM_BASE + 0x0028)
 /*
  * PM DDR PLL Status Reg PM_PLLDDRSTATUS
  */
-#define PM_PLLDDRSTATUS         __REG(PKUNITY_PM_BASE + 0x002C)
+#define PM_PLLDDRSTATUS         (PKUNITY_PM_BASE + 0x002C)
 /*
  * PM VGA PLL Status Reg PM_PLLVGASTATUS
  */
-#define PM_PLLVGASTATUS         __REG(PKUNITY_PM_BASE + 0x0030)
+#define PM_PLLVGASTATUS         (PKUNITY_PM_BASE + 0x0030)
 /*
  * PM Div Status Reg PM_DIVSTATUS
  */
-#define PM_DIVSTATUS            __REG(PKUNITY_PM_BASE + 0x0034)
+#define PM_DIVSTATUS            (PKUNITY_PM_BASE + 0x0034)
 /*
  * PM Software Reset Reg PM_SWRESET
  */
-#define PM_SWRESET              __REG(PKUNITY_PM_BASE + 0x0038)
+#define PM_SWRESET              (PKUNITY_PM_BASE + 0x0038)
 /*
  * PM DDR2 PAD Start Reg PM_DDR2START
  */
-#define PM_DDR2START            __REG(PKUNITY_PM_BASE + 0x003C)
+#define PM_DDR2START            (PKUNITY_PM_BASE + 0x003C)
 /*
  * PM DDR2 PAD Status Reg PM_DDR2CAL0
  */
-#define PM_DDR2CAL0             __REG(PKUNITY_PM_BASE + 0x0040)
+#define PM_DDR2CAL0             (PKUNITY_PM_BASE + 0x0040)
 /*
  * PM PLL DFC Done Reg PM_PLLDFCDONE
  */
-#define PM_PLLDFCDONE           __REG(PKUNITY_PM_BASE + 0x0044)
+#define PM_PLLDFCDONE           (PKUNITY_PM_BASE + 0x0044)
 
 #define PM_PMCR_SFB             FIELD(1, 1, 0)
 #define PM_PMCR_IFB             FIELD(1, 1, 1)

index 7da2071..17d4e6d 100644
@@ -4,17 +4,17 @@
 /*
  * the same as I8042_DATA_REG PS2_DATA
  */
-#define PS2_DATA	__REG(PKUNITY_PS2_BASE + 0x0060)
+#define PS2_DATA	(PKUNITY_PS2_BASE + 0x0060)
 /*
  * the same as I8042_COMMAND_REG PS2_COMMAND
  */
-#define PS2_COMMAND	__REG(PKUNITY_PS2_BASE + 0x0064)
+#define PS2_COMMAND	(PKUNITY_PS2_BASE + 0x0064)
 /*
  * the same as I8042_STATUS_REG PS2_STATUS
  */
-#define PS2_STATUS	__REG(PKUNITY_PS2_BASE + 0x0064)
+#define PS2_STATUS	(PKUNITY_PS2_BASE + 0x0064)
 /*
  * counter reg PS2_CNT
  */
-#define PS2_CNT		__REG(PKUNITY_PS2_BASE + 0x0068)
+#define PS2_CNT		(PKUNITY_PS2_BASE + 0x0068)
 

index 1763989..39900cf 100644
@@ -4,11 +4,11 @@
 /*
  * Software Reset Register
  */
-#define RESETC_SWRR	__REG(PKUNITY_RESETC_BASE + 0x0000)
+#define RESETC_SWRR	(PKUNITY_RESETC_BASE + 0x0000)
 /*
  * Reset Status Register
  */
-#define RESETC_RSSR	__REG(PKUNITY_RESETC_BASE + 0x0004)
+#define RESETC_RSSR	(PKUNITY_RESETC_BASE + 0x0004)
 
 /*
  * Software Reset Bit

index 155e387..e94ca19 100644
@@ -4,19 +4,19 @@
 /*
  * RTC Alarm Reg RTC_RTAR
  */
-#define RTC_RTAR	__REG(PKUNITY_RTC_BASE + 0x0000)
+#define RTC_RTAR	(PKUNITY_RTC_BASE + 0x0000)
 /*
  * RTC Count Reg RTC_RCNR
  */
-#define RTC_RCNR	__REG(PKUNITY_RTC_BASE + 0x0004)
+#define RTC_RCNR	(PKUNITY_RTC_BASE + 0x0004)
 /*
  * RTC Trim Reg RTC_RTTR
  */
-#define RTC_RTTR	__REG(PKUNITY_RTC_BASE + 0x0008)
+#define RTC_RTTR	(PKUNITY_RTC_BASE + 0x0008)
 /*
  * RTC Status Reg RTC_RTSR
  */
-#define RTC_RTSR	__REG(PKUNITY_RTC_BASE + 0x0010)
+#define RTC_RTSR	(PKUNITY_RTC_BASE + 0x0010)
 
 /*
  * ALarm detected RTC_RTSR_AL

index 3457b88..1303ecf 100644
@@ -4,67 +4,67 @@
 /*
  * Clock Control Reg SDC_CCR
  */
-#define SDC_CCR		__REG(PKUNITY_SDC_BASE + 0x0000)
+#define SDC_CCR		(PKUNITY_SDC_BASE + 0x0000)
 /*
  * Software Reset Reg SDC_SRR
  */
-#define SDC_SRR		__REG(PKUNITY_SDC_BASE + 0x0004)
+#define SDC_SRR		(PKUNITY_SDC_BASE + 0x0004)
 /*
  * Argument Reg SDC_ARGUMENT
  */
-#define SDC_ARGUMENT	__REG(PKUNITY_SDC_BASE + 0x0008)
+#define SDC_ARGUMENT	(PKUNITY_SDC_BASE + 0x0008)
 /*
  * Command Reg SDC_COMMAND
  */
-#define SDC_COMMAND	__REG(PKUNITY_SDC_BASE + 0x000C)
+#define SDC_COMMAND	(PKUNITY_SDC_BASE + 0x000C)
 /*
  * Block Size Reg SDC_BLOCKSIZE
  */
-#define SDC_BLOCKSIZE	__REG(PKUNITY_SDC_BASE + 0x0010)
+#define SDC_BLOCKSIZE	(PKUNITY_SDC_BASE + 0x0010)
 /*
  * Block Cound Reg SDC_BLOCKCOUNT
  */
-#define SDC_BLOCKCOUNT	__REG(PKUNITY_SDC_BASE + 0x0014)
+#define SDC_BLOCKCOUNT	(PKUNITY_SDC_BASE + 0x0014)
 /*
  * Transfer Mode Reg SDC_TMR
  */
-#define SDC_TMR		__REG(PKUNITY_SDC_BASE + 0x0018)
+#define SDC_TMR		(PKUNITY_SDC_BASE + 0x0018)
 /*
  * Response Reg. 0 SDC_RES0
  */
-#define SDC_RES0	__REG(PKUNITY_SDC_BASE + 0x001C)
+#define SDC_RES0	(PKUNITY_SDC_BASE + 0x001C)
 /*
  * Response Reg. 1 SDC_RES1
  */
-#define SDC_RES1	__REG(PKUNITY_SDC_BASE + 0x0020)
+#define SDC_RES1	(PKUNITY_SDC_BASE + 0x0020)
 /*
  * Response Reg. 2 SDC_RES2
  */
-#define SDC_RES2	__REG(PKUNITY_SDC_BASE + 0x0024)
+#define SDC_RES2	(PKUNITY_SDC_BASE + 0x0024)
 /*
  * Response Reg. 3 SDC_RES3
  */
-#define SDC_RES3	__REG(PKUNITY_SDC_BASE + 0x0028)
+#define SDC_RES3	(PKUNITY_SDC_BASE + 0x0028)
 /*
  * Read Timeout Control Reg SDC_RTCR
  */
-#define SDC_RTCR	__REG(PKUNITY_SDC_BASE + 0x002C)
+#define SDC_RTCR	(PKUNITY_SDC_BASE + 0x002C)
 /*
  * Interrupt Status Reg SDC_ISR
  */
-#define SDC_ISR		__REG(PKUNITY_SDC_BASE + 0x0030)
+#define SDC_ISR		(PKUNITY_SDC_BASE + 0x0030)
 /*
  * Interrupt Status Mask Reg SDC_ISMR
  */
-#define SDC_ISMR	__REG(PKUNITY_SDC_BASE + 0x0034)
+#define SDC_ISMR	(PKUNITY_SDC_BASE + 0x0034)
 /*
  * RX FIFO SDC_RXFIFO
  */
-#define SDC_RXFIFO	__REG(PKUNITY_SDC_BASE + 0x0038)
+#define SDC_RXFIFO	(PKUNITY_SDC_BASE + 0x0038)
 /*
  * TX FIFO SDC_TXFIFO
  */
-#define SDC_TXFIFO	__REG(PKUNITY_SDC_BASE + 0x003C)
+#define SDC_TXFIFO	(PKUNITY_SDC_BASE + 0x003C)
 
 /*
  * SD Clock Enable SDC_CCR_CLKEN

index cadc713..de16895 100644
@@ -4,27 +4,27 @@
 /*
  * Control reg. 0 SPI_CR0
  */
-#define SPI_CR0		__REG(PKUNITY_SPI_BASE + 0x0000)
+#define SPI_CR0		(PKUNITY_SPI_BASE + 0x0000)
 /*
  * Control reg. 1 SPI_CR1
  */
-#define SPI_CR1		__REG(PKUNITY_SPI_BASE + 0x0004)
+#define SPI_CR1		(PKUNITY_SPI_BASE + 0x0004)
 /*
  * Enable reg SPI_SSIENR
  */
-#define SPI_SSIENR	__REG(PKUNITY_SPI_BASE + 0x0008)
+#define SPI_SSIENR	(PKUNITY_SPI_BASE + 0x0008)
 /*
  * Status reg SPI_SR
  */
-#define SPI_SR		__REG(PKUNITY_SPI_BASE + 0x0028)
+#define SPI_SR		(PKUNITY_SPI_BASE + 0x0028)
 /*
  * Interrupt Mask reg SPI_IMR
  */
-#define SPI_IMR		__REG(PKUNITY_SPI_BASE + 0x002C)
+#define SPI_IMR		(PKUNITY_SPI_BASE + 0x002C)
 /*
  * Interrupt Status reg SPI_ISR
  */
-#define SPI_ISR		__REG(PKUNITY_SPI_BASE + 0x0030)
+#define SPI_ISR		(PKUNITY_SPI_BASE + 0x0030)
 
 /*
  * Enable SPI Controller SPI_SSIENR_EN