VMState port of all cpus

index f01838f..557eba4 100644
@@ -1457,6 +1457,8 @@ void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
                 n_elems = field->num;
             } else if (field->flags & VMS_VARRAY_INT32) {
                 n_elems = *(int32_t *)(opaque+field->num_offset);
+            } else if (field->flags & VMS_VARRAY_UINT32) {
+                n_elems = *(uint32_t *)(opaque+field->num_offset);
             } else if (field->flags & VMS_VARRAY_UINT16) {
                 n_elems = *(uint16_t *)(opaque+field->num_offset);
             } else if (field->flags & VMS_VARRAY_UINT8) {

index 9dc4edb..165cfe8 100644
@@ -591,7 +591,7 @@ void cpu_exec_init_all(void)
 #endif
 }
 
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
 
 static int cpu_common_post_load(void *opaque, int version_id)
 {

@@ -658,11 +658,13 @@ void cpu_exec_init(CPUState *env)
 #if defined(CONFIG_USER_ONLY)
     cpu_list_unlock();
 #endif
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
     vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
+#if defined(CPU_SAVE_VERSION)
     register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
                     cpu_save, cpu_load, env);
 #endif
+#endif
 }
 
 /* Allocate a new translation block. Flush the translation buffer if

index 165cfe8..09f3f01 100644
@@ -663,6 +663,8 @@ void cpu_exec_init(CPUState *env)
 #if defined(CPU_SAVE_VERSION)
     register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
                     cpu_save, cpu_load, env);
+#else
+    vmstate_register(NULL, cpu_index, &vmstate_cpu, env);
 #endif
 #endif
 }

index ed20f5a..0f0200a 100644
@@ -359,6 +359,8 @@ extern const VMStateInfo vmstate_info_ptimer;
 extern const VMStateInfo vmstate_info_buffer;
 extern const VMStateInfo vmstate_info_unused_buffer;
 
+extern const VMStateDescription vmstate_cpu;
+
 #define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0)
 #define type_check_pointer(t1,t2) ((t1**)0 - (t2*)0)
 

index 76d70d9..8d32d7c 100644
@@ -68,20 +68,10 @@ static VMStateField vmstate_cpu_fields[] = {
     VMSTATE_END_OF_LIST()
 };
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
     .name = "cpu",
     .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields = vmstate_cpu_fields,
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}

index 25fa97d..54f5643 100644
@@ -310,7 +310,7 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
     }
 };
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
     .name = "cpu",
     .version_id = CPU_SAVE_VERSION,
     .minimum_version_id = 3,

index 70ca52a..9014a9f 100644
@@ -1,7 +1,7 @@
 #include "hw/hw.h"
 #include "hw/boards.h"
 
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
     .name = "cpu",
     .version_id = CPU_SAVE_VERSION,
     .minimum_version_id = 1,

index e69de29..86b6fe9 100644
@@ -0,0 +1,10 @@
+
+#include "hw/hw.h"
+
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
+
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index 3e79be6..5a7b219 100644
@@ -18,13 +18,11 @@
  */
 
 #include "hw/hw.h"
-#include "hw/boards.h"
 
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
 
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return 0;
-}
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index e69de29..86b6fe9 100644
@@ -0,0 +1,10 @@
+
+#include "hw/hw.h"
+
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
+
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index ddeffb2..3f98330 100644
@@ -26,13 +26,11 @@
  */
 
 #include "hw/hw.h"
-#include "hw/boards.h"
 
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
 
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return 0;
-}
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index b4e72cf..5632272 100644
@@ -132,8 +132,6 @@ int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
                               int mmu_idx);
 
-#define CPU_SAVE_VERSION 2
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user

index a973f2e..ef6f9f4 100644
@@ -949,8 +949,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
 #define cpu_list_id x86_cpu_list
 #define cpudef_setup	x86_cpudef_setup
 
-#define CPU_SAVE_VERSION 13
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user

index 54f5643..0ecbfe9 100644
@@ -312,7 +312,7 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
 
 const VMStateDescription vmstate_cpu = {
     .name = "cpu",
-    .version_id = CPU_SAVE_VERSION,
+    .version_id = 13,
     .minimum_version_id = 3,
     .minimum_version_id_old = 3,
     .pre_save = cpu_pre_save,

@@ -426,13 +426,3 @@ const VMStateDescription vmstate_cpu = {
         }
     }
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}

index 037ef52..bd37af8 100644
@@ -202,8 +202,6 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
 #define cpu_gen_code cpu_lm32_gen_code
 #define cpu_signal_handler cpu_lm32_signal_handler
 
-#define CPU_SAVE_VERSION 1
-
 int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
                               int mmu_idx);
 #define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault

index 9014a9f..e9ed250 100644
@@ -3,7 +3,7 @@
 
 const VMStateDescription vmstate_cpu = {
     .name = "cpu",
-    .version_id = CPU_SAVE_VERSION,
+    .version_id = 1,
     .minimum_version_id = 1,
     .minimum_version_id_old = 1,
     .fields      = (VMStateField[]) {

@@ -21,13 +21,3 @@ const VMStateDescription vmstate_cpu = {
         VMSTATE_END_OF_LIST()
     }
 };
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}

index 3530286..fc5c098 100644
@@ -287,8 +287,6 @@ enum {
 #define cpu_gen_code cpu_mb_gen_code
 #define cpu_signal_handler cpu_mb_signal_handler
 
-#define CPU_SAVE_VERSION 1
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _nommu
 #define MMU_MODE1_SUFFIX _kernel

index 1be1c35..86b6fe9 100644
@@ -1,11 +1,10 @@
+
 #include "hw/hw.h"
-#include "hw/boards.h"
 
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+   here.  Other things need to be done elsewhere */
 
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
-    return 0;
-}
+const VMStateDescription vmstate_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};

index 8ae0ce3..2cec75c 100644
@@ -99,6 +99,11 @@
 
 #define NB_MMU_MODES 2
 
+typedef struct {
+    uint32_t hi;
+    uint32_t lo;
+} TLBSet;
+
 typedef struct CPUCRISState {
 	uint32_t regs[16];
 	/* P0 - P15 are referred to as special registers in the docs.  */

@@ -152,11 +157,7 @@ typedef struct CPUCRISState {
 	 *
 	 * One for I and another for D.
 	 */
-	struct
-	{
-		uint32_t hi;
-		uint32_t lo;
-	} tlbsets[2][4][16];
+	TLBSet tlbsets[2][4][16];
 
 	CPU_COMMON
 

@@ -214,8 +215,6 @@ enum {
 #define cpu_gen_code cpu_cris_gen_code
 #define cpu_signal_handler cpu_cris_signal_handler
 
-#define CPU_SAVE_VERSION 1
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user

144 lines not on this page · raw message

index 1c40d43..226b4a5 100644
@@ -32,7 +32,6 @@ void cpu_save(QEMUFile *f, void *opaque)
     }
     qemu_put_be32s(f, &env->fpscr);
     qemu_put_sbe32s(f, &env->access_type);
-#if !defined(CONFIG_USER_ONLY)
 #if defined(TARGET_PPC64)
     qemu_put_betls(f, &env->asr);
     qemu_put_sbe32s(f, &env->slb_nr);

@@ -62,7 +61,6 @@ void cpu_save(QEMUFile *f, void *opaque)
     }
     for (i = 0; i < 4; i++)
         qemu_put_betls(f, &env->pb[i]);
-#endif
     for (i = 0; i < 1024; i++)
         qemu_put_betls(f, &env->spr[i]);
     qemu_put_be32s(f, &env->vscr);

@@ -72,7 +70,6 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_be32s(f, &env->flags);
     qemu_put_sbe32s(f, &env->error_code);
     qemu_put_be32s(f, &env->pending_interrupts);
-#if !defined(CONFIG_USER_ONLY)
     qemu_put_be32s(f, &env->irq_input_state);
     for (i = 0; i < POWERPC_EXCP_NB; i++)
         qemu_put_betls(f, &env->excp_vectors[i]);

@@ -81,7 +78,6 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_betls(f, &env->ivor_mask);
     qemu_put_betls(f, &env->ivpr_mask);
     qemu_put_betls(f, &env->hreset_vector);
-#endif
     qemu_put_betls(f, &env->nip);
     qemu_put_betls(f, &env->hflags);
     qemu_put_betls(f, &env->hflags_nmsr);

@@ -120,7 +116,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     }
     qemu_get_be32s(f, &env->fpscr);
     qemu_get_sbe32s(f, &env->access_type);
-#if !defined(CONFIG_USER_ONLY)
 #if defined(TARGET_PPC64)
     qemu_get_betls(f, &env->asr);
     qemu_get_sbe32s(f, &env->slb_nr);

@@ -150,7 +145,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     }
     for (i = 0; i < 4; i++)
         qemu_get_betls(f, &env->pb[i]);
-#endif
     for (i = 0; i < 1024; i++)
         qemu_get_betls(f, &env->spr[i]);
     ppc_store_sdr1(env, sdr1);

@@ -161,7 +155,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     qemu_get_be32s(f, &env->flags);
     qemu_get_sbe32s(f, &env->error_code);
     qemu_get_be32s(f, &env->pending_interrupts);
-#if !defined(CONFIG_USER_ONLY)
     qemu_get_be32s(f, &env->irq_input_state);
     for (i = 0; i < POWERPC_EXCP_NB; i++)
         qemu_get_betls(f, &env->excp_vectors[i]);

@@ -170,7 +163,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     qemu_get_betls(f, &env->ivor_mask);
     qemu_get_betls(f, &env->ivpr_mask);
     qemu_get_betls(f, &env->hreset_vector);
-#endif
     qemu_get_betls(f, &env->nip);
     qemu_get_betls(f, &env->hflags);
     qemu_get_betls(f, &env->hflags_nmsr);

index 0f0200a..014cdc1 100644
@@ -354,6 +354,8 @@ extern const VMStateInfo vmstate_info_uint16;
 extern const VMStateInfo vmstate_info_uint32;
 extern const VMStateInfo vmstate_info_uint64;
 
+extern const VMStateInfo vmstate_info_float32;
+
 extern const VMStateInfo vmstate_info_timer;
 extern const VMStateInfo vmstate_info_ptimer;
 extern const VMStateInfo vmstate_info_buffer;

@@ -875,6 +877,9 @@ extern const VMStateDescription vmstate_hid_ptr_device;
 #define VMSTATE_INT64_ARRAY(_f, _s, _n)                               \
     VMSTATE_INT64_ARRAY_V(_f, _s, _n, 0)
 
+#define VMSTATE_FLOAT32_ARRAY(_f, _s, _n)                             \
+    VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float32, float32)
+
 #define VMSTATE_BUFFER_V(_f, _s, _v)                                  \
     VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
 

index 557eba4..cd0178c 100644
@@ -1027,6 +1027,36 @@ const VMStateInfo vmstate_info_uint16_equal = {
     .put  = put_uint16,
 };
 
+/* 32 bit float */
+
+typedef union {
+    float32 f;
+    uint32_t i;
+} VMStateFloat32;
+
+static int get_float32(QEMUFile *f, void *pv, size_t size)
+{
+    float32 *v = pv;
+    VMStateFloat32 u;
+    qemu_get_be32s(f, &u.i);
+    *v = u.f;
+    return 0;
+}
+
+static void put_float32(QEMUFile *f, void *pv, size_t size)
+{
+    float32 *v = pv;
+    VMStateFloat32 u;
+    u.f = *v;
+    qemu_put_be32s(f, &u.i);
+}
+
+const VMStateInfo vmstate_info_float32 = {
+    .name = "float32",
+    .get  = get_float32,
+    .put  = put_float32,
+};
+
 /* timers  */
 
 static int get_timer(QEMUFile *f, void *pv, size_t size)

index 014cdc1..3044cec 100644
@@ -355,6 +355,7 @@ extern const VMStateInfo vmstate_info_uint32;
 extern const VMStateInfo vmstate_info_uint64;
 
 extern const VMStateInfo vmstate_info_float32;
+extern const VMStateInfo vmstate_info_float64;
 
 extern const VMStateInfo vmstate_info_timer;
 extern const VMStateInfo vmstate_info_ptimer;

@@ -880,6 +881,9 @@ extern const VMStateDescription vmstate_hid_ptr_device;
 #define VMSTATE_FLOAT32_ARRAY(_f, _s, _n)                             \
     VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float32, float32)
 
+#define VMSTATE_FLOAT64_ARRAY(_f, _s, _n)                             \
+    VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float64, float64)
+
 #define VMSTATE_BUFFER_V(_f, _s, _v)                                  \
     VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
 

index cd0178c..2e191ad 100644
@@ -1057,6 +1057,36 @@ const VMStateInfo vmstate_info_float32 = {
     .put  = put_float32,
 };
 
+/* 64 bit float */
+
+typedef union {
+    float64 d;
+    uint64_t l;
+} VMStateFloat64;
+
+static int get_float64(QEMUFile *f, void *pv, size_t size)
+{
+    float64 *v = pv;
+    VMStateFloat64 u;
+    qemu_get_be64s(f, &u.l);
+    *v = u.d;
+    return 0;
+}
+
+static void put_float64(QEMUFile *f, void *pv, size_t size)
+{
+    float64 *v = pv;
+    VMStateFloat64 u;
+    u.d = *v;
+    qemu_put_be64s(f, &u.l);
+}
+
+const VMStateInfo vmstate_info_float64 = {
+    .name = "float64",
+    .get  = get_float64,
+    .put  = put_float64,
+};
+
 /* timers  */
 
 static int get_timer(QEMUFile *f, void *pv, size_t size)

index 3044cec..798732f 100644
@@ -533,6 +533,16 @@ extern const VMStateDescription vmstate_cpu;
     .offset     = offsetof(_state, _field),                          \
 }
 
+#define VMSTATE_STRUCT_VARRAY_INT32_TEST(_field, _state, _field_num, _test, _vmsd, _type) { \
+    .name       = (stringify(_field)),                               \
+    .num_offset = vmstate_offset_value(_state, _field_num, int32_t), \
+    .vmsd       = &(_vmsd),                                          \
+    .field_exists = (_test),                                         \
+    .size       = sizeof(_type),                                     \
+    .flags      = VMS_STRUCT|VMS_VARRAY_INT32,                       \
+    .offset     = offsetof(_state, _field),                          \
+}
+
 #define VMSTATE_STRUCT_VARRAY_POINTER_INT32(_field, _state, _field_num, _vmsd, _type) { \
     .name       = (stringify(_field)),                               \
     .version_id = 0,                                                 \

index 3f77e30..e7f6625 100644
@@ -1029,6 +1029,8 @@ struct CPUPPCState {
      */
     uint8_t fit_period[4];
     uint8_t wdt_period[4];
+
+    target_ulong sdr1_vmstate;
 };
 
 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \

@@ -1183,8 +1185,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
 #define cpu_signal_handler cpu_ppc_signal_handler
 #define cpu_list ppc_cpu_list
 
-#define CPU_SAVE_VERSION 4
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _user
 #define MMU_MODE1_SUFFIX _kernel

259 lines not on this page · raw message

index 798732f..727d563 100644
@@ -300,6 +300,7 @@ enum VMStateFlags {
     VMS_MULTIPLY         = 0x200,  /* multiply "size" field by field_size */
     VMS_VARRAY_UINT8     = 0x400,  /* Array with size in uint8_t field*/
     VMS_VARRAY_UINT32    = 0x800,  /* Array with size in uint32_t field*/
+    VMS_MULTIPLY_ELEMENTS= 0x1000,  /* multiply "size" field by field_size */
 };
 
 typedef struct {

@@ -424,6 +425,16 @@ extern const VMStateDescription vmstate_cpu;
     .offset     = vmstate_offset_array(_state, _field, _type, _num), \
 }
 
+#define VMSTATE_VARRAY_MULTIPLY(_field, _state, _field_num, _multiply, _info, _type) { \
+    .name       = (stringify(_field)),                               \
+    .num_offset = vmstate_offset_value(_state, _field_num, uint32_t),\
+    .num        = (_multiply),                                       \
+    .info       = &(_info),                                          \
+    .size       = sizeof(_type),                                     \
+    .flags      = VMS_VARRAY_UINT32|VMS_MULTIPLY_ELEMENTS,           \
+    .offset     = offsetof(_state, _field),                          \
+}
+
 #define VMSTATE_ARRAY_TEST(_field, _state, _num, _test, _info, _type) {\
     .name         = (stringify(_field)),                              \
     .field_exists = (_test),                                          \

index 2e191ad..8ef46a1 100644
@@ -1460,6 +1460,9 @@ int vmstate_load_state(QEMUFile *f, const VMStateDescription *vmsd,
             } else if (field->flags & VMS_VARRAY_UINT8) {
                 n_elems = *(uint8_t *)(opaque+field->num_offset);
             }
+            if (field->flags & VMS_MULTIPLY_ELEMENTS) {
+                    n_elems *= field->num;
+            }
             if (field->flags & VMS_POINTER) {
                 base_addr = *(void **)base_addr + field->start;
             }

@@ -1524,6 +1527,9 @@ void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
             } else if (field->flags & VMS_VARRAY_UINT8) {
                 n_elems = *(uint8_t *)(opaque+field->num_offset);
             }
+            if (field->flags & VMS_MULTIPLY_ELEMENTS) {
+                    n_elems *= field->num;
+            }
             if (field->flags & VMS_POINTER) {
                 base_addr = *(void **)base_addr + field->start;
             }

index 727d563..306127a 100644
@@ -947,11 +947,13 @@ extern const VMStateDescription vmstate_hid_ptr_device;
     VMSTATE_UINT64_V(_f, _s, _v)
 #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v)                        \
     VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttls vmstate_info_uint64
 #else
 #define VMSTATE_UINTTL_V(_f, _s, _v)                                  \
     VMSTATE_UINT32_V(_f, _s, _v)
 #define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v)                        \
     VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttls vmstate_info_uint32
 #endif
 #define VMSTATE_UINTTL(_f, _s)                                        \
     VMSTATE_UINTTL_V(_f, _s, 0)

index eaaefe3..b0f671d 100644
@@ -324,26 +324,6 @@ typedef struct ResetData {
     uint64_t prom_addr;
 } ResetData;
 
-void cpu_put_timer(QEMUFile *f, CPUTimer *s)
-{
-    qemu_put_be32s(f, &s->frequency);
-    qemu_put_be32s(f, &s->disabled);
-    qemu_put_be64s(f, &s->disabled_mask);
-    qemu_put_sbe64s(f, &s->clock_offset);
-
-    qemu_put_timer(f, s->qtimer);
-}
-
-void cpu_get_timer(QEMUFile *f, CPUTimer *s)
-{
-    qemu_get_be32s(f, &s->frequency);
-    qemu_get_be32s(f, &s->disabled);
-    qemu_get_be64s(f, &s->disabled_mask);
-    qemu_get_sbe64s(f, &s->clock_offset);
-
-    qemu_get_timer(f, s->qtimer);
-}
-
 static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
                                   QEMUBHFunc *cb, uint32_t frequency,
                                   uint64_t disabled_mask)

index 6bf9275..ae554c9 100644
@@ -352,10 +352,6 @@ struct CPUTimer
 
 typedef struct CPUTimer CPUTimer;
 
-struct QEMUFile;
-void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
-void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
-
 typedef struct CPUSPARCState {
     target_ulong gregs[8]; /* general registers */
     target_ulong *regwptr; /* pointer to current register window */

@@ -482,6 +478,8 @@ typedef struct CPUSPARCState {
 
     /* Leon3 cache control */
     uint32_t cache_control;
+
+    uint32_t psr_vmstate;
 } CPUSPARCState;
 
 #ifndef NO_CPU_IO_DEFS

@@ -569,8 +567,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 #define cpu_signal_handler cpu_sparc_signal_handler
 #define cpu_list sparc_cpu_list
 
-#define CPU_SAVE_VERSION 7
-
 /* MMU modes definitions */
 #if defined (TARGET_SPARC64)
 #define MMU_USER_IDX   0

502 lines not on this page · raw message

index 2186756..ccca36f 100644
@@ -74,9 +74,9 @@ static int cpu_post_load(void *opaque, int version_id)
 
 const VMStateDescription vmstate_cpu = {
     .name = "cpu",
-    .version_id = 7,
-    .minimum_version_id = 7,
-    .minimum_version_id_old = 7,
+    .version_id = 8,
+    .minimum_version_id = 8,
+    .minimum_version_id_old = 8,
     .pre_save = cpu_pre_save,
     .post_load = cpu_post_load,
    .fields      = (VMStateField[]) {

@@ -106,166 +106,12 @@ const VMStateDescription vmstate_cpu = {
         VMSTATE_UINT64_ARRAY(mmubpregs, CPUState, 4),
 #else
         VMSTATE_UINT64(lsu, CPUState),
-        VMSTATE_UINT64(immuregs[0], CPUState),
-        VMSTATE_UINT64(dmmuregs[0], CPUState),
-        VMSTATE_UINT64(immuregs[1], CPUState),
-        VMSTATE_UINT64(dmmuregs[1], CPUState),
-        VMSTATE_UINT64(immuregs[2], CPUState),
-        VMSTATE_UINT64(dmmuregs[2], CPUState),
-        VMSTATE_UINT64(immuregs[3], CPUState),
-        VMSTATE_UINT64(dmmuregs[3], CPUState),
-        VMSTATE_UINT64(immuregs[4], CPUState),
-        VMSTATE_UINT64(dmmuregs[4], CPUState),
-        VMSTATE_UINT64(immuregs[5], CPUState),
-        VMSTATE_UINT64(dmmuregs[5], CPUState),
-        VMSTATE_UINT64(immuregs[6], CPUState),
-        VMSTATE_UINT64(dmmuregs[6], CPUState),
-        VMSTATE_UINT64(immuregs[7], CPUState),
-        VMSTATE_UINT64(dmmuregs[7], CPUState),
-        VMSTATE_UINT64(immuregs[8], CPUState),
-        VMSTATE_UINT64(dmmuregs[8], CPUState),
-        VMSTATE_UINT64(immuregs[9], CPUState),
-        VMSTATE_UINT64(dmmuregs[9], CPUState),
-        VMSTATE_UINT64(immuregs[10], CPUState),
-        VMSTATE_UINT64(dmmuregs[10], CPUState),
-        VMSTATE_UINT64(immuregs[11], CPUState),
-        VMSTATE_UINT64(dmmuregs[11], CPUState),
-        VMSTATE_UINT64(immuregs[12], CPUState),
-        VMSTATE_UINT64(dmmuregs[12], CPUState),
-        VMSTATE_UINT64(immuregs[13], CPUState),
-        VMSTATE_UINT64(dmmuregs[13], CPUState),
-        VMSTATE_UINT64(immuregs[14], CPUState),
-        VMSTATE_UINT64(dmmuregs[14], CPUState),
-        VMSTATE_UINT64(immuregs[15], CPUState),
-        VMSTATE_UINT64(dmmuregs[15], CPUState),
-        VMSTATE_STRUCT(itlb[0], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[0], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[1], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[1], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[2], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[2], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[3], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[3], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[4], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[4], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[5], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[5], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[6], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[6], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[7], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[7], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[8], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[8], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[9], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[9], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[10], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[10], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[11], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[11], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[12], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[12], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[13], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[13], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[14], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[14], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[15], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[15], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[16], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[16], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[17], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[17], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[18], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[18], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[19], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[19], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[20], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[20], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[21], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[21], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[22], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[22], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[23], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[23], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[24], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[24], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[25], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[25], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[26], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[26], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[27], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[27], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[28], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[28], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[29], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[29], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[30], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[30], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[31], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[31], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[32], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[32], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[33], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[33], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[34], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[34], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[35], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[35], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[36], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[36], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[37], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[37], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[38], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[38], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[39], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[39], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[40], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[40], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[41], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[41], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[42], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[42], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[43], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[43], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[44], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[44], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[45], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[45], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[46], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[46], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[47], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[47], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[48], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[48], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[49], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[49], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[50], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[50], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[51], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[51], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[52], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[52], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[53], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[53], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[54], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[54], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[55], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[55], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[56], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[56], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[57], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[57], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[58], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[58], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[59], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[59], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[60], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[60], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[61], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[61], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[62], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[62], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(itlb[63], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
-        VMSTATE_STRUCT(dtlb[63], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+        VMSTATE_UINT64_ARRAY(immuregs, CPUState, 16),
+        VMSTATE_UINT64_ARRAY(dmmuregs, CPUState, 16),
+        VMSTATE_STRUCT_ARRAY(itlb, CPUState, 64, 0,
+                             vmstate_tlb_entry, SparcTLBEntry),
+        VMSTATE_STRUCT_ARRAY(dtlb, CPUState, 64, 0,
+                             vmstate_tlb_entry, SparcTLBEntry),
         VMSTATE_UINT32(mmu_version, CPUState),
         VMSTATE_STRUCT_ARRAY(ts, CPUState, MAXTL_MAX, 0,
                              vmstate_trap_state, trap_state),

index 04921c1..d96b7dc 100644
@@ -281,7 +281,6 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
         exit(1);
     }
 
-    register_savevm(NULL, "cpu", 0, 3, cpu_save, cpu_load, env);
     qemu_register_reset(main_cpu_reset, env);
 
     /* fulong 2e has 256M ram. */

index bb49749..cd40e7b 100644
@@ -732,8 +732,8 @@ static int64_t load_kernel (void)
 
 static void malta_mips_config(CPUState *env)
 {
-    env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
-                         ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
+    env->mvp.CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
+                          ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
 }
 
 static void main_cpu_reset(void *opaque)

index 79e2558..e11865b 100644
@@ -473,7 +473,7 @@ struct CPUMIPSState {
 
     CPU_COMMON
 
-    CPUMIPSMVPContext *mvp;
+    CPUMIPSMVPContext mvp;
 #if !defined(CONFIG_USER_ONLY)
     CPUMIPSTLBContext *tlb;
 #endif

@@ -675,7 +675,7 @@ static inline int mips_vpe_active(CPUState *env)
     int active = 1;
 
     /* Check that the VPE is enabled.  */
-    if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
+    if (!(env->mvp.CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
         active = 0;
     }
     /* Check that the VPE is actived.  */

index be72b36..8137488 100644
@@ -52,9 +52,9 @@ void cpu_save(QEMUFile *f, void *opaque)
     save_fpu(f, &env->active_fpu);
 
     /* Save MVP */
-    qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
-    qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
-    qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
+    qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl);
+    qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0);
+    qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
 
     /* Save TLB */
     qemu_put_be32s(f, &env->tlb->nb_tlb);

@@ -203,9 +203,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     load_fpu(f, &env->active_fpu);
 
     /* Load MVP */
-    qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
-    qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
-    qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
+    qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl);
+    qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0);
+    qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
 
     /* Load TLB */
     qemu_get_be32s(f, &env->tlb->nb_tlb);

index c51b9cb..a5d095c 100644
@@ -909,17 +909,17 @@ static void sync_c0_entryhi(CPUState *cpu, int tc)
 /* CP0 helpers */
 target_ulong helper_mfc0_mvpcontrol (void)
 {
-    return env->mvp->CP0_MVPControl;
+    return env->mvp.CP0_MVPControl;
 }
 
 target_ulong helper_mfc0_mvpconf0 (void)
 {
-    return env->mvp->CP0_MVPConf0;
+    return env->mvp.CP0_MVPConf0;
 }
 
 target_ulong helper_mfc0_mvpconf1 (void)
 {
-    return env->mvp->CP0_MVPConf1;
+    return env->mvp.CP0_MVPConf1;
 }
 
 target_ulong helper_mfc0_random (void)

@@ -1172,13 +1172,14 @@ void helper_mtc0_mvpcontrol (target_ulong arg1)
     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
                 (1 << CP0MVPCo_EVP);
-    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+    if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
         mask |= (1 << CP0MVPCo_STLB);
-    newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
+    }
+    newval = (env->mvp.CP0_MVPControl & ~mask) | (arg1 & mask);
 
     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 
-    env->mvp->CP0_MVPControl = newval;
+    env->mvp.CP0_MVPControl = newval;
 }
 
 void helper_mtc0_vpecontrol (target_ulong arg1)

@@ -1266,9 +1267,10 @@ void helper_mtc0_vpeconf1 (target_ulong arg1)
     uint32_t mask = 0;
     uint32_t newval;
 
-    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+    if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
                 (0xff << CP0VPEC1_NCP1);
+    }
     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
 
     /* UDI not implemented. */

@@ -1325,8 +1327,9 @@ void helper_mtc0_tcbind (target_ulong arg1)
     uint32_t mask = (1 << CP0TCBd_TBE);
     uint32_t newval;
 
-    if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+    if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
         mask |= (1 << CP0TCBd_CurVPE);
+    }
     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
     env->active_tc.CP0_TCBind = newval;
 }

@@ -1338,8 +1341,9 @@ void helper_mttc0_tcbind (target_ulong arg1)
     uint32_t newval;
     CPUState *other = mips_cpu_map_tc(&other_tc);
 
-    if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+    if (other->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
         mask |= (1 << CP0TCBd_CurVPE);
+    }
     if (other_tc == other->current_tc) {
         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
         other->active_tc.CP0_TCBind = newval;

@@ -1910,12 +1914,12 @@ target_ulong helper_emt(void)
 target_ulong helper_dvpe(void)
 {
     CPUState *other_cpu = first_cpu;
-    target_ulong prev = env->mvp->CP0_MVPControl;
+    target_ulong prev = env->mvp.CP0_MVPControl;
 
     do {
         /* Turn off all VPEs except the one executing the dvpe.  */
         if (other_cpu != env) {
-            other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+            other_cpu->mvp.CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
             mips_vpe_sleep(other_cpu);
         }
         other_cpu = other_cpu->next_cpu;

@@ -1926,14 +1930,14 @@ target_ulong helper_dvpe(void)
 target_ulong helper_evpe(void)
 {
     CPUState *other_cpu = first_cpu;
-    target_ulong prev = env->mvp->CP0_MVPControl;
+    target_ulong prev = env->mvp.CP0_MVPControl;
 
     do {
         if (other_cpu != env
            /* If the VPE is WFI, dont distrub it's sleep.  */
            && !mips_vpe_is_wfi(other_cpu)) {
             /* Enable the VPE.  */
-            other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+            other_cpu->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
             mips_vpe_wake(other_cpu); /* And wake it up.  */
         }
         other_cpu = other_cpu->next_cpu;

index d5b1c76..c655a34 100644
@@ -5533,7 +5533,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
          (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
         tcg_gen_movi_tl(t0, -1);
     else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
-             (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+             (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
         tcg_gen_movi_tl(t0, -1);
     else if (u == 0) {
         switch (rt) {

@@ -5751,7 +5751,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
          (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
         /* NOP */ ;
     else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
-             (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+             (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
         /* NOP */ ;
     else if (u == 0) {
         switch (rd) {

@@ -12827,7 +12827,7 @@ void cpu_reset (CPUMIPSState *env)
 
         if (!env->cpu_index) {
             /* VPE0 starts up enabled.  */
-            env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+            env->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
             env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 
             /* TC0 starts up unhalted.  */

index c39138f..54fd1eb 100644
@@ -568,27 +568,25 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 
 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
-
     /* MVPConf1 implemented, TLB sharable, no gating storage support,
        programmable cache partitioning implemented, number of allocatable
        and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
        implemented, 5 TCs implemented. */
-    env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
-                             (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
+    env->mvp.CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
+                            (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
 // TODO: actually do 2 VPEs.
 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
 //                             (0x04 << CP0MVPC0_PTC);
-                             (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
-                             (0x00 << CP0MVPC0_PTC);
+                            (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
+                            (0x00 << CP0MVPC0_PTC);
 #if !defined(CONFIG_USER_ONLY)
     /* Usermode has no TLB support */
-    env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+    env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
 #endif
 
     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
        no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
-    env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
+    env->mvp.CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
                              (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
                              (0x1 << CP0MVPC1_PCP1);
 }

index cf6ac69..cb72d0d 100644
@@ -35,7 +35,7 @@ uint32_t cpu_mips_get_random (CPUState *env)
     /* Don't return same value twice, so get another value */
     do {
         lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
-        idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+        idx = lfsr % (env->tlb.nb_tlb - env->CP0_Wired) + env->CP0_Wired;
     } while (idx == prev_idx);
     prev_idx = idx;
     return idx;

index e11865b..7ca751b 100644
@@ -475,7 +475,7 @@ struct CPUMIPSState {
 
     CPUMIPSMVPContext mvp;
 #if !defined(CONFIG_USER_ONLY)
-    CPUMIPSTLBContext *tlb;
+    CPUMIPSTLBContext tlb;
 #endif
 
     const mips_def_t *cpu_model;

index 1c58e0c..32209e3 100644
@@ -69,8 +69,8 @@ int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
     uint8_t ASID = env->CP0_EntryHi & 0xFF;
     int i;
 
-    for (i = 0; i < env->tlb->tlb_in_use; i++) {
-        r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
+    for (i = 0; i < env->tlb.tlb_in_use; i++) {
+        r4k_tlb_t *tlb = &env->tlb.mmu.r4k.tlb[i];
         /* 1k pages are not supported. */
         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
         target_ulong tag = address & ~mask;

@@ -124,13 +124,15 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
             *physical = address & 0xFFFFFFFF;
             *prot = PAGE_READ | PAGE_WRITE;
         } else {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         }
 #if defined(TARGET_MIPS64)
     } else if (address < 0x4000000000000000ULL) {
         /* xuseg */
         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -138,7 +140,8 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
         /* xsseg */
         if ((supervisor_mode || kernel_mode) &&
             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -155,7 +158,8 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
         /* xkseg */
         if (kernel_mode && KX &&
             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -179,7 +183,8 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
     } else if (address < (int32_t)0xE0000000UL) {
         /* sseg (kseg2) */
         if (supervisor_mode || kernel_mode) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -187,7 +192,8 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
         /* kseg3 */
         /* XXX: debug segment is not emulated */
         if (kernel_mode) {
-            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+            ret = env->tlb.map_address(env, physical, prot, address, rw,
+                                       access_type);
         } else {
             ret = TLBRET_BADADDR;
         }

@@ -645,19 +651,19 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
     uint8_t ASID = env->CP0_EntryHi & 0xFF;
     target_ulong mask;
 
-    tlb = &env->tlb->mmu.r4k.tlb[idx];
+    tlb = &env->tlb.mmu.r4k.tlb[idx];
     /* The qemu TLB is flushed when the ASID changes, so no need to
        flush these entries again.  */
     if (tlb->G == 0 && tlb->ASID != ASID) {
         return;
     }
 
-    if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
+    if (use_extra && env->tlb.tlb_in_use < MIPS_TLB_MAX) {
         /* For tlbwr, we can shadow the discarded entry into
            a new (fake) TLB entry, as long as the guest can not
            tell that it's there.  */
-        env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
-        env->tlb->tlb_in_use++;
+        env->tlb.mmu.r4k.tlb[env->tlb.tlb_in_use] = *tlb;
+        env->tlb.tlb_in_use++;
         return;
     }
 

79 lines not on this page · raw message

index a5d095c..85efac1 100644
@@ -1155,7 +1155,7 @@ target_ulong helper_dmfc0_watchlo (uint32_t sel)
 void helper_mtc0_index (target_ulong arg1)
 {
     int num = 1;
-    unsigned int tmp = env->tlb->nb_tlb;
+    unsigned int tmp = env->tlb.nb_tlb;
 
     do {
         tmp >>= 1;

@@ -1486,7 +1486,7 @@ void helper_mtc0_pagegrain (target_ulong arg1)
 
 void helper_mtc0_wired (target_ulong arg1)
 {
-    env->CP0_Wired = arg1 % env->tlb->nb_tlb;
+    env->CP0_Wired = arg1 % env->tlb.nb_tlb;
 }
 
 void helper_mtc0_srsconf0 (target_ulong arg1)

@@ -1989,14 +1989,14 @@ static void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 {
     /* Flush qemu's TLB and discard all shadowed entries.  */
     tlb_flush (env, flush_global);
-    env->tlb->tlb_in_use = env->tlb->nb_tlb;
+    env->tlb.tlb_in_use = env->tlb.nb_tlb;
 }
 
 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
 {
     /* Discard entries from env->tlb[first] onwards.  */
-    while (env->tlb->tlb_in_use > first) {
-        r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
+    while (env->tlb.tlb_in_use > first) {
+        r4k_invalidate_tlb(env, --env->tlb.tlb_in_use, 0);
     }
 }
 

@@ -2005,7 +2005,7 @@ static void r4k_fill_tlb (int idx)
     r4k_tlb_t *tlb;
 
     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
-    tlb = &env->tlb->mmu.r4k.tlb[idx];
+    tlb = &env->tlb.mmu.r4k.tlb[idx];
     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
 #if defined(TARGET_MIPS64)
     tlb->VPN &= env->SEGMask;

@@ -2027,12 +2027,12 @@ void r4k_helper_tlbwi (void)
 {
     int idx;
 
-    idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
+    idx = (env->CP0_Index & ~0x80000000) % env->tlb.nb_tlb;
 
     /* Discard cached TLB entries.  We could avoid doing this if the
        tlbwi is just upgrading access permissions on the current entry;
        that might be a further win.  */
-    r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
+    r4k_mips_tlb_flush_extra(env, env->tlb.nb_tlb);
 
     r4k_invalidate_tlb(env, idx, 0);
     r4k_fill_tlb(idx);

@@ -2056,8 +2056,8 @@ void r4k_helper_tlbp (void)
     int i;
 
     ASID = env->CP0_EntryHi & 0xFF;
-    for (i = 0; i < env->tlb->nb_tlb; i++) {
-        tlb = &env->tlb->mmu.r4k.tlb[i];
+    for (i = 0; i < env->tlb.nb_tlb; i++) {
+        tlb = &env->tlb.mmu.r4k.tlb[i];
         /* 1k pages are not supported. */
         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
         tag = env->CP0_EntryHi & ~mask;

@@ -2069,10 +2069,10 @@ void r4k_helper_tlbp (void)
             break;
         }
     }
-    if (i == env->tlb->nb_tlb) {
+    if (i == env->tlb.nb_tlb) {
         /* No match.  Discard any shadow entries, if any of them match.  */
-        for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
-            tlb = &env->tlb->mmu.r4k.tlb[i];
+        for (i = env->tlb.nb_tlb; i < env->tlb.tlb_in_use; i++) {
+            tlb = &env->tlb.mmu.r4k.tlb[i];
             /* 1k pages are not supported. */
             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
             tag = env->CP0_EntryHi & ~mask;

@@ -2095,14 +2095,14 @@ void r4k_helper_tlbr (void)
     int idx;
 
     ASID = env->CP0_EntryHi & 0xFF;
-    idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
-    tlb = &env->tlb->mmu.r4k.tlb[idx];
+    idx = (env->CP0_Index & ~0x80000000) % env->tlb.nb_tlb;
+    tlb = &env->tlb.mmu.r4k.tlb[idx];
 
     /* If this will change the current ASID, flush qemu's TLB.  */
     if (ASID != tlb->ASID)
         cpu_mips_tlb_flush (env, 1);
 
-    r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
+    r4k_mips_tlb_flush_extra(env, env->tlb.nb_tlb);
 
     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
     env->CP0_PageMask = tlb->PageMask;

@@ -2114,22 +2114,22 @@ void r4k_helper_tlbr (void)
 
 void helper_tlbwi(void)
 {
-    env->tlb->helper_tlbwi();
+    env->tlb.helper_tlbwi();
 }
 
 void helper_tlbwr(void)
 {
-    env->tlb->helper_tlbwr();
+    env->tlb.helper_tlbwr();
 }
 
 void helper_tlbp(void)
 {
-    env->tlb->helper_tlbp();
+    env->tlb.helper_tlbp();
 }
 
 void helper_tlbr(void)
 {
-    env->tlb->helper_tlbr();
+    env->tlb.helper_tlbr();
 }
 
 /* Specials */

index c655a34..48a0108 100644
@@ -5999,26 +5999,30 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
         break;
     case OPC_TLBWI:
         opn = "tlbwi";
-        if (!env->tlb->helper_tlbwi)
+        if (!env->tlb.helper_tlbwi) {
             goto die;
+        }
         gen_helper_tlbwi();
         break;
     case OPC_TLBWR:
         opn = "tlbwr";
-        if (!env->tlb->helper_tlbwr)
+        if (!env->tlb.helper_tlbwr) {
             goto die;
+        }
         gen_helper_tlbwr();
         break;
     case OPC_TLBP:
         opn = "tlbp";
-        if (!env->tlb->helper_tlbp)
+        if (!env->tlb.helper_tlbp) {
             goto die;
+        }
         gen_helper_tlbp();
         break;
     case OPC_TLBR:
         opn = "tlbr";
-        if (!env->tlb->helper_tlbr)
+        if (!env->tlb.helper_tlbr) {
             goto die;
+        }
         gen_helper_tlbr();
         break;
     case OPC_ERET:

@@ -12792,8 +12796,8 @@ void cpu_reset (CPUMIPSState *env)
         env->CP0_ErrorEPC = env->active_tc.PC;
     }
     env->active_tc.PC = (int32_t)0xBFC00000;
-    env->CP0_Random = env->tlb->nb_tlb - 1;
-    env->tlb->tlb_in_use = env->tlb->nb_tlb;
+    env->CP0_Random = env->tlb.nb_tlb - 1;
+    env->tlb.tlb_in_use = env->tlb.nb_tlb;
     env->CP0_Wired = 0;
     env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);

index 54fd1eb..0adb304 100644
@@ -513,30 +513,28 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
 #ifndef CONFIG_USER_ONLY
 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb->nb_tlb = 1;
-    env->tlb->map_address = &no_mmu_map_address;
+    env->tlb.nb_tlb = 1;
+    env->tlb.map_address = &no_mmu_map_address;
 }
 
 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb->nb_tlb = 1;
-    env->tlb->map_address = &fixed_mmu_map_address;
+    env->tlb.nb_tlb = 1;
+    env->tlb.map_address = &fixed_mmu_map_address;
 }
 
 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
-    env->tlb->map_address = &r4k_map_address;
-    env->tlb->helper_tlbwi = r4k_helper_tlbwi;
-    env->tlb->helper_tlbwr = r4k_helper_tlbwr;
-    env->tlb->helper_tlbp = r4k_helper_tlbp;
-    env->tlb->helper_tlbr = r4k_helper_tlbr;
+    env->tlb.nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+    env->tlb.map_address = &r4k_map_address;
+    env->tlb.helper_tlbwi = r4k_helper_tlbwi;
+    env->tlb.helper_tlbwr = r4k_helper_tlbwr;
+    env->tlb.helper_tlbp = r4k_helper_tlbp;
+    env->tlb.helper_tlbr = r4k_helper_tlbr;
 }
 
 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
     switch (def->mmu_type) {
         case MMU_TYPE_NONE:
             no_mmu_init(env, def);

@@ -581,7 +579,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
                             (0x00 << CP0MVPC0_PTC);
 #if !defined(CONFIG_USER_ONLY)
     /* Usermode has no TLB support */
-    env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+    env->mvp.CP0_MVPConf0 |= (env->tlb.nb_tlb << CP0MVPC0_PTLBE);
 #endif
 
     /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,

index 7ca751b..7810924 100644
@@ -507,7 +507,7 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 #define cpu_signal_handler cpu_mips_signal_handler
 #define cpu_list mips_cpu_list
 
-#define CPU_SAVE_VERSION 3
+#define CPU_SAVE_VERSION 4
 
 /* MMU modes definitions. We carefully match the indices with our
    hflags layout. */

index a55fbb6..134dbd5 100644
@@ -84,8 +84,7 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_sbe32s(f, &env->error_code);
     qemu_put_be32s(f, &env->hflags);
     qemu_put_betls(f, &env->btarget);
-    i = env->bcond;
-    qemu_put_sbe32s(f, &i);
+    qemu_put_betls(f, &env->bcond);
 
     /* Save remaining CP1 registers */
     qemu_put_sbe32s(f, &env->CP0_Index);

@@ -193,9 +192,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     CPUState *env = opaque;
     int i;
 
-    if (version_id != 3)
+    if (version_id != 4) {
         return -EINVAL;
-
+    }
     /* Load active TC */
     load_tc(f, &env->active_tc);
 

@@ -236,8 +235,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     qemu_get_sbe32s(f, &env->error_code);
     qemu_get_be32s(f, &env->hflags);
     qemu_get_betls(f, &env->btarget);
-    qemu_get_sbe32s(f, &i);
-    env->bcond = i;
+    qemu_get_betls(f, &env->bcond);
 
     /* Load remaining CP1 registers */
     qemu_get_sbe32s(f, &env->CP0_Index);

index 7810924..9bb7379 100644
@@ -37,6 +37,8 @@ struct r4k_tlb_t {
     uint_fast16_t D0:1;
     uint_fast16_t D1:1;
     target_ulong PFN[2];
+    uint8_t asid_vmstate;
+    uint16_t flags_vmstate;
 };
 
 #if !defined(CONFIG_USER_ONLY)

@@ -507,8 +509,6 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 #define cpu_signal_handler cpu_mips_signal_handler
 #define cpu_list mips_cpu_list
 
-#define CPU_SAVE_VERSION 4
-
 /* MMU modes definitions. We carefully match the indices with our
    hflags layout. */
 #define MMU_MODE0_SUFFIX _kernel

487 lines not on this page · raw message

index 6ab780d..f6d9436 100644
@@ -446,7 +446,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 #define cpu_signal_handler cpu_arm_signal_handler
 #define cpu_list arm_cpu_list
 
-#define CPU_SAVE_VERSION 4
+#define CPU_SAVE_VERSION 5
 
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel

index 7d4fc54..3a3b325 100644
@@ -60,7 +60,7 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_be32(f, env->features);
 
     if (arm_feature(env, ARM_FEATURE_VFP)) {
-        for (i = 0;  i < 16; i++) {
+        for (i = 0;  i < 32; i++) {
             CPU_DoubleU u;
             u.d = env->vfp.regs[i];
             qemu_put_be32(f, u.l.upper);

@@ -73,15 +73,6 @@ void cpu_save(QEMUFile *f, void *opaque)
         /* TODO: Should use proper FPSCR access functions.  */
         qemu_put_be32(f, env->vfp.vec_len);
         qemu_put_be32(f, env->vfp.vec_stride);
-
-        if (arm_feature(env, ARM_FEATURE_VFP3)) {
-            for (i = 16;  i < 32; i++) {
-                CPU_DoubleU u;
-                u.d = env->vfp.regs[i];
-                qemu_put_be32(f, u.l.upper);
-                qemu_put_be32(f, u.l.lower);
-            }
-        }
     }
 
     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {

@@ -174,7 +165,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     env->features = qemu_get_be32(f);
 
     if (arm_feature(env, ARM_FEATURE_VFP)) {
-        for (i = 0;  i < 16; i++) {
+        for (i = 0;  i < 32; i++) {
             CPU_DoubleU u;
             u.l.upper = qemu_get_be32(f);
             u.l.lower = qemu_get_be32(f);

@@ -187,15 +178,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
         /* TODO: Should use proper FPSCR access functions.  */
         env->vfp.vec_len = qemu_get_be32(f);
         env->vfp.vec_stride = qemu_get_be32(f);
-
-        if (arm_feature(env, ARM_FEATURE_VFP3)) {
-            for (i = 0;  i < 16; i++) {
-                CPU_DoubleU u;
-                u.l.upper = qemu_get_be32(f);
-                u.l.lower = qemu_get_be32(f);
-                env->vfp.regs[i] = u.d;
-            }
-        }
     }
 
     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {

index f6d9436..ec02f85 100644
@@ -228,6 +228,8 @@ typedef struct CPUARMState {
     } cp[15];
     void *nvic;
     const struct arm_boot_info *boot_info;
+
+    uint32_t cpsr_vmstate;
 } CPUARMState;
 
 CPUARMState *cpu_arm_init(const char *cpu_model);

@@ -446,8 +448,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 #define cpu_signal_handler cpu_arm_signal_handler
 #define cpu_list arm_cpu_list
 
-#define CPU_SAVE_VERSION 5
-
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
 #define MMU_MODE1_SUFFIX _user

356 lines not on this page · raw message

index 09f3f01..cc84378 100644
@@ -660,13 +660,8 @@ void cpu_exec_init(CPUState *env)
 #endif
 #if !defined(CONFIG_USER_ONLY)
     vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
-#if defined(CPU_SAVE_VERSION)
-    register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
-                    cpu_save, cpu_load, env);
-#else
     vmstate_register(NULL, cpu_index, &vmstate_cpu, env);
 #endif
-#endif
 }
 
 /* Allocate a new translation block. Flush the translation buffer if

index 1c15cb1..fd0fc30 100644
@@ -246,10 +246,6 @@ bool tcg_enabled(void);
 
 void cpu_exec_init_all(void);
 
-/* CPU save/load.  */
-void cpu_save(QEMUFile *f, void *opaque);
-int cpu_load(QEMUFile *f, void *opaque, int version_id);
-
 /* Unblock cpu */
 void qemu_cpu_kick(void *env);
 void qemu_cpu_kick_self(void);