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drm/i915: interlaced mode support

PATCH In review Peter Ross 6 participants 14 messages Jan 18, 2012 – Jan 22, 2012

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DRM drivers Intel i915
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Peter Ross

author
#0 lore raw

v2 cover drm/i915: interlaced mode support

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220

It has been tested on the following hardware:
* ASUS P5E-VM-HDMI (G35_G) and LG 32FS4D (VGA and SDVO connectors)
* Intel DQ45CB (Q45_G) and Sony GDM 5411 (VGA connector)
* Toshiba Portege R500 (I935_GM) and Sony GDM 5411 CRT (VGA connector)

PATCH HISTORY
Version 1. Initial cut.
Version 2. Set timings for gen3 and ILK/SB chipsets.
Allow interlaced output on HDMI connector.

Peter Ross (3):
drm/i915: specify vertical timings in frame units for interlaced

    modes (gen3+)

drm/i915: allow interlaced mode output on the SDVO connector drm/i915: allow interlaced mode output on the HDMI connector

 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c    |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c    |    2 +-
 3 files changed, 16 insertions(+), 2 deletions(-)
Signature · 4 lines
1.7.5.4

-- Peter
(A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)

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author
#1 lore raw

PATCH v2 1/3 drm/i915: specify vertical timings in frame units for interlaced modes (gen3+)

The I945, I965, IronLake and SandyBridge chipsets expect vertical timings in frame units, whereas the DRM subsystem uses field units internally for interlaced modes.

Signed-off-by Peter Ross <[email protected]>
---
 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)
drivers/gpu/drm/i915/intel_display.c +14 -0
index 2a3f707..992f481 100644
@@ -5316,6 +5316,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		adjusted_mode->crtc_vblank_end -= 1;
 		adjusted_mode->crtc_vsync_end -= 1;
 		adjusted_mode->crtc_vsync_start -= 1;
+		if (INTEL_INFO(dev)->gen >= 3) {
+			adjusted_mode->crtc_vdisplay *= 2;
+			adjusted_mode->crtc_vtotal *= 2;
+			adjusted_mode->crtc_vblank_start *= 2;
+			adjusted_mode->crtc_vblank_end *= 2;
+			adjusted_mode->crtc_vsync_end *= 2;
+			adjusted_mode->crtc_vsync_start *= 2;
+		}
 	} else
 		pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
 

@@ -5908,6 +5916,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		adjusted_mode->crtc_vblank_end -= 1;
 		adjusted_mode->crtc_vsync_end -= 1;
 		adjusted_mode->crtc_vsync_start -= 1;
+		adjusted_mode->crtc_vdisplay *= 2;
+		adjusted_mode->crtc_vtotal *= 2;
+		adjusted_mode->crtc_vblank_start *= 2;
+		adjusted_mode->crtc_vblank_end *= 2;
+		adjusted_mode->crtc_vsync_end *= 2;
+		adjusted_mode->crtc_vsync_start *= 2;
 	} else
 		pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
Signature · 4 lines
1.7.5.4

-- Peter
(A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)

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author
#2 lore raw

PATCH v2 2/3 drm/i915: allow interlaced mode output on the SDVO connector

In reply to Peter Ross
Signed-off-by Peter Ross <[email protected]>
---
 drivers/gpu/drm/i915/intel_sdvo.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/gpu/drm/i915/intel_sdvo.c +1 -1
index f7b9268..03a84f8 100644
@@ -1987,7 +1987,7 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
 	drm_connector_helper_add(&connector->base.base,
 				 &intel_sdvo_connector_helper_funcs);
 
-	connector->base.base.interlace_allowed = 0;
+	connector->base.base.interlace_allowed = 1;
 	connector->base.base.doublescan_allowed = 0;
 	connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
Signature · 4 lines
1.7.5.4

-- Peter
(A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)

_______________________________________________
Intel-gfx mailing list
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author
#3 lore raw

PATCH v2 3/3 drm/i915: allow interlaced mode output on the HDMI connector

In reply to Peter Ross
Signed-off-by Peter Ross <[email protected]>
---
 drivers/gpu/drm/i915/intel_hdmi.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/gpu/drm/i915/intel_hdmi.c +1 -1
index e799e85..c243141 100644
@@ -513,7 +513,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 	intel_encoder->type = INTEL_OUTPUT_HDMI;
 
 	connector->polled = DRM_CONNECTOR_POLL_HPD;
-	connector->interlace_allowed = 0;
+	connector->interlace_allowed = 1;
 	connector->doublescan_allowed = 0;
 	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Signature · 4 lines
1.7.5.4

-- Peter
(A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)

_______________________________________________
Intel-gfx mailing list
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Reviewed-by on the v2 series
#4 lore raw
In reply to Peter Ross
Quoted 17 lines · On Thu, 19 Jan 2012 00:29:23 +1100 Peter Ross <[email protected]> wrote:

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220

It has been tested on the following hardware:
* ASUS P5E-VM-HDMI (G35_G) and LG 32FS4D (VGA and SDVO connectors)
* Intel DQ45CB (Q45_G) and Sony GDM 5411 (VGA connector)
* Toshiba Portege R500 (I935_GM) and Sony GDM 5411 CRT (VGA connector)

PATCH HISTORY
Version 1. Initial cut.
Version 2. Set timings for gen3 and ILK/SB chipsets.
Allow interlaced output on HDMI connector.

Peter Ross (3):
drm/i915: specify vertical timings in frame units for interlaced

Quoted 8 lines
    modes (gen3+)

drm/i915: allow interlaced mode output on the SDVO connector drm/i915: allow interlaced mode output on the HDMI connector

 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c    |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c    |    2 +-
 3 files changed, 16 insertions(+), 2 deletions(-)

Cool, this series looks good.

Reviewed-by Jesse Barnes <[email protected]>

Yi, can you give these patches a try with interlaced modes on SDVO and HDMI attached displays and reply with your tested-by?

Thanks,

Signature · 1 line
Jesse Barnes, Intel Open Source Technology Center

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Tested-by
#5 lore raw
Quoted 26 lines
Quoted 17 lines

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220

It has been tested on the following hardware:
* ASUS P5E-VM-HDMI (G35_G) and LG 32FS4D (VGA and SDVO connectors)
* Intel DQ45CB (Q45_G) and Sony GDM 5411 (VGA connector)
* Toshiba Portege R500 (I935_GM) and Sony GDM 5411 CRT (VGA connector)

PATCH HISTORY
Version 1. Initial cut.
Version 2. Set timings for gen3 and ILK/SB chipsets.
Allow interlaced output on HDMI connector.

Peter Ross (3):
drm/i915: specify vertical timings in frame units for interlaced

Quoted 8 lines
    modes (gen3+)

drm/i915: allow interlaced mode output on the SDVO connector drm/i915: allow interlaced mode output on the HDMI connector

 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c    |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c    |    2 +-
 3 files changed, 16 insertions(+), 2 deletions(-)
Quoted 7 lines

Cool, this series looks good.

Reviewed-by Jesse Barnes <[email protected]>

Yi, can you give these patches a try with interlaced modes on SDVO and HDMI attached displays and reply with your tested-by?

I tried the 3 patches on 3 machines, gm45(HDMI), g45(SDVO-HDMI) and a SandyBridge mobile(HDMI). The patches work well on gm45 with HDMI and g45 with SDVO-HDMI card. I could reproduce the issue and fix it.

But on the SandyBridge, it seems that the issue still exists.

Tested-by Sun Yi <[email protected]>

Yi
--Thanks

Quoted 3 lines

Thanks,
--
Jesse Barnes, Intel Open Source Technology Center

#6 lore raw
Quoted 34 lines · Yi
Quoted 26 lines
Quoted 17 lines

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220

It has been tested on the following hardware:
* ASUS P5E-VM-HDMI (G35_G) and LG 32FS4D (VGA and SDVO connectors)
* Intel DQ45CB (Q45_G) and Sony GDM 5411 (VGA connector)
* Toshiba Portege R500 (I935_GM) and Sony GDM 5411 CRT (VGA connector)

PATCH HISTORY
Version 1. Initial cut.
Version 2. Set timings for gen3 and ILK/SB chipsets.
Allow interlaced output on HDMI connector.

Peter Ross (3):
drm/i915: specify vertical timings in frame units for interlaced

Quoted 8 lines
    modes (gen3+)

drm/i915: allow interlaced mode output on the SDVO connector drm/i915: allow interlaced mode output on the HDMI connector

 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c    |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c    |    2 +-
 3 files changed, 16 insertions(+), 2 deletions(-)
Quoted 7 lines

Cool, this series looks good.

Reviewed-by Jesse Barnes <[email protected]>

Yi, can you give these patches a try with interlaced modes on SDVO and HDMI attached displays and reply with your tested-by?

Quoted 6 lines

I tried the 3 patches on 3 machines, gm45(HDMI), g45(SDVO-HDMI) and a SandyBridge mobile(HDMI). The patches work well on gm45 with HDMI and g45 with SDVO-HDMI card. I could reproduce the issue and fix it.

But on the SandyBridge, it seems that the issue still exists.

Tested-by Sun Yi <[email protected]>

So I guess it works on pre-PCH_SPLIT machines, but not on later ones. Peter, on which machines have you tried this out?
-Daniel

Signature · 3 lines
Daniel Vetter
Mail: [email protected]
Mobile: +41 (0)79 365 57 48
Reviewed-by on the v2 series
#7 lore raw
In reply to Peter Ross
Quoted 21 lines · Peter Ross

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220

It has been tested on the following hardware:
* ASUS P5E-VM-HDMI (G35_G) and LG 32FS4D (VGA and SDVO connectors)
* Intel DQ45CB (Q45_G) and Sony GDM 5411 (VGA connector)
* Toshiba Portege R500 (I935_GM) and Sony GDM 5411 CRT (VGA connector)

PATCH HISTORY
Version 1. Initial cut.
Version 2. Set timings for gen3 and ILK/SB chipsets.
Allow interlaced output on HDMI connector.

Peter Ross (3):
drm/i915: specify vertical timings in frame units for interlaced
modes (gen3+)
drm/i915: allow interlaced mode output on the SDVO connector drm/i915: allow interlaced mode output on the HDMI connector

Quoted 5 lines
 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c    |    2 +-
 drivers/gpu/drm/i915/intel_sdvo.c    |    2 +-
 3 files changed, 16 insertions(+), 2 deletions(-)

Everything looks correct to me, thanks for the testing!

Reviewed-by Eugeni Dodonov <[email protected]>
Signature · 2 lines
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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#8 lore raw
In reply to Peter Ross

Hi

2012/1/18 Peter Ross <[email protected]>:

Quoted 2 lines

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

I just tested that on HDMI.

The "interlace_allowed=1" patch seems fine: it made xrandr list more modes. But I believe patch 1 is still not correct. I tested that and instead of getting a 1920x1080 I got a 1920x1078 mode: vtotal, vblank and vsync were wrong. If you look at the patch, you'll see that the code has some "something -= 1" statements. I believe they could be wrong.

So I removed these lines and tested again... Now the mode is actually 1920x1080, but my monitor's OSD displays it as "1080p". So I also tested my TV and it reported "1080p@25hz" too.

I guess we're still missing something... I'll try to debug.

Thanks for the patches!
Paulo

Quoted 35 lines

History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220

It has been tested on the following hardware:
* ASUS P5E-VM-HDMI (G35_G) and LG 32FS4D (VGA and SDVO connectors)
* Intel DQ45CB (Q45_G) and Sony GDM 5411 (VGA connector)
* Toshiba Portege R500 (I935_GM) and Sony GDM 5411 CRT (VGA connector)

PATCH HISTORY
Version 1. Initial cut.
Version 2. Set timings for gen3 and ILK/SB chipsets. Allow interlaced output on HDMI connector.

Peter Ross (3):
 drm/i915: specify vertical timings in frame units for interlaced modes (gen3+)
 drm/i915: allow interlaced mode output on the SDVO connector drm/i915: allow interlaced mode output on the HDMI connector

 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++++++ drivers/gpu/drm/i915/intel_hdmi.c    |    2 +- drivers/gpu/drm/i915/intel_sdvo.c    |    2 +-

 3 files changed, 16 insertions(+), 2 deletions(-)

--
1.7.5.4

-- Peter
(A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)

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Intel-gfx mailing list
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Signature · 1 line
Paulo Zanoni
#9 lore raw
Quoted 15 lines · On Wed, 18 Jan 2012 18:39:40 -0200 Paulo Zanoni <[email protected]> wrote:

Hi

2012/1/18 Peter Ross <[email protected]>:

Quoted 2 lines

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

I just tested that on HDMI.

The "interlace_allowed=1" patch seems fine: it made xrandr list more modes. But I believe patch 1 is still not correct. I tested that and instead of getting a 1920x1080 I got a 1920x1078 mode: vtotal, vblank and vsync were wrong. If you look at the patch, you'll see that the code has some "something -= 1" statements. I believe they could be wrong.

Quoted 5 lines

So I removed these lines and tested again... Now the mode is actually 1920x1080, but my monitor's OSD displays it as "1080p". So I also tested my TV and it reported "1080p@25hz" too.

I guess we're still missing something... I'll try to debug.

Yeah for the interlaced case the -1 should be after the multiply, if it's there at all... would have to double check the docs.

Signature · 1 line
Jesse Barnes, Intel Open Source Technology Center

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author
#10 lore raw
Quoted 18 lines · Jesse Barnes
Quoted 15 lines · On Wed, 18 Jan 2012 18:39:40 -0200 Paulo Zanoni <[email protected]> wrote:

Hi

2012/1/18 Peter Ross <[email protected]>:

Quoted 2 lines

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

I just tested that on HDMI.

The "interlace_allowed=1" patch seems fine: it made xrandr list more modes. But I believe patch 1 is still not correct. I tested that and instead of getting a 1920x1080 I got a 1920x1078 mode: vtotal, vblank and vsync were wrong. If you look at the patch, you'll see that the code has some "something -= 1" statements. I believe they could be wrong.

Quoted 5 lines
Quoted 5 lines

So I removed these lines and tested again... Now the mode is actually 1920x1080, but my monitor's OSD displays it as "1080p". So I also tested my TV and it reported "1080p@25hz" too.

I guess we're still missing something... I'll try to debug.

Yep. I can confirm this problem too. With PATCH-v2, the output height is reduced by two lines. (I used a test bitmap to count the lines on CRT)

Quoted 2 lines

Yeah for the interlaced case the -1 should be after the multiply, if it's there at all... would have to double check the docs.

The docs do suggest the timings need to be subtracted by one line. Performing the -1 after the *2 fixes the problem, and this has been tested on gen 3 and 4 chipsets.

When the -1 is removed altogether, the output is the visually identical to when the -1 is present. I'm erring on the side of keeping the -1, since that makes the implementation consistent with the documentation.

-- Peter
(A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

author
#11 lore raw
Quoted 11 lines · Peter Ross
Quoted 10 lines · Jesse Barnes
Quoted 7 lines · On Wed, 18 Jan 2012 18:39:40 -0200 Paulo Zanoni <[email protected]> wrote:

Hi

2012/1/18 Peter Ross <[email protected]>:

Quoted 2 lines

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

I just tested that on HDMI.

Hey Paul, can you confirm which chipset you tested this on. I am keeping track of who has had successes and fails in the patch comments.

I can also confirm that the patch also works on I915_G and I945_GME chipsets using VGA out.

Quoted 19 lines
Quoted 7 lines
Quoted 7 lines

The "interlace_allowed=1" patch seems fine: it made xrandr list more modes. But I believe patch 1 is still not correct. I tested that and instead of getting a 1920x1080 I got a 1920x1078 mode: vtotal, vblank and vsync were wrong. If you look at the patch, you'll see that the code has some "something -= 1" statements. I believe they could be wrong.

Quoted 5 lines
Quoted 5 lines

So I removed these lines and tested again... Now the mode is actually 1920x1080, but my monitor's OSD displays it as "1080p". So I also tested my TV and it reported "1080p@25hz" too.

I guess we're still missing something... I'll try to debug.

Yep. I can confirm this problem too. With PATCH-v2, the output height is reduced by two lines. (I used a test bitmap to count the lines on CRT)

Quoted 2 lines

Yeah for the interlaced case the -1 should be after the multiply, if it's there at all... would have to double check the docs.

Quoted 7 lines

The docs do suggest the timings need to be subtracted by one line. Performing the -1 after the *2 fixes the problem, and this has been tested on gen 3 and 4 chipsets.

When the -1 is removed altogether, the output is the visually identical to when the -1 is present. I'm erring on the side of keeping the -1, since that makes the implementation consistent with the documentation.

Another data point: The Intel G35 Display Driver for Windows XP does *not* perform the -1. To determine this I dumped the G35 PCI memory region on windows, and fed the dump file into intel_reg_dumper.

Cheers,

-- Peter
(A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)

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Intel-gfx mailing list
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author
#12 lore raw
Quoted 11 lines · Peter Ross
Quoted 10 lines · Peter Ross
Quoted 9 lines · Jesse Barnes
Quoted 6 lines · On Wed, 18 Jan 2012 18:39:40 -0200 Paulo Zanoni <[email protected]> wrote:

Hi

2012/1/18 Peter Ross <[email protected]>:

Quoted 2 lines

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

[snip]

Quoted 10 lines
Quoted 10 lines

Yep. I can confirm this problem too. With PATCH-v2, the output height is reduced by two lines. (I used a test bitmap to count the lines on CRT)

Quoted 2 lines

Yeah for the interlaced case the -1 should be after the multiply, if it's there at all... would have to double check the docs.

The docs do suggest the timings need to be subtracted by one line. Performing the -1 after the *2 fixes the problem, and this has been tested on gen 3 and 4 chipsets.

Quoted 6 lines
Quoted 3 lines

When the -1 is removed altogether, the output is the visually identical to when the -1 is present. I'm erring on the side of keeping the -1, since that makes the implementation consistent with the documentation.

Another data point: The Intel G35 Display Driver for Windows XP does *not* perform the -1. To determine this I dumped the G35 PCI memory region on

Please disregard my comment about -1, turns out I was looking at the wrong pipe! In actuality, the Intel G35 Display Driver for Windows XP performs -2 on the VTOTAL and VBLANK_END registers.

For anyone interested in this topic, I have attached reg dumps for the modes supported by the Windows driver. The windows driver does not detect the CEA modes of my television, and instead provides a bunch of oddball modes, like 1184x666x60 (which works, but there is lots of underscan).

Cheers,

-- Peter
(A907 E02F A6E5 0CD2 34CD 20D2 6760 79C5 AC40 DD6B)

                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0c00000 (enabled, double-wide)
            PIPEASRC: 0x077f0437 (1920, 1080)
           PIPEASTAT: 0x00000237 (status: VSYNC_INT_STATUS OFIELD_INT_STATUS EFIELD_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02004000
    CURSOR_A_CONTROL: 0x04000005
   CURSOR_A_POSITION: 0x021202f2
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x0897077f (1920 active, 2200 total)
            HBLANK_A: 0x0897077f (1920 start, 2200 end)
             HSYNC_A: 0x080307d7 (2008 start, 2052 end)
            VTOTAL_A: 0x04630437 (1080 active, 1124 total)
            VBLANK_A: 0x04630437 (1080 start, 1124 end)
             VSYNC_A: 0x0445043b (1084 start, 1094 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x000000fd (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x000000fd (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0c00000 (enabled, double-wide)
            PIPEASRC: 0x077f0437 (1920, 1080)
           PIPEASTAT: 0x00000237 (status: VSYNC_INT_STATUS OFIELD_INT_STATUS EFIELD_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02004000
    CURSOR_A_CONTROL: 0x04000005
   CURSOR_A_POSITION: 0x00a7013a
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x0a4f077f (1920 active, 2640 total)
            HBLANK_A: 0x0a4f077f (1920 start, 2640 end)
             HSYNC_A: 0x09bb098f (2448 start, 2492 end)
            VTOTAL_A: 0x04630437 (1080 active, 1124 total)
            VBLANK_A: 0x04630437 (1080 start, 1124 end)
             VSYNC_A: 0x0445043b (1084 start, 1094 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x000000fd (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x000000fd (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0c00000 (enabled, double-wide)
            PIPEASRC: 0x06ef03e7 (1776, 1000)
           PIPEASTAT: 0x00000237 (status: VSYNC_INT_STATUS OFIELD_INT_STATUS EFIELD_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02004000
    CURSOR_A_CONTROL: 0x04000005
   CURSOR_A_POSITION: 0x01e30324
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x089706ef (1776 active, 2200 total)
            HBLANK_A: 0x084f0737 (1848 start, 2128 end)
             HSYNC_A: 0x07bb078f (1936 start, 1980 end)
            VTOTAL_A: 0x046303e7 (1000 active, 1124 total)
            VBLANK_A: 0x043b040f (1040 start, 1084 end)
             VSYNC_A: 0x041d0413 (1044 start, 1054 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x000000fd (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x000000fd (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0c00000 (enabled, double-wide)
            PIPEASRC: 0x06ef03e7 (1776, 1000)
           PIPEASTAT: 0x00000237 (status: VSYNC_INT_STATUS OFIELD_INT_STATUS EFIELD_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02004000
    CURSOR_A_CONTROL: 0x04000005
   CURSOR_A_POSITION: 0x005c014c
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x0a4f06ef (1776 active, 2640 total)
            HBLANK_A: 0x0a070737 (1848 start, 2568 end)
             HSYNC_A: 0x09730947 (2376 start, 2420 end)
            VTOTAL_A: 0x046303e7 (1000 active, 1124 total)
            VBLANK_A: 0x043b040f (1040 start, 1084 end)
             VSYNC_A: 0x041d0413 (1044 start, 1054 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x000000fd (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x000000fd (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0c00000 (enabled, double-wide)
            PIPEASRC: 0x04ff03ff (1280, 1024)
           PIPEASTAT: 0x00000237 (status: VSYNC_INT_STATUS OFIELD_INT_STATUS EFIELD_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02004000
    CURSOR_A_CONTROL: 0x04000005
   CURSOR_A_POSITION: 0x0091024c
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x089704ff (1280 active, 2200 total)
            HBLANK_A: 0x0757063f (1600 start, 1880 end)
             HSYNC_A: 0x06c30697 (1688 start, 1732 end)
            VTOTAL_A: 0x046303ff (1024 active, 1124 total)
            VBLANK_A: 0x0447041b (1052 start, 1096 end)
             VSYNC_A: 0x0429041f (1056 start, 1066 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x000000fd (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x000000fd (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0000000 (enabled, double-wide)
            PIPEASRC: 0x04ff02cf (1280, 720)
           PIPEASTAT: 0x00000207 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02004000
    CURSOR_A_CONTROL: 0x04000005
   CURSOR_A_POSITION: 0x00d101c3
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x067104ff (1280 active, 1650 total)
            HBLANK_A: 0x067104ff (1280 start, 1650 end)
             HSYNC_A: 0x0595056d (1390 start, 1430 end)
            VTOTAL_A: 0x02ed02cf (720 active, 750 total)
            VBLANK_A: 0x02ed02cf (720 start, 750 end)
             VSYNC_A: 0x02d902d4 (725 start, 730 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x000000fd (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x000000fd (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0000000 (enabled, double-wide)
            PIPEASRC: 0x04ff02cf (1280, 720)
           PIPEASTAT: 0x00000207 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02004000
    CURSOR_A_CONTROL: 0x04000005
   CURSOR_A_POSITION: 0x01c1035d
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x07bb04ff (1280 active, 1980 total)
            HBLANK_A: 0x07bb04ff (1280 start, 1980 end)
             HSYNC_A: 0x06df06b7 (1720 start, 1760 end)
            VTOTAL_A: 0x02ed02cf (720 active, 750 total)
            VBLANK_A: 0x02ed02cf (720 start, 750 end)
             VSYNC_A: 0x02d902d4 (725 start, 730 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000044
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x000000fd (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x000000fd (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00002000 (8192 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0000000 (enabled, double-wide)
            PIPEASRC: 0x049f0299 (1184, 666)
           PIPEASTAT: 0x00000207 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02004000
    CURSOR_A_CONTROL: 0x04000005
   CURSOR_A_POSITION: 0x004901e4
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x0671049f (1184 active, 1650 total)
            HBLANK_A: 0x064104cf (1232 start, 1602 end)
             HSYNC_A: 0x0565053d (1342 start, 1382 end)
            VTOTAL_A: 0x02ed0299 (666 active, 750 total)
            VBLANK_A: 0x02d202b4 (693 start, 723 end)
             VSYNC_A: 0x02be02b9 (698 start, 703 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000044
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x000000fd (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x000000fd (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000
pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
                 DCC: 0x00100008 (��|)
           CHDECMISC: 0x0000002c (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep not present)
              C0DRB0: 0x00100008 (0x0008)
              C0DRB1: 0x00100010 (0x0010)
              C0DRB2: 0x00100010 (0x0010)
              C0DRB3: 0x02020010 (0x0010)
              C1DRB0: 0x00100008 (0x0008)
              C1DRB1: 0x00100010 (0x0010)
              C1DRB2: 0x00100010 (0x0010)
              C1DRB3: 0x02020010 (0x0010)
             C0DRA01: 0x00000202 (0x0202)
             C0DRA23: 0x00000000 (0x0000)
             C1DRA01: 0x00000202 (0x0202)
             C1DRA23: 0x00000000 (0x0000)
          PGETBL_CTL: 0x7ff80001
   VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
   VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
       VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
           DPLL_TEST: 0x00010001 ()
        CACHE_MODE_0: 0x00006800
             D_STATE: 0x00000000
       DSPCLK_GATE_D: 0x00040000 (clock gates disabled: DSSUNIT)
      RENCLK_GATE_D1: 0x70800000
      RENCLK_GATE_D2: 0x00000000
               SDVOB: 0x8000009c (enabled, pipe A, stall disabled, detected)
               SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
             SDVOUDI: 0x00000000
              DSPARB: 0x00001d9c
              DSPFW1: 0x1f8f0f0f
              DSPFW2: 0x00000f0f
              DSPFW3: 0x00000000
                ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
                LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
                DVOB: 0x8000009c (enabled, pipe A, no stall, +hsync, +vsync)
                DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
         DVOA_SRCDIM: 0x00000000
         DVOB_SRCDIM: 0x00000000
         DVOC_SRCDIM: 0x00000000
          PP_CONTROL: 0x00000000 (power target: off)
           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
        PP_ON_DELAYS: 0x00000000
       PP_OFF_DELAYS: 0x00000000
          PP_DIVISOR: 0x00000000
        PFIT_CONTROL: 0x00000000
     PFIT_PGM_RATIOS: 0x10001000
     PORT_HOTPLUG_EN: 0x04000220
   PORT_HOTPLUG_STAT: 0x00000000
            DSPACNTR: 0xd8000400 (enabled, pipe A)
          DSPASTRIDE: 0x00001000 (4096 bytes)
             DSPAPOS: 0x00000000 (0, 0)
            DSPASIZE: 0x00000000 (1, 1)
            DSPABASE: 0x00000000
            DSPASURF: 0x00000000
         DSPATILEOFF: 0x00000000
           PIPEACONF: 0xc0c00000 (enabled, double-wide)
            PIPEASRC: 0x03ff02ff (1024, 768)
           PIPEASTAT: 0x00000237 (status: VSYNC_INT_STATUS OFIELD_INT_STATUS EFIELD_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
   PIPEA_GMCH_DATA_M: 0x00000000
   PIPEA_GMCH_DATA_N: 0x00000000
     PIPEA_DP_LINK_M: 0x00000000
     PIPEA_DP_LINK_N: 0x00000000
       CURSOR_A_BASE: 0x02000000
    CURSOR_A_CONTROL: 0x00000000
   CURSOR_A_POSITION: 0x00dd0187
                FPA0: 0x00010f06 (n = 1, m1 = 15, m2 = 6)
                FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_A: 0xd4020c00 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
           DPLL_A_MD: 0x00000103
            HTOTAL_A: 0x089703ff (1024 active, 2200 total)
            HBLANK_A: 0x06d705bf (1472 start, 1752 end)
             HSYNC_A: 0x06430617 (1560 start, 1604 end)
            VTOTAL_A: 0x046302ff (768 active, 1124 total)
            VBLANK_A: 0x03c7039b (924 start, 968 end)
             VSYNC_A: 0x03a9039f (928 start, 938 end)
           BCLRPAT_A: 0x00000000
        VSYNCSHIFT_A: 0x00000000
            DSPBCNTR: 0x01000000 (disabled, pipe B)
          DSPBSTRIDE: 0x00000000 (0 bytes)
             DSPBPOS: 0x00000000 (0, 0)
            DSPBSIZE: 0x00000000 (1, 1)
            DSPBBASE: 0x00000000
            DSPBSURF: 0x00000000
         DSPBTILEOFF: 0x00000000
           PIPEBCONF: 0xc00c0000 (enabled, double-wide)
            PIPEBSRC: 0x027f01df (640, 480)
           PIPEBSTAT: 0x00000206 (status: VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
   PIPEB_GMCH_DATA_M: 0x00000000
   PIPEB_GMCH_DATA_N: 0x00000000
     PIPEB_DP_LINK_M: 0x00000000
     PIPEB_DP_LINK_N: 0x00000000
       CURSOR_B_BASE: 0x00000000
    CURSOR_B_CONTROL: 0x00000000
   CURSOR_B_POSITION: 0x00000000
                FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
                FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
              DPLL_B: 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
           DPLL_B_MD: 0x00000303
            HTOTAL_B: 0x031f027f (640 active, 800 total)
            HBLANK_B: 0x03170287 (648 start, 792 end)
             HSYNC_B: 0x02ef028f (656 start, 752 end)
            VTOTAL_B: 0x020c01df (480 active, 525 total)
            VBLANK_B: 0x020401e7 (488 start, 517 end)
             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
           BCLRPAT_B: 0x00000000
        VSYNCSHIFT_B: 0x00000000
   VCLK_DIVISOR_VGA0: 0x00031108
   VCLK_DIVISOR_VGA1: 0x00031406
       VCLK_POST_DIV: 0x00020002
            VGACNTRL: 0x8224008e (disabled)
              TV_CTL: 0x00000000
              TV_DAC: 0x00000000
            TV_CSC_Y: 0x00000000
           TV_CSC_Y2: 0x00000000
            TV_CSC_U: 0x00000000
           TV_CSC_U2: 0x00000000
            TV_CSC_V: 0x00000000
           TV_CSC_V2: 0x00000000
        TV_CLR_KNOBS: 0x00000000
        TV_CLR_LEVEL: 0x00000000
          TV_H_CTL_1: 0x00000000
          TV_H_CTL_2: 0x00000000
          TV_H_CTL_3: 0x00000000
          TV_V_CTL_1: 0x00000000
          TV_V_CTL_2: 0x00000000
          TV_V_CTL_3: 0x00000000
          TV_V_CTL_4: 0x00000000
          TV_V_CTL_5: 0x00000000
          TV_V_CTL_6: 0x00000000
          TV_V_CTL_7: 0x00000000
         TV_SC_CTL_1: 0x00000000
         TV_SC_CTL_2: 0x00000000
         TV_SC_CTL_3: 0x00000000
          TV_WIN_POS: 0x00000000
         TV_WIN_SIZE: 0x00000000
     TV_FILTER_CTL_1: 0x00000000
     TV_FILTER_CTL_2: 0x00000000
     TV_FILTER_CTL_3: 0x00000000
       TV_CC_CONTROL: 0x00000000
          TV_CC_DATA: 0x00000000
         TV_H_LUMA_0: 0x00000000
        TV_H_LUMA_59: 0x00000000
       TV_H_CHROMA_0: 0x00000000
      TV_H_CHROMA_59: 0x00000000
        FBC_CFB_BASE: 0xffffffff
         FBC_LL_BASE: 0xffffffff
         FBC_CONTROL: 0xffffffff
         FBC_COMMAND: 0xffffffff
          FBC_STATUS: 0xffffffff
        FBC_CONTROL2: 0xffffffff
       FBC_FENCE_OFF: 0xffffffff
         FBC_MOD_NUM: 0xffffffff
             MI_MODE: 0x00000640
        MI_ARB_STATE: 0x00000000
      MI_RDRET_STATE: 0x00000000
             ECOSKPD: 0x00000317
                DP_B: 0x00000000
      DPB_AUX_CH_CTL: 0x00000000
    DPB_AUX_CH_DATA1: 0x00000000
    DPB_AUX_CH_DATA2: 0x00000000
    DPB_AUX_CH_DATA3: 0x00000000
    DPB_AUX_CH_DATA4: 0x00000000
    DPB_AUX_CH_DATA5: 0x00000000
                DP_C: 0x00000000
      DPC_AUX_CH_CTL: 0x00000000
    DPC_AUX_CH_DATA1: 0x00000000
    DPC_AUX_CH_DATA2: 0x00000000
    DPC_AUX_CH_DATA3: 0x00000000
    DPC_AUX_CH_DATA4: 0x00000000
    DPC_AUX_CH_DATA5: 0x00000000
                DP_D: 0x00000000
      DPD_AUX_CH_CTL: 0x00000000
    DPD_AUX_CH_DATA1: 0x00000000
    DPD_AUX_CH_DATA2: 0x00000000
    DPD_AUX_CH_DATA3: 0x00000000
    DPD_AUX_CH_DATA4: 0x00000000
    DPD_AUX_CH_DATA5: 0x00000000
          AUD_CONFIG: 0x00000000
    AUD_HDMIW_STATUS: 0x00000000
      AUD_CONV_CHCNT: 0x00000000
       VIDEO_DIP_CTL: 0x00000000
       AUD_PINW_CNTR: 0x00000000
         AUD_CNTL_ST: 0x00000000
         AUD_PIN_CAP: 0x00000000
        AUD_PINW_CAP: 0x00000000
  AUD_PINW_UNSOLRESP: 0x00000000
    AUD_OUT_DIG_CNVT: 0x00000000
       AUD_OUT_CWCAP: 0x00000000
         AUD_GRP_CAP: 0x00000000
            FENCE  0: 0x00000000 (disabled)
            FENCE  1: 0x00000000 (disabled)
            FENCE  2: 0x00000000 (disabled)
            FENCE  3: 0x00000000 (disabled)
            FENCE  4: 0x00000000 (disabled)
            FENCE  5: 0x00000000 (disabled)
            FENCE  6: 0x00000000 (disabled)
            FENCE  7: 0x00000000 (disabled)
            FENCE  8: 0x0000007d (enabled, X tiled, 65536 pitch, 0x00000000 - 0x00100000 (1024kb))
            FENCE  9: 0x00fff000 (disabled)
           FENCE  10: 0x00000000 (disabled)
           FENCE  11: 0x00000000 (disabled)
           FENCE  12: 0x00000000 (disabled)
           FENCE  13: 0x00000000 (disabled)
           FENCE  14: 0x00000000 (disabled)
           FENCE  15: 0x00000000 (disabled)
       FENCE START 0: 0x0000007d (disabled)
         FENCE END 0: 0x00fff000 (disabled)
       FENCE START 1: 0x00000000 (disabled)
         FENCE END 1: 0x00000000 (disabled)
       FENCE START 2: 0x00000000 (disabled)
         FENCE END 2: 0x00000000 (disabled)
       FENCE START 3: 0x00000000 (disabled)
         FENCE END 3: 0x00000000 (disabled)
       FENCE START 4: 0x00000000 (disabled)
         FENCE END 4: 0x00000000 (disabled)
       FENCE START 5: 0x00000000 (disabled)
         FENCE END 5: 0x00000000 (disabled)
       FENCE START 6: 0x00000000 (disabled)
         FENCE END 6: 0x00000000 (disabled)
       FENCE START 7: 0x00000000 (disabled)
         FENCE END 7: 0x00000000 (disabled)
       FENCE START 8: 0x00000000 (disabled)
         FENCE END 8: 0x00000000 (disabled)
       FENCE START 9: 0x00000000 (disabled)
         FENCE END 9: 0x00000000 (disabled)
      FENCE START 10: 0x00000000 (disabled)
        FENCE END 10: 0x00000000 (disabled)
      FENCE START 11: 0x00000000 (disabled)
        FENCE END 11: 0x00000000 (disabled)
      FENCE START 12: 0x00000000 (disabled)
        FENCE END 12: 0x00000000 (disabled)
      FENCE START 13: 0x00000000 (disabled)
        FENCE END 13: 0x00000000 (disabled)
      FENCE START 14: 0x00000000 (disabled)
        FENCE END 14: 0x00000000 (disabled)
      FENCE START 15: 0x00000000 (disabled)
        FENCE END 15: 0x00000000 (disabled)
             INST_PM: 0x00000000

pipe A dot 148800 n 1 m1 15 m2 6 p1 2 p2 10
pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10

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#13 lore raw
In reply to Paulo Zanoni
Quoted 15 lines · Paulo Zanoni

Hi

2012/1/18 Peter Ross <[email protected]>:

Quoted 2 lines

This patch set enables enables interlaced mode output on generation 3 and above chipsets.

I just tested that on HDMI.

The "interlace_allowed=1" patch seems fine: it made xrandr list more modes. But I believe patch 1 is still not correct. I tested that and instead of getting a 1920x1080 I got a 1920x1078 mode: vtotal, vblank and vsync were wrong. If you look at the patch, you'll see that the code has some "something -= 1" statements. I believe they could be wrong.

Quoted 5 lines

So I removed these lines and tested again... Now the mode is actually 1920x1080, but my monitor's OSD displays it as "1080p". So I also tested my TV and it reported "1080p@25hz" too.

I guess we're still missing something... I'll try to debug.

To clarify, on which machines have you tried this? In particular, can you try this on an Ironlake?
-Daniel

Signature · 3 lines
Daniel Vetter
Mail: [email protected]
Mobile: +41 (0)79 365 57 48