Use scratch registers on XLR/XLS/XLP

PATCH Superseded Jayachandran C 2 participants 6 messages Mar 20, 2013 MIPS

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Jayachandran C

author

2013-03-20 16:25 UTC #0 lore raw

v2 cover Use scratch registers on XLR/XLS/XLP

This set of patches enable the use of scratch registers on XLR/XLS and XLP (cop0 reg 22, sel 0-7) to optimize the generated TLB handlers.

The current code assumes scratch is 31, which is fixed by the first patch. The second patch enables use of a scratch register when it is available even on a 32-bit or non-r2 platform. The third patch is a cleanup to consolidate all the defines needed into one file, this patch does not have any change in logic.

In the earlier scheme, if MIPS_PGD_C0_CONTEXT was defined, the Context register or a scratch register would contain the current PGD, and the Xcontext would contain the smp_processor_id shifted to index pointers.

In the new scheme, the behavior when MIPS_PGD_C0_CONTEXT is defined remains the same. But when it is not defined, we still try to allocate a scratch register for the current pgd. and the smp processor id remains in Context.

There is also an additional change is to generate the tlbmiss_handler_setup_pgd() function even when MIPS_PGD_C0_CONTEXT is not defined. This function will save the PGD in pgd_current[] and also in the scratch register if one has been allocated.

Comments/testing welcome.

Thanks,
JC.

Changes in v2:
* Update macros in thread-info.h, remove __ASSEMBLY__ part
* add ASM_CPUID_MFC0 and UASM_i_CPUID_MFC0 which allows us to remove a lot of conditional compilation.
* make c0_kscratch a inline function and remove global variable

Jayachandran C (3):
MIPS: Allow platform specific scratch registers
MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT
MIPS: Move definition of SMP processor id register to header file

 arch/mips/include/asm/mmu_context.h |   26 ++----
 arch/mips/include/asm/stackframe.h  |   26 ++----
 arch/mips/include/asm/thread_info.h |   30 +++++-
 arch/mips/kernel/cpu-probe.c        |    1 +
 arch/mips/mm/tlbex.c                |  176 +++++++++++++++++------------------
 5 files changed, 130 insertions(+), 129 deletions(-)

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-03-20 16:26 UTC #1 lore raw

PATCH v2 1/3 MIPS: Allow platform specific scratch registers

XLR/XLP COP0 scratch is register 22, sel 0-7. Add a function c0_kscratch() which returns the scratch register for the platform, and use the return value while generating TLB handlers.

Setup kscratch_mask to 0xf for XLR/XLP since the config4 register does not exist. This allows the kernel to allocate scratch registers 0-3 if needed.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/kernel/cpu-probe.c |    1 +
 arch/mips/mm/tlbex.c         |   41 ++++++++++++++++++++++++++---------------
 2 files changed, 27 insertions(+), 15 deletions(-)

arch/mips/kernel/cpu-probe.c +1 -0

index d069a19..1d7bfb3 100644
@@ -1154,6 +1154,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
 		set_isa(c, MIPS_CPU_ISA_M64R1);
 		c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
 	}
+	c->kscratch_mask = 0xf;
 }
 
 #ifdef CONFIG_64BIT

arch/mips/mm/tlbex.c +26 ~~-15~~

115 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Jayachandran C

author

2013-03-20 16:26 UTC #2 lore raw

PATCH v2 2/3 MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT

In reply to Jayachandran C

Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context which was used for cpuid to be used for saving PGD. This option was also tied to using a scratch register for storing PGD.

This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpu id will be kept in the CP0 Context register in this case.

The code to store the current pgd for the TLB miss handler is now generated in all cases. When scratch register is available, the PGD is also stored in the scratch register.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/mmu_context.h |    8 +-
 arch/mips/mm/tlbex.c                |  142 ++++++++++++++++++++++-------------
 2 files changed, 92 insertions(+), 58 deletions(-)

arch/mips/include/asm/mmu_context.h +2 -6

index e81d719..39e87ee 100644
@@ -24,13 +24,12 @@
 #endif /* SMTC */
 #include <asm-generic/mm_hooks.h>
 
-#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
 
 #define TLBMISS_HANDLER_SETUP_PGD(pgd)				\
 	tlbmiss_handler_setup_pgd((unsigned long)(pgd))
 
-extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
-
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
 #define TLBMISS_HANDLER_SETUP()						\
 	do {								\
 		TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);		\

@@ -46,9 +45,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
  */
 extern unsigned long pgd_current[];
 
-#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
-	pgd_current[smp_processor_id()] = (unsigned long)(pgd)
-
 #ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()						\
 	write_c0_context((unsigned long) smp_processor_id() << 25);	\

arch/mips/mm/tlbex.c +90 ~~-52~~

221 lines not on this page · raw message

Signature · 1 line

1.7.9.5

David Daney

2013-03-20 16:45 UTC #3 lore raw

Re: [PATCH 2/3] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT

Quoted 11 lines · Jayachandran C

Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context which was used for cpuid to be used for saving PGD. This option was also tied to using a scratch register for storing PGD.
This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpu id will be kept in the CP0 Context register in this case.

The point of MIPS_PGD_C0_CONTEXT is really to indicate that the PGD pointer is stored in a register (or portion thereof) and that setting the PGD is done by calling into uasm generated code.

Perhaps we should rename this Kconfig vairable so that its name indicates its function, or remove it altogether if possible, and machine generate the setting of the PGD pointer even when it is stored in the array in memory.

Quoted 277 lines

The code to store the current pgd for the TLB miss handler is now generated in all cases. When scratch register is available, the PGD is also stored in the scratch register.

Signed-off-by Jayachandran C <[email protected]>

---
  arch/mips/include/asm/mmu_context.h |    8 +-
  arch/mips/mm/tlbex.c                |  142 ++++++++++++++++++++++-------------
  2 files changed, 92 insertions(+), 58 deletions(-)

arch/mips/include/asm/mmu_context.h +2 -6

index e81d719..39e87ee 100644
@@ -24,13 +24,12 @@
  #endif /* SMTC */
  #include <asm-generic/mm_hooks.h>
 
-#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
+extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
 
  #define TLBMISS_HANDLER_SETUP_PGD(pgd)				\
  	tlbmiss_handler_setup_pgd((unsigned long)(pgd))
 
-extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
-
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  #define TLBMISS_HANDLER_SETUP()						\
  	do {								\
  		TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);		\

@@ -46,9 +45,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
   */
  extern unsigned long pgd_current[];
 
-#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
-	pgd_current[smp_processor_id()] = (unsigned long)(pgd)
-
  #ifdef CONFIG_32BIT
  #define TLBMISS_HANDLER_SETUP()						\
  	write_c0_context((unsigned long) smp_processor_id() << 25);	\

arch/mips/mm/tlbex.c +90 ~~-52~~

index ca470c6..ede46d7 100644
@@ -829,11 +829,11 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
  	}
  	/* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
 
-#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  	if (pgd_reg != -1) {
  		/* pgd is in pgd_reg */
  		UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
  	} else {
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  		/*
  		 * &pgd << 11 stored in CONTEXT [23..63].
  		 */

@@ -845,30 +845,30 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
  		/* 1 0	1 0 1  << 6  xkphys cached */
  		uasm_i_ori(p, ptr, ptr, 0x540);
  		uasm_i_drotr(p, ptr, ptr, 11);
-	}
  #elif defined(CONFIG_SMP)
-# ifdef	 CONFIG_MIPS_MT_SMTC
-	/*
-	 * SMTC uses TCBind value as "CPU" index
-	 */
-	uasm_i_mfc0(p, ptr, C0_TCBIND);
-	uasm_i_dsrl_safe(p, ptr, ptr, 19);
+# ifdef CONFIG_MIPS_MT_SMTC
+		/*
+		 * SMTC uses TCBind value as "CPU" index
+		 */
+		uasm_i_mfc0(p, ptr, C0_TCBIND);
+		uasm_i_dsrl_safe(p, ptr, ptr, 19);
  # else
-	/*
-	 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
-	 * stored in CONTEXT.
-	 */
-	uasm_i_dmfc0(p, ptr, C0_CONTEXT);
-	uasm_i_dsrl_safe(p, ptr, ptr, 23);
+		/*
+		 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
+		 * stored in CONTEXT.
+		 */
+		uasm_i_dmfc0(p, ptr, C0_CONTEXT);
+		uasm_i_dsrl_safe(p, ptr, ptr, 23);
  # endif
-	UASM_i_LA_mostly(p, tmp, pgdc);
-	uasm_i_daddu(p, ptr, ptr, tmp);
-	uasm_i_dmfc0(p, tmp, C0_BADVADDR);
-	uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
+		UASM_i_LA_mostly(p, tmp, pgdc);
+		uasm_i_daddu(p, ptr, ptr, tmp);
+		uasm_i_dmfc0(p, tmp, C0_BADVADDR);
+		uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
  #else
-	UASM_i_LA_mostly(p, ptr, pgdc);
-	uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
+		UASM_i_LA_mostly(p, ptr, pgdc);
+		uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
  #endif
+	}
 
  	uasm_l_vmalloc_done(l, *p);

@@ -963,31 +963,37 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
  static void __cpuinit __maybe_unused
  build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
  {
-	long pgdc = (long)pgd_current;
+	if (pgd_reg != -1) {
+		/* pgd is in pgd_reg */
+		uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
+		uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
+	} else {
+		long pgdc = (long)pgd_current;
 
-	/* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
+		/* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
  #ifdef CONFIG_SMP
-#ifdef	CONFIG_MIPS_MT_SMTC
-	/*
-	 * SMTC uses TCBind value as "CPU" index
-	 */
-	uasm_i_mfc0(p, ptr, C0_TCBIND);
-	UASM_i_LA_mostly(p, tmp, pgdc);
-	uasm_i_srl(p, ptr, ptr, 19);
-#else
-	/*
-	 * smp_processor_id() << 3 is stored in CONTEXT.
-	 */
-	uasm_i_mfc0(p, ptr, C0_CONTEXT);
-	UASM_i_LA_mostly(p, tmp, pgdc);
-	uasm_i_srl(p, ptr, ptr, 23);
-#endif
-	uasm_i_addu(p, ptr, tmp, ptr);
+# ifdef CONFIG_MIPS_MT_SMTC
+		/*
+		 * SMTC uses TCBind value as "CPU" index
+		 */
+		uasm_i_mfc0(p, ptr, C0_TCBIND);
+		UASM_i_LA_mostly(p, tmp, pgdc);
+		uasm_i_srl(p, ptr, ptr, 19);
+# else
+		/*
+		 * smp_processor_id() << 3 is stored in CONTEXT.
+		 */
+		uasm_i_mfc0(p, ptr, C0_CONTEXT);
+		UASM_i_LA_mostly(p, tmp, pgdc);
+		uasm_i_srl(p, ptr, ptr, 23);
+# endif
+		uasm_i_addu(p, ptr, tmp, ptr);
  #else
-	UASM_i_LA_mostly(p, ptr, pgdc);
+		UASM_i_LA_mostly(p, ptr, pgdc);
  #endif
-	uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
-	uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
+		uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
+		uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
+	}
  	uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
  	uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
  	uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */

@@ -1468,16 +1474,17 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
  u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
  u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
  u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
-#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  u32 tlbmiss_handler_setup_pgd[16] __cacheline_aligned;
 
-static void __cpuinit build_r4000_setup_pgd(void)
+static void __cpuinit build_setup_pgd(void)
  {
  	const int a0 = 4;
-	const int a1 = 5;
+	const int __maybe_unused a1 = 5;
+	const int __maybe_unused a2 = 6;
  	u32 *p = tlbmiss_handler_setup_pgd;
-	struct uasm_label *l = labels;
-	struct uasm_reloc *r = relocs;
+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
+	long pgdc = (long)pgd_current;
+#endif
 
  	memset(tlbmiss_handler_setup_pgd, 0, sizeof(tlbmiss_handler_setup_pgd));
  	memset(labels, 0, sizeof(labels));

@@ -1485,7 +1492,11 @@ static void __cpuinit build_r4000_setup_pgd(void)
 
  	pgd_reg = allocate_kscratch();
 
+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  	if (pgd_reg == -1) {
+		struct uasm_label *l = labels;
+		struct uasm_reloc *r = relocs;
+
  		/* PGD << 11 in c0_Context */
  		/*
  		 * If it is a ckseg0 address, convert to a physical

@@ -1507,6 +1518,37 @@ static void __cpuinit build_r4000_setup_pgd(void)
  		uasm_i_jr(&p, 31);
  		UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
  	}
+#else
+	/* Save PGD to pgd_current[smp_processor_id()] */
+#if defined(CONFIG_SMP)
+# ifdef CONFIG_MIPS_MT_SMTC
+	/*
+	 * SMTC uses TCBind value as "CPU" index
+	 */
+	uasm_i_mfc0(&p, a1, C0_TCBIND);
+	uasm_i_dsrl_safe(&p, a1, a1, 19);
+# else
+	/*
+	 * smp_processor_id() is in CONTEXT
+	 */
+	UASM_i_MFC0(&p, a1, C0_CONTEXT);
+	uasm_i_dsrl_safe(&p, a1, a1, 23);
+# endif
+	UASM_i_LA_mostly(&p, a2, pgdc);
+	UASM_i_ADDU(&p, a2, a2, a1);
+	UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
+#else
+	UASM_i_LA_mostly(&p, a2, pgdc);
+	UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
+#endif /* SMP */
+	uasm_i_jr(&p, 31);
+
+	/* if pgd_reg is allocated, save PGD also to scratch register */
+	if (pgd_reg != -1)
+		UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
+	else
+		uasm_i_nop(&p);
+#endif
  	if (p - tlbmiss_handler_setup_pgd > ARRAY_SIZE(tlbmiss_handler_setup_pgd))
  		panic("tlbmiss_handler_setup_pgd space exceeded");
  	uasm_resolve_relocs(relocs, labels);

@@ -1517,7 +1559,6 @@ static void __cpuinit build_r4000_setup_pgd(void)
  		     tlbmiss_handler_setup_pgd,
  		     ARRAY_SIZE(tlbmiss_handler_setup_pgd));
  }
-#endif
 
  static void __cpuinit
  iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)

@@ -2175,6 +2216,7 @@ void __cpuinit build_tlb_refill_handler(void)
  #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
  		build_r3000_tlb_refill_handler();
  		if (!run_once) {
+			build_setup_pgd();
  			build_r3000_tlb_load_handler();
  			build_r3000_tlb_store_handler();
  			build_r3000_tlb_modify_handler();

@@ -2197,9 +2239,7 @@ void __cpuinit build_tlb_refill_handler(void)
  	default:
  		if (!run_once) {
  			scratch_reg = allocate_kscratch();
-#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
-			build_r4000_setup_pgd();
-#endif
+			build_setup_pgd();
  			build_r4000_tlb_load_handler();
  			build_r4000_tlb_store_handler();
  			build_r4000_tlb_modify_handler();

@@ -2217,8 +2257,6 @@ void __cpuinit flush_tlb_handlers(void)
  			   (unsigned long)handle_tlbs + sizeof(handle_tlbs));
  	local_flush_icache_range((unsigned long)handle_tlbm,
  			   (unsigned long)handle_tlbm + sizeof(handle_tlbm));
-#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  	local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
  			   (unsigned long)tlbmiss_handler_setup_pgd + sizeof(handle_tlbm));
-#endif
  }

Jayachandran C.

author

2013-03-20 17:59 UTC #4 lore raw

Re: [PATCH 2/3] MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT

Quoted 14 lines · David Daney

Quoted 11 lines · Jayachandran C
Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context which was used for cpuid to be used for saving PGD. This option was also tied to using a scratch register for storing PGD.
This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpu id will be kept in the CP0 Context register in this case.

Quoted 8 lines

The point of MIPS_PGD_C0_CONTEXT is really to indicate that the PGD pointer is stored in a register (or portion thereof) and that setting the PGD is done by calling into uasm generated code.
Perhaps we should rename this Kconfig vairable so that its name indicates its function, or remove it altogether if possible, and machine generate the setting of the PGD pointer even when it is stored in the array in memory.

Removing the MIPS_PGD_C0_CONTEXT Kconfig variable does not look feasible. The processor id is used by get_saved_sp macro and it needs to know at compile time whether the processor id is in Context or Xcontext. We could call it something like MIPS_PROCESSOR_ID_IN_XCONTEXT (if it would not affect too many config files).

The second part (generating code for setting PGD pointer in pgd_current) is already in the patch. This generated code also saves PGD to the scratch register if one was allocated.

JC.

Jayachandran C

author

2013-03-20 16:26 UTC #5 lore raw

PATCH v2 3/3 MIPS: Move definition of SMP processor id register to header file

In reply to Jayachandran C

The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/mmu_context.h |   18 +++------
 arch/mips/include/asm/stackframe.h  |   26 ++++--------
 arch/mips/include/asm/thread_info.h |   30 +++++++++++++-
 arch/mips/mm/tlbex.c                |   75 +++++------------------------------
 4 files changed, 52 insertions(+), 97 deletions(-)

arch/mips/include/asm/mmu_context.h +6 ~~-12~~

index 39e87ee..514a7fd 100644
@@ -26,17 +26,18 @@
 
 extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
 
-#define TLBMISS_HANDLER_SETUP_PGD(pgd)				\
+#define TLBMISS_HANDLER_SETUP_PGD(pgd)					\
 	tlbmiss_handler_setup_pgd((unsigned long)(pgd))
 
 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
 #define TLBMISS_HANDLER_SETUP()						\
 	do {								\
 		TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);		\
-		write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
+		write_c0_xcontext((unsigned long) smp_processor_id() <<	\
+						SMP_CPUID_REGSHIFT);	\
 	} while (0)
 
-#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
+#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
 
 /*
  * For the fast tlb miss handlers, we keep a per cpu array of pointers

@@ -45,18 +46,11 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
  */
 extern unsigned long pgd_current[];
 
-#ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()						\
-	write_c0_context((unsigned long) smp_processor_id() << 25);	\
+	write_c0_context((unsigned long) smp_processor_id() <<		\
+						SMP_CPUID_REGSHIFT);	\
 	back_to_back_c0_hazard();					\
 	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
-#endif
-#ifdef CONFIG_64BIT
-#define TLBMISS_HANDLER_SETUP()						\
-	write_c0_context((unsigned long) smp_processor_id() << 26);	\
-	back_to_back_c0_hazard();					\
-	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
-#endif
 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

arch/mips/include/asm/stackframe.h +7 ~~-19~~

index c993840..690a71c 100644
@@ -17,6 +17,7 @@
 #include <asm/asmmacro.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
 
 /*
  * For SMTC kernel, global IE should be left set, and interrupts

@@ -85,21 +86,8 @@
 		.endm
 
 #ifdef CONFIG_SMP
-#ifdef CONFIG_MIPS_MT_SMTC
-#define PTEBASE_SHIFT	19	/* TCBIND */
-#define CPU_ID_REG CP0_TCBIND
-#define CPU_ID_MFC0 mfc0
-#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
-#define PTEBASE_SHIFT	48	/* XCONTEXT */
-#define CPU_ID_REG CP0_XCONTEXT
-#define CPU_ID_MFC0 MFC0
-#else
-#define PTEBASE_SHIFT	23	/* CONTEXT */
-#define CPU_ID_REG CP0_CONTEXT
-#define CPU_ID_MFC0 MFC0
-#endif
 		.macro	get_saved_sp	/* SMP variation */
-		CPU_ID_MFC0	k0, CPU_ID_REG
+		ASM_CPUID_MFC0	k0, $SMP_CPUID_REG
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
 		lui	k1, %hi(kernelsp)
 #else

@@ -109,17 +97,17 @@
 		daddiu	k1, %hi(kernelsp)
 		dsll	k1, 16
 #endif
-		LONG_SRL	k0, PTEBASE_SHIFT
+		LONG_SRL	k0, SMP_CPUID_PTRSHIFT
 		LONG_ADDU	k1, k0
 		LONG_L	k1, %lo(kernelsp)(k1)
 		.endm
 
 		.macro	set_saved_sp stackp temp temp2
-		CPU_ID_MFC0	\temp, CPU_ID_REG
-		LONG_SRL	\temp, PTEBASE_SHIFT
+		ASM_CPUID_MFC0	\temp, $SMP_CPUID_REG
+		LONG_SRL	\temp, SMP_CPUID_PTRSHIFT
 		LONG_S	\stackp, kernelsp(\temp)
 		.endm
-#else
+#else /* !CONFIG_SMP */
 		.macro	get_saved_sp	/* Uniprocessor variation */
 #ifdef CONFIG_CPU_JUMP_WORKAROUNDS
 		/*

@@ -139,7 +127,7 @@
 1:		move	ra, k0
 		li	k0, 3
 		mtc0	k0, $22
-#endif /* CONFIG_CPU_LOONGSON2F */
+#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
 		lui	k1, %hi(kernelsp)
 #else

arch/mips/include/asm/thread_info.h +29 -1

index 178f792..e373626 100644
@@ -136,6 +136,34 @@ register struct thread_info *__current_thread_info __asm__("$28");
 /* work to do on any return to u-space */
 #define _TIF_ALLWORK_MASK	(_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT)
 
-#endif /* __KERNEL__ */
+/*
+ * We stash processor id into a COP0 register to retrieve it fast
+ * at kernel exception entry. The register and shift used for this.
+ */
+#if defined(CONFIG_MIPS_MT_SMTC)
+#define SMP_CPUID_REG		2, 2	/* TCBIND */
+#define SMP_CPUID_PTRSHIFT	19
+#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
+#define SMP_CPUID_REG		20, 0	/* XCONTEXT */
+#define SMP_CPUID_PTRSHIFT	48
+#else
+#define SMP_CPUID_REG		4, 0	/* CONTEXT */
+#define SMP_CPUID_PTRSHIFT	23
+#endif
 
+#ifdef CONFIG_64BIT
+#define SMP_CPUID_REGSHIFT	(SMP_CPUID_PTRSHIFT + 3)
+#else
+#define SMP_CPUID_REGSHIFT	(SMP_CPUID_PTRSHIFT + 2)
+#endif
+
+#ifdef CONFIG_MIPS_MT_SMTC
+#define ASM_CPUID_MFC0		mfc0
+#define UASM_i_CPUID_MFC0	uasm_i_mfc0
+#else
+#define ASM_CPUID_MFC0		MFC0
+#define UASM_i_CPUID_MFC0	UASM_i_MFC0
+#endif
+
+#endif /* __KERNEL__ */
 #endif /* _ASM_THREAD_INFO_H */

arch/mips/mm/tlbex.c +10 ~~-65~~

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