drm/i915: initialize backlight pwm frequency from vbt if needed

PATCH In review Jani Nikula 3 participants 6 messages Jan 7, 2014 – Feb 5, 2014

Subsystems (2)

DRM drivers Intel i915

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Jani Nikula

author

2014-01-07 16:06 UTC #0 lore raw

cover drm/i915: initialize backlight pwm frequency from vbt if needed

Per inquiries from Vathsala et al, here's some early code for initializing the backlight PWM from VBT if it hasn't been initialized by the BIOS. I didn't have the chance to test this at all yet, just wanted to unblock others. Testing and comments welcome. Particularly the frequency in Hz to PWM register value conversions need eyeballs.

BR,
Jani.

Jani Nikula (2):
drm/i915: move intel_hrawclk() to intel_display.c drm/i915: initialize backlight max from vbt

 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   33 ++++++
 drivers/gpu/drm/i915/intel_dp.c      |   34 ------
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 drivers/gpu/drm/i915/intel_panel.c   |  197 +++++++++++++++++++++++++++++-----
 5 files changed, 204 insertions(+), 62 deletions(-)

Signature · 1 line

1.7.10.4

Jani Nikula

author

2014-01-07 16:07 UTC #5 lore raw

PATCH 2/2 drm/i915: initialize backlight max from vbt

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/i915_reg.h    |    1 +
 drivers/gpu/drm/i915/intel_panel.c |  197 +++++++++++++++++++++++++++++++-----
 2 files changed, 170 insertions(+), 28 deletions(-)

drivers/gpu/drm/i915/i915_reg.h +1 -0

index a699efd..344f717 100644
@@ -4531,6 +4531,7 @@
 #define SOUTH_CHICKEN2		0xc2004
 #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
 #define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
+#define  PWM_GRANULARITY		(1<<5)	/* LPT */
 #define  DPLS_EDP_PPS_FIX_DIS		(1<<0)
 
 #define _FDI_RXA_CHICKEN         0xc200c

drivers/gpu/drm/i915/intel_panel.c +169 ~~-28~~

249 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Jani Nikula

author

2014-01-07 16:07 UTC #1 lore raw

PATCH 1/2 drm/i915: move intel_hrawclk() to intel_display.c

In reply to Jani Nikula

Make it available outside of intel_dp.c.

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_display.c |   33 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c      |   34 ----------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 3 files changed, 34 insertions(+), 34 deletions(-)

drivers/gpu/drm/i915/intel_display.c +33 -0

index a562eef..e784feb 100644
@@ -78,6 +78,39 @@ intel_pch_rawclk(struct drm_device *dev)
 	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 }
 
+/* hrawclock is 1/4 the FSB frequency */
+int intel_hrawclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t clkcfg;
+
+	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+	if (IS_VALLEYVIEW(dev))
+		return 200;
+
+	clkcfg = I915_READ(CLKCFG);
+	switch (clkcfg & CLKCFG_FSB_MASK) {
+	case CLKCFG_FSB_400:
+		return 100;
+	case CLKCFG_FSB_533:
+		return 133;
+	case CLKCFG_FSB_667:
+		return 166;
+	case CLKCFG_FSB_800:
+		return 200;
+	case CLKCFG_FSB_1067:
+		return 266;
+	case CLKCFG_FSB_1333:
+		return 333;
+	/* these two are just a guess; one of them might be right */
+	case CLKCFG_FSB_1600:
+	case CLKCFG_FSB_1600_ALT:
+		return 400;
+	default:
+		return 133;
+	}
+}
+
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
 {

drivers/gpu/drm/i915/intel_dp.c +0 ~~-34~~

index 7df5085..a36a2a3 100644
@@ -203,40 +203,6 @@ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 		dst[i] = src >> ((3-i) * 8);
 }
 
-/* hrawclock is 1/4 the FSB frequency */
-static int
-intel_hrawclk(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t clkcfg;
-
-	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
-	if (IS_VALLEYVIEW(dev))
-		return 200;
-
-	clkcfg = I915_READ(CLKCFG);
-	switch (clkcfg & CLKCFG_FSB_MASK) {
-	case CLKCFG_FSB_400:
-		return 100;
-	case CLKCFG_FSB_533:
-		return 133;
-	case CLKCFG_FSB_667:
-		return 166;
-	case CLKCFG_FSB_800:
-		return 200;
-	case CLKCFG_FSB_1067:
-		return 266;
-	case CLKCFG_FSB_1333:
-		return 333;
-	/* these two are just a guess; one of them might be right */
-	case CLKCFG_FSB_1600:
-	case CLKCFG_FSB_1600_ALT:
-		return 400;
-	default:
-		return 133;
-	}
-}
-
 static void
 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 				    struct intel_dp *intel_dp,

drivers/gpu/drm/i915/intel_drv.h +1 -0

index 46aea6c..9c5e984 100644
@@ -626,6 +626,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 
 /* intel_display.c */
 int intel_pch_rawclk(struct drm_device *dev);
+int intel_hrawclk(struct drm_device *dev);
 void intel_mark_busy(struct drm_device *dev);
 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 			struct intel_ring_buffer *ring);

Signature · 1 line

1.7.10.4

Daniel Vetter

2014-01-07 16:24 UTC #2 lore raw

Re: [PATCH 1/2] drm/i915: move intel_hrawclk() to intel_display.c

Quoted 3 lines · Jani Nikula

Make it available outside of intel_dp.c.
Signed-off-by Jani Nikula <[email protected]>

Since this only really applies to gmch platforms I wonder whether we should give this a more platforms specific prefix. Established precedence would point towardy i9xx_ I think ... But I'm happy with other colors, too. Maybe a patch on top of this series for less fuzz? -Daniel

Quoted 114 lines

---
 drivers/gpu/drm/i915/intel_display.c |   33 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c      |   34 ----------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 3 files changed, 34 insertions(+), 34 deletions(-)

drivers/gpu/drm/i915/intel_display.c +33 -0

index a562eef..e784feb 100644
@@ -78,6 +78,39 @@ intel_pch_rawclk(struct drm_device *dev)
 	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 }
 
+/* hrawclock is 1/4 the FSB frequency */
+int intel_hrawclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t clkcfg;
+
+	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+	if (IS_VALLEYVIEW(dev))
+		return 200;
+
+	clkcfg = I915_READ(CLKCFG);
+	switch (clkcfg & CLKCFG_FSB_MASK) {
+	case CLKCFG_FSB_400:
+		return 100;
+	case CLKCFG_FSB_533:
+		return 133;
+	case CLKCFG_FSB_667:
+		return 166;
+	case CLKCFG_FSB_800:
+		return 200;
+	case CLKCFG_FSB_1067:
+		return 266;
+	case CLKCFG_FSB_1333:
+		return 333;
+	/* these two are just a guess; one of them might be right */
+	case CLKCFG_FSB_1600:
+	case CLKCFG_FSB_1600_ALT:
+		return 400;
+	default:
+		return 133;
+	}
+}
+
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
 {

drivers/gpu/drm/i915/intel_dp.c +0 ~~-34~~

index 7df5085..a36a2a3 100644
@@ -203,40 +203,6 @@ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 		dst[i] = src >> ((3-i) * 8);
 }
 
-/* hrawclock is 1/4 the FSB frequency */
-static int
-intel_hrawclk(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t clkcfg;
-
-	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
-	if (IS_VALLEYVIEW(dev))
-		return 200;
-
-	clkcfg = I915_READ(CLKCFG);
-	switch (clkcfg & CLKCFG_FSB_MASK) {
-	case CLKCFG_FSB_400:
-		return 100;
-	case CLKCFG_FSB_533:
-		return 133;
-	case CLKCFG_FSB_667:
-		return 166;
-	case CLKCFG_FSB_800:
-		return 200;
-	case CLKCFG_FSB_1067:
-		return 266;
-	case CLKCFG_FSB_1333:
-		return 333;
-	/* these two are just a guess; one of them might be right */
-	case CLKCFG_FSB_1600:
-	case CLKCFG_FSB_1600_ALT:
-		return 400;
-	default:
-		return 133;
-	}
-}
-
 static void
 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 				    struct intel_dp *intel_dp,

drivers/gpu/drm/i915/intel_drv.h +1 -0

index 46aea6c..9c5e984 100644
@@ -626,6 +626,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 
 /* intel_display.c */
 int intel_pch_rawclk(struct drm_device *dev);
+int intel_hrawclk(struct drm_device *dev);
 void intel_mark_busy(struct drm_device *dev);
 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 			struct intel_ring_buffer *ring);

Signature · 6 lines

1.7.10.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 3 lines

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Jani Nikula

author

2014-01-07 16:49 UTC #3 lore raw

Re: [PATCH 1/2] drm/i915: move intel_hrawclk() to intel_display.c

Quoted 9 lines · Daniel Vetter

Quoted 3 lines · Jani Nikula
Make it available outside of intel_dp.c.
Signed-off-by Jani Nikula <[email protected]>
Since this only really applies to gmch platforms I wonder whether we should give this a more platforms specific prefix. Established precedence would point towardy i9xx_ I think ... But I'm happy with other colors, too. Maybe a patch on top of this series for less fuzz?

Good point, will do (once we have this cleared up).

BR,
Jani.

Quoted 125 lines

-Daniel

Quoted 114 lines

---
 drivers/gpu/drm/i915/intel_display.c |   33 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c      |   34 ----------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 3 files changed, 34 insertions(+), 34 deletions(-)

drivers/gpu/drm/i915/intel_display.c +33 -0

index a562eef..e784feb 100644
@@ -78,6 +78,39 @@ intel_pch_rawclk(struct drm_device *dev)
 	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 }
 
+/* hrawclock is 1/4 the FSB frequency */
+int intel_hrawclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t clkcfg;
+
+	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+	if (IS_VALLEYVIEW(dev))
+		return 200;
+
+	clkcfg = I915_READ(CLKCFG);
+	switch (clkcfg & CLKCFG_FSB_MASK) {
+	case CLKCFG_FSB_400:
+		return 100;
+	case CLKCFG_FSB_533:
+		return 133;
+	case CLKCFG_FSB_667:
+		return 166;
+	case CLKCFG_FSB_800:
+		return 200;
+	case CLKCFG_FSB_1067:
+		return 266;
+	case CLKCFG_FSB_1333:
+		return 333;
+	/* these two are just a guess; one of them might be right */
+	case CLKCFG_FSB_1600:
+	case CLKCFG_FSB_1600_ALT:
+		return 400;
+	default:
+		return 133;
+	}
+}
+
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
 {

drivers/gpu/drm/i915/intel_dp.c +0 ~~-34~~

index 7df5085..a36a2a3 100644
@@ -203,40 +203,6 @@ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 		dst[i] = src >> ((3-i) * 8);
 }
 
-/* hrawclock is 1/4 the FSB frequency */
-static int
-intel_hrawclk(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t clkcfg;
-
-	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
-	if (IS_VALLEYVIEW(dev))
-		return 200;
-
-	clkcfg = I915_READ(CLKCFG);
-	switch (clkcfg & CLKCFG_FSB_MASK) {
-	case CLKCFG_FSB_400:
-		return 100;
-	case CLKCFG_FSB_533:
-		return 133;
-	case CLKCFG_FSB_667:
-		return 166;
-	case CLKCFG_FSB_800:
-		return 200;
-	case CLKCFG_FSB_1067:
-		return 266;
-	case CLKCFG_FSB_1333:
-		return 333;
-	/* these two are just a guess; one of them might be right */
-	case CLKCFG_FSB_1600:
-	case CLKCFG_FSB_1600_ALT:
-		return 400;
-	default:
-		return 133;
-	}
-}
-
 static void
 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 				    struct intel_dp *intel_dp,

drivers/gpu/drm/i915/intel_drv.h +1 -0

index 46aea6c..9c5e984 100644
@@ -626,6 +626,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 
 /* intel_display.c */
 int intel_pch_rawclk(struct drm_device *dev);
+int intel_hrawclk(struct drm_device *dev);
 void intel_mark_busy(struct drm_device *dev);
 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 			struct intel_ring_buffer *ring);

Signature · 6 lines

1.7.10.4

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 7 lines

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 1 line

Jani Nikula, Intel Open Source Technology Center

Jesse Barnes

Reviewed-by on v1 1/2

2014-02-05 15:03 UTC #4 lore raw

Re: [PATCH 1/2] drm/i915: move intel_hrawclk() to intel_display.c

In reply to Jani Nikula

Quoted 103 lines · On Tue, 7 Jan 2014 18:01:33 +0200 Jani Nikula <[email protected]> wrote:

Make it available outside of intel_dp.c.

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_display.c |   33 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c      |   34 ----------------------------------
 drivers/gpu/drm/i915/intel_drv.h     |    1 +
 3 files changed, 34 insertions(+), 34 deletions(-)

drivers/gpu/drm/i915/intel_display.c +33 -0

index a562eef..e784feb 100644
@@ -78,6 +78,39 @@ intel_pch_rawclk(struct drm_device *dev)
 	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 }
 
+/* hrawclock is 1/4 the FSB frequency */
+int intel_hrawclk(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t clkcfg;
+
+	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
+	if (IS_VALLEYVIEW(dev))
+		return 200;
+
+	clkcfg = I915_READ(CLKCFG);
+	switch (clkcfg & CLKCFG_FSB_MASK) {
+	case CLKCFG_FSB_400:
+		return 100;
+	case CLKCFG_FSB_533:
+		return 133;
+	case CLKCFG_FSB_667:
+		return 166;
+	case CLKCFG_FSB_800:
+		return 200;
+	case CLKCFG_FSB_1067:
+		return 266;
+	case CLKCFG_FSB_1333:
+		return 333;
+	/* these two are just a guess; one of them might be right */
+	case CLKCFG_FSB_1600:
+	case CLKCFG_FSB_1600_ALT:
+		return 400;
+	default:
+		return 133;
+	}
+}
+
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
 {

drivers/gpu/drm/i915/intel_dp.c +0 ~~-34~~

index 7df5085..a36a2a3 100644
@@ -203,40 +203,6 @@ unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 		dst[i] = src >> ((3-i) * 8);
 }
 
-/* hrawclock is 1/4 the FSB frequency */
-static int
-intel_hrawclk(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t clkcfg;
-
-	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
-	if (IS_VALLEYVIEW(dev))
-		return 200;
-
-	clkcfg = I915_READ(CLKCFG);
-	switch (clkcfg & CLKCFG_FSB_MASK) {
-	case CLKCFG_FSB_400:
-		return 100;
-	case CLKCFG_FSB_533:
-		return 133;
-	case CLKCFG_FSB_667:
-		return 166;
-	case CLKCFG_FSB_800:
-		return 200;
-	case CLKCFG_FSB_1067:
-		return 266;
-	case CLKCFG_FSB_1333:
-		return 333;
-	/* these two are just a guess; one of them might be right */
-	case CLKCFG_FSB_1600:
-	case CLKCFG_FSB_1600_ALT:
-		return 400;
-	default:
-		return 133;
-	}
-}
-
 static void
 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 				    struct intel_dp *intel_dp,

drivers/gpu/drm/i915/intel_drv.h +0 -0

index 46aea6c..9c5e984 100644

drivers/gpu/drm/i915/intel_drv.h void intel_ddi_get_config(struct intel_encoder *encoder, · line 632

Quoted 7 lines

drivers/gpu/drm/i915/intel_drv.h +1 -0

@@ -626,6 +626,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
 
 /* intel_display.c */
 int intel_pch_rawclk(struct drm_device *dev);
+int intel_hrawclk(struct drm_device *dev);
 void intel_mark_busy(struct drm_device *dev);
 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
 			struct intel_ring_buffer *ring);

Reviewed-by Jesse Barnes <[email protected]>