Add platform support for LSI AXM55xx

arch/arm/mach-axxia/Kconfig new file +1 -0

new file mode 100644
index 0000000..8c308fd
@@ -0,0 +1,16 @@
+config ARCH_AXXIA

arch/arm/mach-axxia/Kconfig new file +11 -0

+static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	struct device_node *syscon_np;
+	void __iomem *syscon;
+	u32 tmp;
+
+	syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon");
+	if (!syscon_np)
+		return -ENOENT;
+
+	syscon = of_iomap(syscon_np, 0);

Add clk driver to support clock blocks found on the AXM55xx devices. The driver provides clock implementations for three different types of clock devices on the AXM55xx device: PLL clock, a clock divider and a clock mux.

Signed-off-by Anders Berg <[email protected]>

---
 .../devicetree/bindings/clock/clk-axxia.txt        |  88 +++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-axxia.c                            | 281 +++++++++++++++++++++
 3 files changed, 370 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-axxia.txt
 create mode 100644 drivers/clk/clk-axxia.c

Documentation/devicetree/bindings/clock/clk-axxia.txt new file +88 -0

new file mode 100644
index 0000000..94eb840
@@ -0,0 +1,88 @@
+* Axxia clock driver bindings
+
+This document contains bindings for the Axxia PLL, clock divider and mux. The
+binding uses the common clock binding found in:
+
+       Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+* Axxia PLL
+
+Required properties:
+- #clock-cells : shall be set to 0.
+- compatible : shall be "lsi,axxia-pll-clock"
+- clocks : parent clock phandle
+- reg - specifies PLL control registers
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+
+       clk_ref0: clk_ref0 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;
+       };
+
+       clk_cpu_pll: clk_cpu_pll at 2010022000 {
+               compatible = "lsi,axxia-pll-clock";
+               #clock-cells = <0>;
+               clocks = <&clk_ref0>;
+               clock-output-names = "clk_cpu_pll";
+               reg = <0x20 0x10022000 0 0x2c>;
+       };
+
+
+* Axxia clock divider
+
+Required properties:
+- #clock-cells : shall be set to 0.
+- compatible : shall be "lsi,axxia-div-clock"
+- clocks : parent clock phandle
+- reg - clock divider control register
+- lsi,bit-shift : bit position of the divider control field.
+- lsi,bit-mask : width of the divider control field.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+
+       clk_cpu_div: cpu {
+               compatible = "lsi,axxia-div-clock";
+               #clock-cells = <0>;
+               clocks = <&clk_cpu_pll>;
+               clock-output-names = "clk_cpu_div";
+               reg = <0x20 0x10030008 0 0x4>;
+               lsi,bit-shift = <0>;
+               lsi,bit-width = <4>;
+       };
+
+
+* Axxia clock mux
+
+Required properties:
+- #clock-cells : shall be set to 0.
+- compatible : shall be "lsi,axxia-mux-clock"
+- clocks : phandle of parent clocks (max 4)
+- reg - clock divider control register
+- lsi,bit-shift : bit position of the divider control field.
+- lsi,bit-mask : width of the divider control field.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+
+       clk_cpu: clk_cpu0 at 2010030000 {
+               compatible = "lsi,axxia-mux-clock";
+               #clock-cells = <0>;
+               clocks = <&clk_ref0>,
+                        <&clk_cpu_pll>,
+                        <&clk_cpu_div>,
+                        <&clk_cpu_div>;
+               clock-output-names = "clk_cpu";
+               reg = <0x20 0x10030000 0 0x4>;
+               lsi,bit-shift = <0>;
+               lsi,bit-width = <2>;
+       };

drivers/clk/Makefile +1 -0

index 88af4a3..a9d0626 100644
@@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK)      += clk-composite.o
 # hardware specific clock types
 # please keep this section sorted lexicographically by file/directory path name
 obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)    += clk-axi-clkgen.o
+obj-$(CONFIG_ARCH_AXXIA)               += clk-axxia.o
 obj-$(CONFIG_ARCH_BCM2835)             += clk-bcm2835.o
 obj-$(CONFIG_ARCH_EFM32)               += clk-efm32gg.o
 obj-$(CONFIG_ARCH_HIGHBANK)            += clk-highbank.o

drivers/clk/clk-axxia.c new file +281 -1

new file mode 100644
index 0000000..996b8f2
@@ -0,0 +1,281 @@
+/*
+ * arch/arm/mach-axxia/clock.c
+ *
+ * Provides clock implementations for three different types of clock devices on
+ * the Axxia device: PLL clock, a clock divider and a clock mux.
+ *
+ * Copyright (C) 2012 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk-provider.h>
+
+
+static void __iomem *
+parse_and_map_reg(struct device_node *node, u32 *shift, u32 *width)
+{
+       void __iomem *reg;
+
+       if (of_property_read_u32(node, "lsi,bit-shift", shift)) {
+               pr_err("%s: no 'lsi,bit-shift' property\n", node->name);
+               return NULL;
+       }
+
+       if (of_property_read_u32(node, "lsi,bit-width", width)) {
+               pr_err("%s: no 'lsi,bit-width' property\n", node->name);
+               return NULL;
+       }
+
+       reg = of_iomap(node, 0);
+       if (!reg)
+               pr_err("%s: failed to map register\n", node->name);
+
+       return reg;
+}
+
+/**
+ * struct axxia_pllclk - Axxia PLL generated clock.
+ * @hw: clk_hw for the PLL
+ * @regs: Pointer to control registers
+ */
+struct axxia_pllclk {
+       struct clk_hw hw;
+       void __iomem *regs;
+};
+
+#define to_axxia_pll(_hw) container_of(_hw, struct axxia_pllclk, hw)
+
+static unsigned long
+axxia_pllclk_recalc(struct clk_hw *hw, unsigned long parent_rate)
+{
+       struct axxia_pllclk *pll = to_axxia_pll(hw);
+       unsigned long rate, fbdiv, refdiv, postdiv;
+       u32 control;
+
+       control = readl(pll->regs);
+       postdiv = ((control >> 0) & 0xf) + 1;
+       fbdiv   = ((control >> 4) & 0xfff) + 3;
+       refdiv  = ((control >> 16) & 0x1f) + 1;
+       rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
+
+       return rate;
+}
+
+static const struct clk_ops clk_pll_ops = {
+       .recalc_rate = axxia_pllclk_recalc,
+};
+
+static struct clk *
+register_axxia_pllclk(struct device *dev, const char *name,
+                     const char *parent_name, void __iomem *regs)
+{
+       struct clk_init_data init;
+       struct axxia_pllclk *pll;
+       struct clk *clk;
+
+       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &clk_pll_ops;
+       init.flags = 0;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       pll->regs = regs;
+       pll->hw.init = &init;
+
+       clk = clk_register(NULL, &pll->hw);
+       if (IS_ERR(clk))
+               kfree(pll);
+
+       return clk;
+}
+
+
+/**
+ * struct axxia_divclk - Axxia clock divider
+ * @hw: clk_hw for the divider
+ * @regs: Pointer to control registers
+ */
+struct axxia_divclk {
+       struct clk_hw hw;
+       void __iomem *regs;
+       int shift;
+       int width;
+};
+
+#define to_axxia_divclk(_hw) container_of(_hw, struct axxia_divclk, hw)
+
+static unsigned long
+axxia_divclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+       struct axxia_divclk *divclk = to_axxia_divclk(hw);
+       u32 ctrl, div;
+
+       ctrl = readl(divclk->regs);
+       div = 1 + ((ctrl >> divclk->shift) & GENMASK(divclk->width-1, 0));
+
+       return parent_rate / div;
+}
+
+const struct clk_ops axxia_divclk_ops = {
+       .recalc_rate = axxia_divclk_recalc_rate,
+};
+
+static struct clk *
+register_axxia_divclk(struct device *dev, const char *name,
+                     const char *parent_name, void __iomem *regs,
+                     int shift, int width)
+{
+       struct axxia_divclk *div;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       div = kzalloc(sizeof(struct axxia_divclk), GFP_KERNEL);
+       if (!div)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &axxia_divclk_ops;
+       init.flags = CLK_IS_BASIC;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       div->regs = regs;
+       div->shift = shift;
+       div->width = width;
+       div->hw.init = &init;
+
+       /* register the clock */
+       clk = clk_register(dev, &div->hw);
+       if (IS_ERR(clk))
+               kfree(div);
+
+       return clk;
+}
+
+/**
+ * axxia_pll_clk_init - Axxia PLL clock setup function
+ * @node: pointer to device tree node
+ */
+static void __init
+axxia_pll_clk_init(struct device_node *node)
+{
+       struct clk *clk;
+       const char *parent_name;
+       void __iomem *regs;
+       const char *clk_name = node->name;
+
+       of_property_read_string(node, "clock-output-names", &clk_name);
+
+       parent_name = of_clk_get_parent_name(node, 0);
+       if (!parent_name) {
+               pr_err("%s: no parent clock\n", node->name);
+               return;
+       }
+
+       regs = of_iomap(node, 0);
+       if (!regs) {
+               pr_err("%s: failed to map register\n", node->name);
+               return;
+       }
+
+       clk = register_axxia_pllclk(NULL, clk_name, parent_name, regs);
+       if (IS_ERR(clk)) {
+               pr_err("%s: register failed (%ld)\n", clk_name, PTR_ERR(clk));
+               iounmap(regs);
+               return;
+       }
+
+       of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(axxia_pll_clk, "lsi,axxia-pll-clock", axxia_pll_clk_init);
+
+
+/**
+ * axxia_div_clk_init - Axxia clock divider setup function
+ * @node: device tree node for this clock
+ */
+static void __init
+axxia_div_clk_init(struct device_node *node)
+{
+       const char *parent_name;
+       void __iomem *reg;
+       u32 shift, width;
+       struct clk *clk;
+       const char *clk_name = node->name;
+
+       of_property_read_string(node, "clock-output-names", &clk_name);
+
+       parent_name = of_clk_get_parent_name(node, 0);
+       if (!parent_name) {
+               pr_err("%s: no parent clock\n", node->name);
+               return;
+       }
+
+       reg = parse_and_map_reg(node, &shift, &width);
+       if (!reg)
+               return;
+
+       clk = register_axxia_divclk(NULL, clk_name, parent_name, reg,
+                                   shift, width);
+       if (IS_ERR(clk)) {
+               pr_err("%s: register failed (%ld)\n", clk_name, PTR_ERR(clk));
+               iounmap(reg);
+               return;
+       }
+
+       of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(axxia_div_clk, "lsi,axxia-div-clock", axxia_div_clk_init);
+
+
+/**
+ * axxia_mux_clk_init - Clock mux setup function
+ * @node: device tree node for this clock
+ */
+static void __init
+axxia_mux_clk_init(struct device_node *node)
+{
+       void __iomem *reg;
+       struct clk *clk;
+       const char *parents[4];
+       int num_parents;
+       const char *clk_name = node->name;
+       u32 shift, width;
+       int i;
+
+       of_property_read_string(node, "clock-output-names", &clk_name);
+
+       for (i = 0; i < ARRAY_SIZE(parents); ++i) {
+               parents[i] = of_clk_get_parent_name(node, i);
+               if (!parents[i])
+                       break;
+       }
+       num_parents = i;
+
+       reg = parse_and_map_reg(node, &shift, &width);
+       if (!reg)
+               return;
+
+       clk = clk_register_mux(NULL, clk_name, parents,
+                              num_parents, 0, reg, shift, width,
+                              CLK_MUX_READ_ONLY, NULL);
+       if (IS_ERR(clk)) {
+               pr_err("%s: register failed (%ld)\n", clk_name, PTR_ERR(clk));
+               iounmap(reg);
+               return;
+       }
+
+       of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(pll_mux_clock, "lsi,axxia-mux-clock", axxia_mux_clk_init);
--

1.8.3.2

Add device tree for the Amarillo validation board with an AXM5516 SoC.

Signed-off-by Anders Berg <[email protected]>

arch/arm/boot/dts/axm55xx.dtsi new file +24 -0

+                       timer0: timer at 2010091000 {
+                               compatible = "arm,sp804", "arm,primecell";
+                               reg = <0x20 0x10091000 0 0x1000>;
+                               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk_per>;
+                               clock-names = "apb_pclk";
+                               status = "okay";
+                       };
+
+                       gpio0: gpio at 2010092000 {
+                               #gpio-cells = <2>;
+                               compatible = "arm,pl061", "arm,primecell";
+                               gpio-controller;
+                               reg = <0x20 0x10092000 0x00 0x1000>;
+                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

Quoted 3 lines · Anders Berg

Add device tree for the Amarillo validation board with an AXM5516 SoC.

Signed-off-by Anders Berg <[email protected]>

(...)

Quoted 24 lines

arch/arm/boot/dts/axm55xx.dtsi new file +24 -0

+                       timer0: timer at 2010091000 {
+                               compatible = "arm,sp804", "arm,primecell";
+                               reg = <0x20 0x10091000 0 0x1000>;
+                               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk_per>;
+                               clock-names = "apb_pclk";
+                               status = "okay";
+                       };
+
+                       gpio0: gpio at 2010092000 {
+                               #gpio-cells = <2>;
+                               compatible = "arm,pl061", "arm,primecell";
+                               gpio-controller;
+                               reg = <0x20 0x10092000 0x00 0x1000>;
+                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/axm55xx.dtsi line 286

Quoted 10 lines

arch/arm/boot/dts/axm55xx.dtsi new file +10 -0

+                                            <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk_per>;
+                               clock-names = "apb_pclk";
+                               status = "disabled";
+                       };

One interrupt per CPU core?

The drivers for these blocks will really just grab the first IRQ and then I guess they
will only be able to execute on CPU0.

It's definately correct to list all the IRQs here, but how do you envision the drivers making use of them in the long run?

Yours,
Linus Walleij

Quoted 6 lines · Linus Walleij

One interrupt per CPU core?

The drivers for these blocks will really just grab the first IRQ and then I guess they
will only be able to execute on CPU0.

Quoted 2 lines

It's definately correct to list all the IRQs here, but how do you envision the drivers making use of them in the long run?

It's one interrupt line per input pin (so with the current driver only the first pin is usable as interrupt source).

Quoted 11 lines · Anders Berg

Quoted 8 lines · Linus Walleij

One interrupt per CPU core?

The drivers for these blocks will really just grab the first IRQ and then I guess they
will only be able to execute on CPU0.

It's definately correct to list all the IRQs here, but how do you envision the drivers making use of them in the long run?

Quoted 2 lines

It's one interrupt line per input pin (so with the current driver only the first pin is usable as interrupt source).

Hm I'm not sure I understand what a "pin" is in this concept ... being maintainer of the pin control subsystem and all that really triggers my interest.

Yours.
Linus Walleij

Quoted 12 lines · Linus Walleij

Quoted 11 lines · Anders Berg

Quoted 8 lines · Linus Walleij

One interrupt per CPU core?

The drivers for these blocks will really just grab the first IRQ and then I guess they
will only be able to execute on CPU0.

It's definately correct to list all the IRQs here, but how do you envision the drivers making use of them in the long run?

Quoted 7 lines

Quoted 2 lines

It's one interrupt line per input pin (so with the current driver only the first pin is usable as interrupt source).

Hm I'm not sure I understand what a "pin" is in this concept ... being maintainer of the pin control subsystem and all that really triggers my interest.

Ok, maybe should replace "pin" with "GPIO" in my previous comment.

So, a clarification. In one of the PL061 blocks (named gpio0 in the dts) there is a separate interrupt per GPIO (I assume the motivation here is to enable to control irq affinity per GPIO), where as the other block has a more standard configuration with a single interrupt for all 8 GPIOs in that block.

This means that you can only get a proper, working IRQ from the first line on gpio0 right? All other IRQs will be ignored.

I see no problem in augmenting the driver to handle this if #irqs == 8, the big change needs to happen in drivers/amba/bus.c that has no way to pass any more than two IRQs atm.

I guess the best is to augment struct amba_device with a field struct resource *resource and num_resources like platform_device instead of the hard-coded single resource for iomem and two hardcoded IRQ placeholders, so that an arbitrary amount of resources can be added to an amba_device as well. But that may be quite a lot of work. (Russell will know which direction to take here.)

Quoted 23 lines · Anders Berg

Quoted 12 lines · Linus Walleij

Quoted 11 lines · Anders Berg

Quoted 8 lines · Linus Walleij

One interrupt per CPU core?

The drivers for these blocks will really just grab the first IRQ and then I guess they
will only be able to execute on CPU0.

It's definately correct to list all the IRQs here, but how do you envision the drivers making use of them in the long run?

Quoted 7 lines

Quoted 2 lines

It's one interrupt line per input pin (so with the current driver only the first pin is usable as interrupt source).

Hm I'm not sure I understand what a "pin" is in this concept ... being maintainer of the pin control subsystem and all that really triggers my interest.

Ok, maybe should replace "pin" with "GPIO" in my previous comment.

Quoted 4 lines

So, a clarification. In one of the PL061 blocks (named gpio0 in the dts) there is a separate interrupt per GPIO (I assume the motivation here is to enable to control irq affinity per GPIO), where as the other block has a more standard configuration with a single interrupt for all 8 GPIOs in that block.

OK! I get it. Thus this is not a stock PL061, but a version modified to generate a separate IRQ line per GPIO line.

This means that you can only get a proper, working IRQ from the first line on gpio0 right? All other IRQs will be ignored.

Hi,

Verion 2 of this series to introduces basic platform support for the LSI AXM5516 SoC. When this is in shape, could it be merged into the arm-soc tree?

Changes:

v2:
* Rebased to arm-soc/for-next
* Removed redundant HAVE_SMP and ARCH_WANT_OPTIONAL_GPIOLIB from Kconfig
* Use CPU_METHOD_OF_DECLARE to register smp_operations
* Rework smp operations to avoid holding pen and custom headsmp.S
* Clean up board file
* Corrected clock properties for arm,sp804 dts node.
* Changed machine compatible strings to include full model number.
* Break out clk-axxia driver as separate patch
* Removed Makefile.boot

Anders Berg (6):
ARM: Add platform support for LSI AXM55xx SoC
clk: Add clock driver for AXM55xx SoC
ARM: dts: Device tree for AXM55xx.
ARM: axxia: Adding defconfig for AXM55xx
power: reset: Add Axxia system reset driver
ARM: dts: axxia: Add reset controller

 Documentation/devicetree/bindings/arm/axxia.txt    |  12 +
 .../devicetree/bindings/clock/clk-axxia.txt        |  88 ++++++
 .../bindings/power_supply/axxia-reset.txt          |  20 ++
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Makefile                                  |   2 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/axm5516-amarillo.dts             |  51 ++++
 arch/arm/boot/dts/axm5516-cpus.dtsi                | 204 ++++++++++++++
 arch/arm/boot/dts/axm55xx.dtsi                     | 311 +++++++++++++++++++++
 arch/arm/configs/axm55xx_defconfig                 | 248 ++++++++++++++++
 arch/arm/mach-axxia/Kconfig                        |  16 ++
 arch/arm/mach-axxia/Makefile                       |   2 +
 arch/arm/mach-axxia/axxia.c                        |  28 ++
 arch/arm/mach-axxia/platsmp.c                      |  89 ++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-axxia.c                            | 281 +++++++++++++++++++
 drivers/power/reset/Kconfig                        |   8 +
 drivers/power/reset/Makefile                       |   1 +
 drivers/power/reset/axxia-reset.c                  |  97 +++++++
 19 files changed, 1462 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/axxia.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-axxia.txt
 create mode 100644 Documentation/devicetree/bindings/power_supply/axxia-reset.txt
 create mode 100644 arch/arm/boot/dts/axm5516-amarillo.dts
 create mode 100644 arch/arm/boot/dts/axm5516-cpus.dtsi
 create mode 100644 arch/arm/boot/dts/axm55xx.dtsi
 create mode 100644 arch/arm/configs/axm55xx_defconfig
 create mode 100644 arch/arm/mach-axxia/Kconfig
 create mode 100644 arch/arm/mach-axxia/Makefile
 create mode 100644 arch/arm/mach-axxia/axxia.c
 create mode 100644 arch/arm/mach-axxia/platsmp.c
 create mode 100644 drivers/clk/clk-axxia.c
 create mode 100644 drivers/power/reset/axxia-reset.c

Signature · 1 line

1.8.3.2

Hi Anrd,

Any comments on this updated series?