Broadcom XLP changes for 3.16

PATCH In review Jayachandran C 2 participants 25 messages Apr 29, 2014 – May 9, 2014 MIPS

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Jayachandran C

author

2014-04-29 14:31 UTC #0 lore raw

cover Broadcom XLP changes for 3.16

The changes in the patchset are:
* add support for the on chip SATA interfaces of XLP and XLPII
* add MSI/MSIX support for the XLP9xx processors
* add support for the new XLP5xx processors
* update frequency calculation logic for core and PIC
* many fixes and improvements

Patch 01/17 is to support upto 256 CPUs on mips, which is needed for multi-node XLP9xx configuration. The rest of the changes are to Broadcom XLR/XLP specific code.

This is for 3.16, please let me know if there are any comments.

Thanks,
JC.

Ganesan Ramalingam (4):
MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XX
MIPS: Add MSI support for XLP9XX
MIPS: Netlogic: Support for XLP3XX on-chip SATA
MIPS: Netlogic: XLP9XX on-chip SATA support

Jayachandran C (12):
MIPS: Support upto 256 CPUs
MIPS: Netlogic: Fix uniprocessor compilation
MIPS: Netlogic: Move coremask setup to nlm_node_init
MIPS: Netlogic: Warn on invalid irq
MIPS: Netlogic: Update function to read DRAM BARs
MIPS: Netlogic: Use cpumask_scnprintf for wakup_mask
MIPS: Netlogic: Reduce size of reset code
MIPS: Netlogic: Enable access to more than 64GB
MIPS: Netlogic: IRQ mapping for some more SoC blocks
MIPS: Netlogic: Use PRID_IMP_MASK macro
MIPS: Netlogic: Fix XLP9XX pic entry
MIPS: Netlogic: Update XLP9XX/2XX core freq calculation

Yonghong Song (1):
MIPS: Netlogic: Add support for XLP5XX

 arch/mips/Kconfig                               |    4 +-
 arch/mips/include/asm/cpu.h                     |    1 +
 arch/mips/include/asm/mach-netlogic/topology.h  |    2 +
 arch/mips/include/asm/netlogic/mips-extns.h     |    5 +-
 arch/mips/include/asm/netlogic/xlp-hal/iomap.h  |   18 +-
 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h |   14 +
 arch/mips/include/asm/netlogic/xlp-hal/pic.h    |    4 +
 arch/mips/include/asm/netlogic/xlp-hal/sys.h    |   35 +++
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h    |   21 +-
 arch/mips/kernel/cpu-probe.c                    |    1 +
 arch/mips/netlogic/common/irq.c                 |    2 +
 arch/mips/netlogic/common/reset.S               |   39 ++-
 arch/mips/netlogic/common/smp.c                 |    7 +-
 arch/mips/netlogic/common/smpboot.S             |    6 +-
 arch/mips/netlogic/common/time.c                |    5 +-
 arch/mips/netlogic/dts/xlp_gvp.dts              |    5 +-
 arch/mips/netlogic/xlp/Makefile                 |    2 +
 arch/mips/netlogic/xlp/ahci-init-xlp2.c         |  378 +++++++++++++++++++++++
 arch/mips/netlogic/xlp/ahci-init.c              |  209 +++++++++++++
 arch/mips/netlogic/xlp/dt.c                     |    3 +-
 arch/mips/netlogic/xlp/nlm_hal.c                |  295 +++++++++++++-----
 arch/mips/netlogic/xlp/setup.c                  |    5 +-
 arch/mips/netlogic/xlp/wakeup.c                 |   16 +-
 arch/mips/pci/msi-xlp.c                         |  178 ++++++++---
 24 files changed, 1079 insertions(+), 176 deletions(-)
 create mode 100644 arch/mips/netlogic/xlp/ahci-init-xlp2.c
 create mode 100644 arch/mips/netlogic/xlp/ahci-init.c

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:31 UTC #1 lore raw

PATCH 1/17 MIPS: Support upto 256 CPUs

This is needed for two node XLP9xx configurations.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/Kconfig |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/mips/Kconfig +2 -2

index a91f688..d0bcfce 100644
@@ -2297,8 +2297,8 @@ config NR_CPUS_DEFAULT_64
 	bool
 
 config NR_CPUS
-	int "Maximum number of CPUs (2-64)"
-	range 2 64
+	int "Maximum number of CPUs (2-256)"
+	range 2 256
 	depends on SMP
 	default "4" if NR_CPUS_DEFAULT_4
 	default "8" if NR_CPUS_DEFAULT_8

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:31 UTC #2 lore raw

PATCH 2/17 MIPS: Netlogic: Fix uniprocessor compilation

In reply to Jayachandran C

The macros in topology.h need CONFIG_SMP, and the uniprocessor compilation fails due to this. Wrap the macros in an ifdef so that uniprocessor works.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/mach-netlogic/topology.h |    2 ++
 1 file changed, 2 insertions(+)

arch/mips/include/asm/mach-netlogic/topology.h +2 -0

index 0da99fa..ceeb1f5 100644
@@ -10,10 +10,12 @@
 
 #include <asm/mach-netlogic/multi-node.h>
 
+#ifdef CONFIG_SMP
 #define topology_physical_package_id(cpu)	cpu_to_node(cpu)
 #define topology_core_id(cpu)	(cpu_logical_map(cpu) / NLM_THREADS_PER_CORE)
 #define topology_thread_cpumask(cpu)		(&cpu_sibling_map[cpu])
 #define topology_core_cpumask(cpu)	cpumask_of_node(cpu_to_node(cpu))
+#endif
 
 #include <asm-generic/topology.h>

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:31 UTC #3 lore raw

PATCH 3/17 MIPS: Netlogic: Move coremask setup to nlm_node_init

In reply to Jayachandran C

This is needed for nlm_node_present(0) to work on uniprocessor compile.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/xlp/nlm_hal.c |    2 ++
 arch/mips/netlogic/xlp/wakeup.c  |    4 ----
 2 files changed, 2 insertions(+), 4 deletions(-)

arch/mips/netlogic/xlp/nlm_hal.c +2 -0

index 997cd9e..7b277cd 100644
@@ -54,6 +54,8 @@ void nlm_node_init(int node)
 	struct nlm_soc_info *nodep;
 
 	nodep = nlm_get_node(node);
+	if (node == 0)
+		nodep->coremask = 1;	/* node 0, boot cpu */
 	nodep->sysbase = nlm_get_sys_regbase(node);
 	nodep->picbase = nlm_get_pic_regbase(node);
 	nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));

arch/mips/netlogic/xlp/wakeup.c +0 -4

index 9a92617..7589238 100644
@@ -159,10 +159,6 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 		 */
 		syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
 
-		/* The boot cpu */
-		if (n == 0)
-			nodep->coremask = 1;
-
 		pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
 		for (core = 0; core < nlm_cores_per_node(); core++) {
 			/* we will be on node 0 core 0 */

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:31 UTC #4 lore raw

PATCH 4/17 MIPS: Netlogic: Warn on invalid irq

In reply to Jayachandran C

Warn and return if invalid IRQ is passed to nlm_set_pic_extra_ack.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/common/irq.c |    2 ++
 1 file changed, 2 insertions(+)

arch/mips/netlogic/common/irq.c +2 -0

index 5afc4b7..c100b9a 100644
@@ -203,6 +203,8 @@ void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
 
 	xirq = nlm_irq_to_xirq(node, irq);
 	pic_data = irq_get_handler_data(xirq);
+	if (WARN_ON(!pic_data))
+		return;
 	pic_data->extra_ack = xack;
 }

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:31 UTC #5 lore raw

PATCH 5/17 MIPS: Netlogic: Update function to read DRAM BARs

In reply to Jayachandran C

Change name of xlp_get_dram_map to nlm_get_dram_map to be consistent with the rest of the functions in the file. Pass the the size of the array 'dram_map' to the function, and ensure that it does not write past the end of the array.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h |    2 +-
 arch/mips/netlogic/xlp/nlm_hal.c             |   12 +++++++-----
 arch/mips/netlogic/xlp/setup.c               |    2 +-
 3 files changed, 9 insertions(+), 7 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +1 -1

index 2b0c959..1b56bd4 100644
@@ -84,7 +84,7 @@ void xlp_wakeup_secondary_cpus(void);
 
 void xlp_mmu_init(void);
 void nlm_hal_init(void);
-int xlp_get_dram_map(int n, uint64_t *dram_map);
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries);
 
 struct pci_dev;
 int xlp_socdev_to_node(const struct pci_dev *dev);

arch/mips/netlogic/xlp/nlm_hal.c +7 -5

index 7b277cd..d85019b 100644
@@ -319,19 +319,21 @@ unsigned int nlm_get_cpu_frequency(void)
 
 /*
  * Fills upto 8 pairs of entries containing the DRAM map of a node
- * if n < 0, get dram map for all nodes
+ * if node < 0, get dram map for all nodes
  */
-int xlp_get_dram_map(int n, uint64_t *dram_map)
+int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries)
 {
 	uint64_t bridgebase, base, lim;
 	uint32_t val;
 	unsigned int barreg, limreg, xlatreg;
-	int i, node, rv;
+	int i, n, rv;
 
 	/* Look only at mapping on Node 0, we don't handle crazy configs */
 	bridgebase = nlm_get_bridge_regbase(0);
 	rv = 0;
 	for (i = 0; i < 8; i++) {
+		if (rv + 1 >= nentries)
+			break;
 		if (cpu_is_xlp9xx()) {
 			barreg = BRIDGE_9XX_DRAM_BAR(i);
 			limreg = BRIDGE_9XX_DRAM_LIMIT(i);

@@ -341,10 +343,10 @@ int xlp_get_dram_map(int n, uint64_t *dram_map)
 			limreg = BRIDGE_DRAM_LIMIT(i);
 			xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
 		}
-		if (n >= 0) {
+		if (node >= 0) {
 			/* node specified, get node mapping of BAR */
 			val = nlm_read_bridge_reg(bridgebase, xlatreg);
-			node = (val >> 1) & 0x3;
+			n = (val >> 1) & 0x3;
 			if (n != node)
 				continue;
 		}

arch/mips/netlogic/xlp/setup.c +1 -1

index 8c60a2d..d1c9e88 100644
@@ -82,7 +82,7 @@ static void __init xlp_init_mem_from_bars(void)
 	uint64_t map[16];
 	int i, n;
 
-	n = xlp_get_dram_map(-1, map);	/* -1: info for all nodes */
+	n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map));	/* -1 : all nodes */
 	for (i = 0; i < n; i += 2) {
 		/* exclude 0x1000_0000-0x2000_0000, u-boot device */
 		if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:31 UTC #6 lore raw

PATCH 6/17 MIPS: Netlogic: Use cpumask_scnprintf for wakup_mask

In reply to Jayachandran C

Use standard function to print cpumask. Also fixup a typo in the same file.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/common/smp.c |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

arch/mips/netlogic/common/smp.c +4 -3

index 6baae15..b93c5d4 100644
@@ -198,7 +198,7 @@ void __init nlm_smp_setup(void)
 	cpumask_scnprintf(buf, ARRAY_SIZE(buf), cpu_possible_mask);
 	pr_info("Possible CPU mask: %s\n", buf);
 
-	/* check with the cores we have worken up */
+	/* check with the cores we have woken up */
 	for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
 		ncore += hweight32(nlm_get_node(i)->coremask);

@@ -213,6 +213,7 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
 {
 	uint32_t core0_thr_mask, core_thr_mask;
 	int threadmode, i, j;
+	char buf[64];
 
 	core0_thr_mask = 0;
 	for (i = 0; i < NLM_THREADS_PER_CORE; i++)

@@ -247,8 +248,8 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
 	return threadmode;
 
 unsupp:
-	panic("Unsupported CPU mask %lx",
-		(unsigned long)cpumask_bits(wakeup_mask)[0]);
+	cpumask_scnprintf(buf, ARRAY_SIZE(buf), wakeup_mask);
+	panic("Unsupported CPU mask %s", buf);
 	return 0;
 }

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-05-09 10:58 UTC #7 lore raw

PATCH v2 6/17 MIPS: Netlogic: Use cpumask_scnprintf for wakeup_mask

Use standard function to print cpumask. Also fixup a typo in the same file.

Signed-off-by Jayachandran C <[email protected]>

---
[v2: Fix subject line for patch]

 arch/mips/netlogic/common/smp.c |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

arch/mips/netlogic/common/smp.c +4 -3

index 6baae15..b93c5d4 100644
@@ -198,7 +198,7 @@ void __init nlm_smp_setup(void)
 	cpumask_scnprintf(buf, ARRAY_SIZE(buf), cpu_possible_mask);
 	pr_info("Possible CPU mask: %s\n", buf);
 
-	/* check with the cores we have worken up */
+	/* check with the cores we have woken up */
 	for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
 		ncore += hweight32(nlm_get_node(i)->coremask);

@@ -213,6 +213,7 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
 {
 	uint32_t core0_thr_mask, core_thr_mask;
 	int threadmode, i, j;
+	char buf[64];
 
 	core0_thr_mask = 0;
 	for (i = 0; i < NLM_THREADS_PER_CORE; i++)

@@ -247,8 +248,8 @@ static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
 	return threadmode;
 
 unsupp:
-	panic("Unsupported CPU mask %lx",
-		(unsigned long)cpumask_bits(wakeup_mask)[0]);
+	cpumask_scnprintf(buf, ARRAY_SIZE(buf), wakeup_mask);
+	panic("Unsupported CPU mask %s", buf);
 	return 0;
 }

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:32 UTC #8 lore raw

PATCH 7/17 MIPS: Netlogic: Reduce size of reset code

In reply to Jayachandran C

Update thread wakeup function to use scratch registers for saving SP and RA. Move the register restore code needed for thread 0 to the calling function. This reduces the size of code copied to the reset vector.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/common/reset.S   |   15 ++++++++-------
 arch/mips/netlogic/common/smpboot.S |    6 ++++--
 2 files changed, 12 insertions(+), 9 deletions(-)

arch/mips/netlogic/common/reset.S +8 -7

index b231fe1..fda772a 100644
@@ -197,6 +197,9 @@ FEXPORT(nlm_reset_entry)
 EXPORT(nlm_boot_siblings)
 	/* core L1D flush before enable threads */
 	xlp_flush_l1_dcache
+	/* save ra and sp, will be used later (only for boot cpu) */
+	dmtc0	ra, $22, 6
+	dmtc0	sp, $22, 7
 	/* Enable hw threads by writing to MAP_THREADMODE of the core */
 	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)
 	lw	t1, BOOT_THREAD_MODE(t0)	/* t1 <- thread mode */

@@ -238,14 +241,12 @@ EXPORT(nlm_boot_siblings)
 	nop
 
 	/*
-	 * For the boot CPU, we have to restore registers and
-	 * return
+	 * For the boot CPU, we have to restore ra and sp and return, rest
+	 * of the registers will be restored by the caller
 	 */
-4:	dmfc0	t0, $4, 2	/* restore SP from UserLocal */
-	li	t1, 0xfadebeef
-	dmtc0	t1, $4, 2	/* restore SP from UserLocal */
-	PTR_SUBU sp, t0, PT_SIZE
-	RESTORE_ALL
+4:
+	dmfc0	ra, $22, 6
+	dmfc0	sp, $22, 7
 	jr	ra
 	nop
 EXPORT(nlm_reset_entry_end)

arch/mips/netlogic/common/smpboot.S +4 -2

index 8597657..d9b456b 100644
@@ -55,7 +55,6 @@
 	.set	arch=xlr		/* for mfcr/mtcr, XLR is sufficient */
 
 FEXPORT(xlp_boot_core0_siblings)	/* "Master" cpu starts from here */
-	dmtc0	sp, $4, 2		/* SP saved in UserLocal */
 	SAVE_ALL
 	sync
 	/* find the location to which nlm_boot_siblings was relocated */

@@ -65,7 +64,10 @@ FEXPORT(xlp_boot_core0_siblings)	/* "Master" cpu starts from here */
 	dsubu	t2, t1
 	daddu	t2, t0
 	/* call it */
-	jr	t2
+	jalr	t2
+	nop
+	RESTORE_ALL
+	jr	ra
 	nop
 	/* not reached */

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-05-09 10:58 UTC #9 lore raw

PATCH v2 7/17 MIPS: Netlogic: Reduce size of reset code

Signed-off-by Jayachandran C <[email protected]>

---
[v2: Use proper function macros for xlp_boot_core0_siblings]

 arch/mips/netlogic/common/reset.S   |   15 ++++++++-------
 arch/mips/netlogic/common/smpboot.S |   12 ++++++++----
 2 files changed, 16 insertions(+), 11 deletions(-)

arch/mips/netlogic/common/reset.S +8 -7

index b231fe1..fda772a 100644
@@ -197,6 +197,9 @@ FEXPORT(nlm_reset_entry)
 EXPORT(nlm_boot_siblings)
 	/* core L1D flush before enable threads */
 	xlp_flush_l1_dcache
+	/* save ra and sp, will be used later (only for boot cpu) */
+	dmtc0	ra, $22, 6
+	dmtc0	sp, $22, 7
 	/* Enable hw threads by writing to MAP_THREADMODE of the core */
 	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)
 	lw	t1, BOOT_THREAD_MODE(t0)	/* t1 <- thread mode */

@@ -238,14 +241,12 @@ EXPORT(nlm_boot_siblings)
 	nop
 
 	/*
-	 * For the boot CPU, we have to restore registers and
-	 * return
+	 * For the boot CPU, we have to restore ra and sp and return, rest
+	 * of the registers will be restored by the caller
 	 */
-4:	dmfc0	t0, $4, 2	/* restore SP from UserLocal */
-	li	t1, 0xfadebeef
-	dmtc0	t1, $4, 2	/* restore SP from UserLocal */
-	PTR_SUBU sp, t0, PT_SIZE
-	RESTORE_ALL
+4:
+	dmfc0	ra, $22, 6
+	dmfc0	sp, $22, 7
 	jr	ra
 	nop
 EXPORT(nlm_reset_entry_end)

arch/mips/netlogic/common/smpboot.S +8 -4

index 8597657..805355b 100644
@@ -54,8 +54,9 @@
 	.set	noat
 	.set	arch=xlr		/* for mfcr/mtcr, XLR is sufficient */
 
-FEXPORT(xlp_boot_core0_siblings)	/* "Master" cpu starts from here */
-	dmtc0	sp, $4, 2		/* SP saved in UserLocal */
+/* Called by the boot cpu to wake up its sibling threads */
+NESTED(xlp_boot_core0_siblings, PT_SIZE, sp)
+	/* CPU register contents lost when enabling threads, save them first */
 	SAVE_ALL
 	sync
 	/* find the location to which nlm_boot_siblings was relocated */

@@ -65,9 +66,12 @@ FEXPORT(xlp_boot_core0_siblings)	/* "Master" cpu starts from here */
 	dsubu	t2, t1
 	daddu	t2, t0
 	/* call it */
-	jr	t2
+	jalr	t2
 	nop
-	/* not reached */
+	RESTORE_ALL
+	jr	ra
+	nop
+END(xlp_boot_core0_siblings)
 
 NESTED(nlm_boot_secondary_cpus, 16, sp)
 	/* Initialize CP0 Status */

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:31 UTC #10 lore raw

PATCH 8/17 MIPS: Netlogic: Enable access to more than 64GB

In reply to Jayachandran C

The ELPA bit needs to be set in the PAGEGRAIN register to enable access to >64GB physical address. Update reset.S to do this from every hardware thread.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/common/reset.S |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/mips/netlogic/common/reset.S +15 -0

index fda772a..13c1bc5 100644
@@ -74,6 +74,18 @@
 .endm
 
 /*
+ * Allow access to physical mem >64G by enabling ELPA in PAGEGRAIN
+ * register. This is needed before going to C code since the SP can
+ * in this region. Called from all HW threads.
+ */
+.macro xlp_early_mmu_init
+	mfc0	t0, CP0_PAGEMASK, 1
+	li	t1, (1 << 29)		/* ELPA bit */
+	or	t0, t1
+	mtc0	t0, CP0_PAGEMASK, 1
+.endm
+
+/*
  * L1D cache has to be flushed before enabling threads in XLP.
  * On XLP8xx/XLP3xx, we do a low level flush using processor control
  * registers. On XLPII CPUs, usual cache instructions work.

@@ -228,6 +240,8 @@ EXPORT(nlm_boot_siblings)
 #endif
 	mtc0	t1, CP0_STATUS
 
+	xlp_early_mmu_init
+
 	/* mark CPU ready */
 	li	t3, CKSEG1ADDR(RESET_DATA_PHYS)
 	ADDIU	t1, t3, BOOT_CPU_READY

@@ -254,6 +268,7 @@ EXPORT(nlm_reset_entry_end)
 LEAF(nlm_init_boot_cpu)
 #ifdef CONFIG_CPU_XLP
 	xlp_config_lsu
+	xlp_early_mmu_init
 #endif
 	jr	ra
 	nop

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:32 UTC #11 lore raw

PATCH 9/17 MIPS: Netlogic: IRQ mapping for some more SoC blocks

In reply to Jayachandran C

Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add device IDs for a few blocks.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/iomap.h |   16 +++--
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h   |    4 ++
 arch/mips/netlogic/xlp/nlm_hal.c               |   84 ++++++++++++++++--------
 3 files changed, 69 insertions(+), 35 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/iomap.h +9 -7

index 1f23dfa..14b2f51 100644
@@ -74,6 +74,8 @@
 #define XLP_IO_USB_OHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 4)
 #define XLP_IO_USB_OHCI3_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 5)
 
+#define XLP_IO_SATA_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 3, 2)
+
 /* XLP2xx has an updated USB block */
 #define XLP2XX_IO_USB_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 4, i)
 #define XLP2XX_IO_USB_XHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 1)

@@ -103,13 +105,11 @@
 #define XLP_IO_SYS_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 6, 5)
 #define XLP_IO_JTAG_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 6)
 
+/* Flash */
 #define XLP_IO_NOR_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 0)
 #define XLP_IO_NAND_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 7, 1)
 #define XLP_IO_SPI_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 2)
-/* SD flash */
-#define XLP_IO_SD_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 3)
-#define XLP_IO_MMC_OFFSET(node, slot)	\
-		((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
+#define XLP_IO_MMC_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 3)
 
 /* Things have changed drastically in XLP 9XX */
 #define XLP9XX_HDR_OFFSET(n, d, f)	\

@@ -135,11 +135,11 @@
 /* XLP9XX on-chip SATA controller */
 #define XLP9XX_IO_SATA_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 3, 2)
 
+/* Flash */
 #define XLP9XX_IO_NOR_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 0)
 #define XLP9XX_IO_NAND_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 1)
 #define XLP9XX_IO_SPI_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 2)
-/* SD flash */
-#define XLP9XX_IO_MMCSD_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 3)
+#define XLP9XX_IO_MMC_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 3)
 
 /* PCI config header register id's */
 #define XLP_PCI_CFGREG0			0x00

@@ -186,8 +186,10 @@
 #define PCI_DEVICE_ID_NLM_NOR		0x1015
 #define PCI_DEVICE_ID_NLM_NAND		0x1016
 #define PCI_DEVICE_ID_NLM_MMC		0x1018
-#define PCI_DEVICE_ID_NLM_XHCI		0x101d
+#define PCI_DEVICE_ID_NLM_SATA		0x101A
+#define PCI_DEVICE_ID_NLM_XHCI		0x101D
 
+#define PCI_DEVICE_ID_XLP9XX_MMC	0x9018
 #define PCI_DEVICE_ID_XLP9XX_SATA	0x901A
 #define PCI_DEVICE_ID_XLP9XX_XHCI	0x901D

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +4 -0

index 1b56bd4..488863e 100644
@@ -58,6 +58,10 @@
 #define PIC_I2C_1_IRQ			31
 #define PIC_I2C_2_IRQ			32
 #define PIC_I2C_3_IRQ			33
+#define PIC_SPI_IRQ			34
+#define PIC_NAND_IRQ			37
+#define PIC_SATA_IRQ			38
+#define PIC_GPIO_IRQ			39
 
 #define PIC_PCIE_LINK_MSI_IRQ_BASE	44	/* 44 - 47 MSI IRQ */
 #define PIC_PCIE_LINK_MSI_IRQ(i)	(44 + (i))

arch/mips/netlogic/xlp/nlm_hal.c +56 ~~-28~~

118 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-05-09 10:58 UTC #12 lore raw

PATCH v2 9/17 MIPS: Netlogic: IRQ mapping for some more SoC blocks

Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add device IDs for a few blocks.

Signed-off-by Jayachandran C <[email protected]>

---
[v2: Fix GPIO irq]

 arch/mips/include/asm/netlogic/xlp-hal/iomap.h |   16 +++--
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h   |    4 ++
 arch/mips/netlogic/xlp/nlm_hal.c               |   84 ++++++++++++++++--------
 3 files changed, 69 insertions(+), 35 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/iomap.h +9 -7

index 1f23dfa..14b2f51 100644
@@ -74,6 +74,8 @@
 #define XLP_IO_USB_OHCI2_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 4)
 #define XLP_IO_USB_OHCI3_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 2, 5)
 
+#define XLP_IO_SATA_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 3, 2)
+
 /* XLP2xx has an updated USB block */
 #define XLP2XX_IO_USB_OFFSET(node, i)	XLP_HDR_OFFSET(node, 0, 4, i)
 #define XLP2XX_IO_USB_XHCI0_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 4, 1)

@@ -103,13 +105,11 @@
 #define XLP_IO_SYS_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 6, 5)
 #define XLP_IO_JTAG_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 6, 6)
 
+/* Flash */
 #define XLP_IO_NOR_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 0)
 #define XLP_IO_NAND_OFFSET(node)	XLP_HDR_OFFSET(node, 0, 7, 1)
 #define XLP_IO_SPI_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 2)
-/* SD flash */
-#define XLP_IO_SD_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 3)
-#define XLP_IO_MMC_OFFSET(node, slot)	\
-		((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
+#define XLP_IO_MMC_OFFSET(node)		XLP_HDR_OFFSET(node, 0, 7, 3)
 
 /* Things have changed drastically in XLP 9XX */
 #define XLP9XX_HDR_OFFSET(n, d, f)	\

@@ -135,11 +135,11 @@
 /* XLP9XX on-chip SATA controller */
 #define XLP9XX_IO_SATA_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 3, 2)
 
+/* Flash */
 #define XLP9XX_IO_NOR_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 0)
 #define XLP9XX_IO_NAND_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 1)
 #define XLP9XX_IO_SPI_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 2)
-/* SD flash */
-#define XLP9XX_IO_MMCSD_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 3)
+#define XLP9XX_IO_MMC_OFFSET(node)		XLP9XX_HDR_OFFSET(node, 7, 3)
 
 /* PCI config header register id's */
 #define XLP_PCI_CFGREG0			0x00

@@ -186,8 +186,10 @@
 #define PCI_DEVICE_ID_NLM_NOR		0x1015
 #define PCI_DEVICE_ID_NLM_NAND		0x1016
 #define PCI_DEVICE_ID_NLM_MMC		0x1018
-#define PCI_DEVICE_ID_NLM_XHCI		0x101d
+#define PCI_DEVICE_ID_NLM_SATA		0x101A
+#define PCI_DEVICE_ID_NLM_XHCI		0x101D
 
+#define PCI_DEVICE_ID_XLP9XX_MMC	0x9018
 #define PCI_DEVICE_ID_XLP9XX_SATA	0x901A
 #define PCI_DEVICE_ID_XLP9XX_XHCI	0x901D

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +4 -0

index 1b56bd4..488863e 100644
@@ -58,6 +58,10 @@
 #define PIC_I2C_1_IRQ			31
 #define PIC_I2C_2_IRQ			32
 #define PIC_I2C_3_IRQ			33
+#define PIC_SPI_IRQ			34
+#define PIC_NAND_IRQ			37
+#define PIC_SATA_IRQ			38
+#define PIC_GPIO_IRQ			39
 
 #define PIC_PCIE_LINK_MSI_IRQ_BASE	44	/* 44 - 47 MSI IRQ */
 #define PIC_PCIE_LINK_MSI_IRQ(i)	(44 + (i))

arch/mips/netlogic/xlp/nlm_hal.c +56 ~~-28~~

118 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:32 UTC #13 lore raw

PATCH 10/17 MIPS: Netlogic: Use PRID_IMP_MASK macro

In reply to Jayachandran C

Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor type.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/mips-extns.h  |    4 ++--
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h |    4 ++--
 arch/mips/netlogic/common/reset.S            |    5 +++--
 arch/mips/netlogic/xlp/dt.c                  |    2 +-
 arch/mips/netlogic/xlp/setup.c               |    2 +-
 arch/mips/netlogic/xlp/wakeup.c              |    2 +-
 6 files changed, 10 insertions(+), 9 deletions(-)

arch/mips/include/asm/netlogic/mips-extns.h +2 -2

index de9aada..38af905 100644
@@ -146,9 +146,9 @@ static inline int hard_smp_processor_id(void)
 
 static inline int nlm_nodeid(void)
 {
-	uint32_t prid = read_c0_prid();
+	uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
 
-	if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX)
+	if (prid == PRID_IMP_NETLOGIC_XLP9XX)
 		return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
 	else
 		return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +2 -2

index 488863e..f75014c 100644
@@ -99,7 +99,7 @@ void *xlp_dt_init(void *fdtp);
 
 static inline int cpu_is_xlpii(void)
 {
-	int chip = read_c0_prid() & 0xff00;
+	int chip = read_c0_prid() & PRID_IMP_MASK;
 
 	return chip == PRID_IMP_NETLOGIC_XLP2XX ||
 		chip == PRID_IMP_NETLOGIC_XLP9XX;

@@ -107,7 +107,7 @@ static inline int cpu_is_xlpii(void)
 
 static inline int cpu_is_xlp9xx(void)
 {
-	int chip = read_c0_prid() & 0xff00;
+	int chip = read_c0_prid() & PRID_IMP_MASK;
 
 	return chip == PRID_IMP_NETLOGIC_XLP9XX;
 }

arch/mips/netlogic/common/reset.S +3 -2

index 13c1bc5..5b60b46 100644
@@ -35,6 +35,7 @@
 
 #include <asm/asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/cpu.h>
 #include <asm/cacheops.h>
 #include <asm/regdef.h>
 #include <asm/mipsregs.h>

@@ -92,7 +93,7 @@
  */
 .macro	xlp_flush_l1_dcache
 	mfc0	t0, CP0_EBASE, 0
-	andi	t0, t0, 0xff00
+	andi	t0, t0, PRID_IMP_MASK
 	slt	t1, t0, 0x1200
 	beqz	t1, 15f
 	nop

@@ -171,7 +172,7 @@ FEXPORT(nlm_reset_entry)
 
 1:	/* Entry point on core wakeup */
 	mfc0	t0, CP0_EBASE, 0	/* processor ID */
-	andi	t0, 0xff00
+	andi	t0, PRID_IMP_MASK
 	li	t1, 0x1500		/* XLP 9xx */
 	beq	t0, t1, 2f		/* does not need to set coherent */
 	nop

arch/mips/netlogic/xlp/dt.c +1 -1

index 5754097..0b36ac8 100644
@@ -48,7 +48,7 @@ static void *xlp_fdt_blob;
 void __init *xlp_dt_init(void *fdtp)
 {
 	if (!fdtp) {
-		switch (current_cpu_data.processor_id & 0xff00) {
+		switch (current_cpu_data.processor_id & PRID_IMP_MASK) {
 #ifdef CONFIG_DT_XLP_GVP
 		case PRID_IMP_NETLOGIC_XLP9XX:
 			fdtp = __dtb_xlp_gvp_begin;

arch/mips/netlogic/xlp/setup.c +1 -1

index d1c9e88..3455e9f 100644
@@ -121,7 +121,7 @@ void __init plat_mem_setup(void)
 
 const char *get_system_type(void)
 {
-	switch (read_c0_prid() & 0xff00) {
+	switch (read_c0_prid() & PRID_IMP_MASK) {
 	case PRID_IMP_NETLOGIC_XLP9XX:
 	case PRID_IMP_NETLOGIC_XLP2XX:
 		return "Broadcom XLPII Series";

arch/mips/netlogic/xlp/wakeup.c +1 -1

index 7589238..f4823ad 100644
@@ -139,7 +139,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 		} else {
 			fusemask = nlm_read_sys_reg(nodep->sysbase,
 						SYS_EFUSE_DEVICE_CFG_STATUS0);
-			switch (read_c0_prid() & 0xff00) {
+			switch (read_c0_prid() & PRID_IMP_MASK) {
 			case PRID_IMP_NETLOGIC_XLP3XX:
 				mask = 0xf;
 				break;

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:32 UTC #14 lore raw

PATCH 11/17 MIPS: Netlogic: Fix XLP9XX pic entry

In reply to Jayachandran C

Add the compatible property to the PIC entry. Also fix up the nodename to use the correct address.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/dts/xlp_gvp.dts |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/mips/netlogic/dts/xlp_gvp.dts +3 -2

index 047d27f..bb4ecd1 100644
@@ -26,11 +26,12 @@
 			interrupt-parent = <&pic>;
 			interrupts = <17>;
 		};
-		pic: pic@4000 {
-			interrupt-controller;
+		pic: pic@110000 {
+			compatible = "netlogic,xlp-pic";
 			#address-cells = <0>;
 			#interrupt-cells = <1>;
 			reg = <0 0x110000 0x200>;
+			interrupt-controller;
 		};
 
 		nor_flash@1,0 {

Signature · 1 line

1.7.9.5

Sergei Shtylyov

2014-04-29 17:36 UTC #15 lore raw

Re: [PATCH 11/17] MIPS: Netlogic: Fix XLP9XX pic entry

Hello.

Quoted 13 lines · Jayachandran C

Add the compatible property to the PIC entry. Also fix up the nodename to use the correct address.
Signed-off-by Jayachandran C <[email protected]>
---
  arch/mips/netlogic/dts/xlp_gvp.dts |    5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)
arch/mips/netlogic/dts/xlp_gvp.dts +0 -0
index 047d27f..bb4ecd1 100644

arch/mips/netlogic/dts/xlp_gvp.dts line 29

Quoted 6 lines

arch/mips/netlogic/dts/xlp_gvp.dts +1 -2

@@ -26,11 +26,12 @@
  			interrupt-parent = <&pic>;
  			interrupts = <17>;
  		};
-		pic: pic@4000 {
-			interrupt-controller;
+		pic: pic@110000 {

According to the ePAPR standard [1], the node name should be
"interrupt-controller@110000".

arch/mips/netlogic/dts/xlp_gvp.dts line 35

Quoted 6 lines

arch/mips/netlogic/dts/xlp_gvp.dts +2 -0

+			compatible = "netlogic,xlp-pic";
  			#address-cells = <0>;
  			#interrupt-cells = <1>;
  			reg = <0 0x110000 0x200>;
+			interrupt-controller;
  		};

[1] http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf

WBR, Sergei

Jayachandran C.

author

2014-04-30 09:49 UTC #16 lore raw

Re: [PATCH 11/17] MIPS: Netlogic: Fix XLP9XX pic entry

Quoted 27 lines · Sergei Shtylyov

Hello.
Quoted 13 lines · Jayachandran C
Add the compatible property to the PIC entry. Also fix up the nodename to use the correct address.
Signed-off-by Jayachandran C <[email protected]>
---
 arch/mips/netlogic/dts/xlp_gvp.dts |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
arch/mips/netlogic/dts/xlp_gvp.dts +0 -0
index 047d27f..bb4ecd1 100644
arch/mips/netlogic/dts/xlp_gvp.dts line 29
Quoted 6 lines
arch/mips/netlogic/dts/xlp_gvp.dts +1 -2
@@ -26,11 +26,12 @@
 			interrupt-parent = <&pic>;
 			interrupts = <17>;
 		};
-		pic: pic@4000 {
-			interrupt-controller;
+		pic: pic@110000 {
According to the ePAPR standard [1], the node name should be
"interrupt-controller@110000".

Quoted 6 lines

arch/mips/netlogic/dts/xlp_gvp.dts line 35
Quoted 6 lines
arch/mips/netlogic/dts/xlp_gvp.dts +2 -0
+			compatible = "netlogic,xlp-pic";
 			#address-cells = <0>;
 			#interrupt-cells = <1>;
 			reg = <0 0x110000 0x200>;
+			interrupt-controller;
 		};

The ePAPR document itself has a interrupt-controller definition which uses the node name "pic". And most of the linux kernel dts files use "pic" as well.

Based on this, I think that even if the standard recommends using interrupt-contoller as the nodename, pic can be used as well.

Thanks,
JC.

Jayachandran C

author

2014-04-29 14:32 UTC #17 lore raw

PATCH 12/17 MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XX

In reply to Jayachandran C

From: Ganesan Ramalingam <[email protected]>

Update PIC frequency calculation for XLP9XX and 2XX processors using the correct PLL registers. This should work for all possible board configurations.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/iomap.h |    2 +
 arch/mips/include/asm/netlogic/xlp-hal/sys.h   |   27 ++++++
 arch/mips/netlogic/common/time.c               |    5 +-
 arch/mips/netlogic/xlp/nlm_hal.c               |  114 +++++++++++++++++-------
 4 files changed, 114 insertions(+), 34 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/iomap.h +2 -0

index 14b2f51..805bfd2 100644
@@ -120,6 +120,8 @@
 #define XLP9XX_IO_UART_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 2, 2)
 #define XLP9XX_IO_SYS_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 0)
 #define XLP9XX_IO_FUSE_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 1)
+#define XLP9XX_IO_CLOCK_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 2)
+#define XLP9XX_IO_POWER_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 3)
 #define XLP9XX_IO_JTAG_OFFSET(node)	XLP9XX_HDR_OFFSET(node, 6, 4)
 
 #define XLP9XX_IO_PCIE_OFFSET(node, i)	XLP9XX_HDR_OFFSET(node, 1, i)

arch/mips/include/asm/netlogic/xlp-hal/sys.h +27 -0

index d9b107f..bcb136d 100644
@@ -147,6 +147,28 @@
 #define SYS_SYS_PLL_MEM_REQ			0x2a3
 #define SYS_PLL_MEM_STAT			0x2a4
 
+/* PLL registers XLP9XX */
+#define SYS_9XX_DMC_PLL_CTRL0			0x140
+#define SYS_9XX_DMC_PLL_CTRL1			0x141
+#define SYS_9XX_DMC_PLL_CTRL2			0x142
+#define SYS_9XX_DMC_PLL_CTRL3			0x143
+#define SYS_9XX_PLL_CTRL0			0x144
+#define SYS_9XX_PLL_CTRL1			0x145
+#define SYS_9XX_PLL_CTRL2			0x146
+#define SYS_9XX_PLL_CTRL3			0x147
+
+#define SYS_9XX_PLL_CTRL0_DEVX(x)		(0x148 + (x) * 4)
+#define SYS_9XX_PLL_CTRL1_DEVX(x)		(0x149 + (x) * 4)
+#define SYS_9XX_PLL_CTRL2_DEVX(x)		(0x14a + (x) * 4)
+#define SYS_9XX_PLL_CTRL3_DEVX(x)		(0x14b + (x) * 4)
+
+#define SYS_9XX_CPU_PLL_CHG_CTRL		0x188
+#define SYS_9XX_PLL_CHG_CTRL			0x189
+#define SYS_9XX_CLK_DEV_DIS			0x18a
+#define SYS_9XX_CLK_DEV_SEL			0x18b
+#define SYS_9XX_CLK_DEV_DIV			0x18d
+#define SYS_9XX_CLK_DEV_CHG			0x18f
+
 /* Registers changed on 9XX */
 #define SYS_9XX_POWER_ON_RESET_CFG		0x00
 #define SYS_9XX_CHIP_RESET			0x01

@@ -170,6 +192,11 @@
 #define nlm_get_fuse_regbase(node)	\
 			(nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
+#define nlm_get_clock_pcibase(node)	\
+			nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node))
+#define nlm_get_clock_regbase(node)	\
+			(nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
 unsigned int nlm_get_pic_frequency(int node);
 #endif
 #endif

arch/mips/netlogic/common/time.c +4 -1

index 13391b8..0c0a1a6 100644
@@ -82,6 +82,7 @@ static struct clocksource csrc_pic = {
 static void nlm_init_pic_timer(void)
 {
 	uint64_t picbase = nlm_get_node(0)->picbase;
+	u32 picfreq;
 
 	nlm_pic_set_timer(picbase, PIC_CLOCK_TIMER, ~0ULL, 0, 0);
 	if (current_cpu_data.cputype == CPU_XLR) {

@@ -92,7 +93,9 @@ static void nlm_init_pic_timer(void)
 		csrc_pic.read	= nlm_get_pic_timer;
 	}
 	csrc_pic.rating = 1000;
-	clocksource_register_hz(&csrc_pic, pic_timer_freq());
+	picfreq = pic_timer_freq();
+	clocksource_register_hz(&csrc_pic, picfreq);
+	pr_info("PIC clock source added, frequency %d\n", picfreq);
 }
 
 void __init plat_time_init(void)

arch/mips/netlogic/xlp/nlm_hal.c +81 ~~-33~~

151 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:32 UTC #18 lore raw

PATCH 13/17 MIPS: Netlogic: Update XLP9XX/2XX core freq calculation

In reply to Jayachandran C

Calculate XLP 9XX and 2XX core frequency from the per-core PLL. This should give the correct value for all board configurations.

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/sys.h |    8 +++
 arch/mips/netlogic/xlp/nlm_hal.c             |   83 ++++++++++++++++++++------
 2 files changed, 73 insertions(+), 18 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/sys.h +8 -0

index bcb136d..bc7bddf 100644
@@ -118,6 +118,10 @@
 #define SYS_SCRTCH3				0x4c
 
 /* PLL registers XLP2XX */
+#define SYS_CPU_PLL_CTRL0(core)			(0x1c0 + (core * 4))
+#define SYS_CPU_PLL_CTRL1(core)			(0x1c1 + (core * 4))
+#define SYS_CPU_PLL_CTRL2(core)			(0x1c2 + (core * 4))
+#define SYS_CPU_PLL_CTRL3(core)			(0x1c3 + (core * 4))
 #define SYS_PLL_CTRL0				0x240
 #define SYS_PLL_CTRL1				0x241
 #define SYS_PLL_CTRL2				0x242

@@ -148,6 +152,10 @@
 #define SYS_PLL_MEM_STAT			0x2a4
 
 /* PLL registers XLP9XX */
+#define SYS_9XX_CPU_PLL_CTRL0(core)		(0xc0 + (core * 4))
+#define SYS_9XX_CPU_PLL_CTRL1(core)		(0xc1 + (core * 4))
+#define SYS_9XX_CPU_PLL_CTRL2(core)		(0xc2 + (core * 4))
+#define SYS_9XX_CPU_PLL_CTRL3(core)		(0xc3 + (core * 4))
 #define SYS_9XX_DMC_PLL_CTRL0			0x140
 #define SYS_9XX_DMC_PLL_CTRL1			0x141
 #define SYS_9XX_DMC_PLL_CTRL2			0x142

arch/mips/netlogic/xlp/nlm_hal.c +65 ~~-18~~

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1.7.9.5

Jayachandran C

author

2014-04-29 14:32 UTC #19 lore raw

PATCH 14/17 MIPS: Netlogic: Add support for XLP5XX

In reply to Jayachandran C

From: Yonghong Song <[email protected]>

Add support for the XLP5XX processor which is an 8 core variant of the XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX.

Signed-off-by Yonghong Song <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/cpu.h                  |    1 +
 arch/mips/include/asm/netlogic/mips-extns.h  |    3 ++-
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h |    6 ++++--
 arch/mips/kernel/cpu-probe.c                 |    1 +
 arch/mips/netlogic/common/reset.S            |    4 ++++
 arch/mips/netlogic/xlp/dt.c                  |    1 +
 arch/mips/netlogic/xlp/setup.c               |    1 +
 arch/mips/netlogic/xlp/wakeup.c              |   10 +++++++++-
 8 files changed, 23 insertions(+), 4 deletions(-)

arch/mips/include/asm/cpu.h +1 -0

index 530eb8b..fd18e86 100644
@@ -201,6 +201,7 @@
 #define PRID_IMP_NETLOGIC_XLP3XX	0x1100
 #define PRID_IMP_NETLOGIC_XLP2XX	0x1200
 #define PRID_IMP_NETLOGIC_XLP9XX	0x1500
+#define PRID_IMP_NETLOGIC_XLP5XX	0x1300
 
 /*
  * Particular Revision values for bits 7:0 of the PRId register.

arch/mips/include/asm/netlogic/mips-extns.h +2 -1

index 38af905..06f1f75 100644
@@ -148,7 +148,8 @@ static inline int nlm_nodeid(void)
 {
 	uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
 
-	if (prid == PRID_IMP_NETLOGIC_XLP9XX)
+	if ((prid == PRID_IMP_NETLOGIC_XLP9XX) ||
+			(prid == PRID_IMP_NETLOGIC_XLP5XX))
 		return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
 	else
 		return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +4 -2

index f75014c..8f8afe0 100644
@@ -102,14 +102,16 @@ static inline int cpu_is_xlpii(void)
 	int chip = read_c0_prid() & PRID_IMP_MASK;
 
 	return chip == PRID_IMP_NETLOGIC_XLP2XX ||
-		chip == PRID_IMP_NETLOGIC_XLP9XX;
+		chip == PRID_IMP_NETLOGIC_XLP9XX ||
+		chip == PRID_IMP_NETLOGIC_XLP5XX;
 }
 
 static inline int cpu_is_xlp9xx(void)
 {
 	int chip = read_c0_prid() & PRID_IMP_MASK;
 
-	return chip == PRID_IMP_NETLOGIC_XLP9XX;
+	return chip == PRID_IMP_NETLOGIC_XLP9XX ||
+		chip == PRID_IMP_NETLOGIC_XLP5XX;
 }
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_NLM_XLP_H */

arch/mips/kernel/cpu-probe.c +1 -0

index 6e8fb85..5114beb 100644
@@ -1074,6 +1074,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_NETLOGIC_XLP2XX:
 	case PRID_IMP_NETLOGIC_XLP9XX:
+	case PRID_IMP_NETLOGIC_XLP5XX:
 		c->cputype = CPU_XLP;
 		__cpu_name[cpu] = "Broadcom XLPII";
 		break;

arch/mips/netlogic/common/reset.S +4 -0

index 5b60b46..701c4bc 100644
@@ -177,6 +177,10 @@ FEXPORT(nlm_reset_entry)
 	beq	t0, t1, 2f		/* does not need to set coherent */
 	nop
 
+	li	t1, 0x1300		/* XLP 5xx */
+	beq	t0, t1, 2f		/* does not need to set coherent */
+	nop
+
 	/* set bit in SYS coherent register for the core */
 	mfc0	t0, CP0_EBASE, 1
 	mfc0	t1, CP0_EBASE, 1

arch/mips/netlogic/xlp/dt.c +1 -0

index 0b36ac8..bba993a 100644
@@ -51,6 +51,7 @@ void __init *xlp_dt_init(void *fdtp)
 		switch (current_cpu_data.processor_id & PRID_IMP_MASK) {
 #ifdef CONFIG_DT_XLP_GVP
 		case PRID_IMP_NETLOGIC_XLP9XX:
+		case PRID_IMP_NETLOGIC_XLP5XX:
 			fdtp = __dtb_xlp_gvp_begin;
 			break;
 #endif

arch/mips/netlogic/xlp/setup.c +1 -0

index 3455e9f..135a38f 100644
@@ -123,6 +123,7 @@ const char *get_system_type(void)
 {
 	switch (read_c0_prid() & PRID_IMP_MASK) {
 	case PRID_IMP_NETLOGIC_XLP9XX:
+	case PRID_IMP_NETLOGIC_XLP5XX:
 	case PRID_IMP_NETLOGIC_XLP2XX:
 		return "Broadcom XLPII Series";
 	default:

arch/mips/netlogic/xlp/wakeup.c +9 -1

index f4823ad..e5f44d2 100644
@@ -135,7 +135,15 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
 		if (cpu_is_xlp9xx()) {
 			fusebase = nlm_get_fuse_regbase(n);
 			fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
-			mask = 0xfffff;
+			switch (read_c0_prid() & PRID_IMP_MASK) {
+			case PRID_IMP_NETLOGIC_XLP5XX:
+				mask = 0xff;
+				break;
+			case PRID_IMP_NETLOGIC_XLP9XX:
+			default:
+				mask = 0xfffff;
+				break;
+			}
 		} else {
 			fusemask = nlm_read_sys_reg(nodep->sysbase,
 						SYS_EFUSE_DEVICE_CFG_STATUS0);

Signature · 1 line

1.7.9.5

Jayachandran C

author

2014-04-29 14:32 UTC #20 lore raw

PATCH 15/17 MIPS: Add MSI support for XLP9XX

In reply to Jayachandran C

From: Ganesan Ramalingam <[email protected]>

In XLP9XX, the interrupt routing table for MSI-X has been moved to the PCIe controller's config space from PIC. There are also 32 MSI-X interrupts available per link on XLP9XX.

Update XLP MSI/MSI-X code to handle this.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h |   14 ++
 arch/mips/include/asm/netlogic/xlp-hal/pic.h    |    4 +
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h    |    5 +-
 arch/mips/pci/msi-xlp.c                         |  178 +++++++++++++++++------
 4 files changed, 151 insertions(+), 50 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/pcibus.h +14 -0

index d4deb87..91540f4 100644
@@ -69,6 +69,20 @@
 #define PCIE_9XX_BYTE_SWAP_IO_BASE	0x25e
 #define PCIE_9XX_BYTE_SWAP_IO_LIM	0x25f
 
+#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE	0x264
+#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT	0x265
+#define PCIE_9XX_MSI_STATUS		0x283
+#define PCIE_9XX_MSI_EN			0x284
+/* 128 MSIX vectors available in 9xx */
+#define PCIE_9XX_MSIX_STATUS0		0x286
+#define PCIE_9XX_MSIX_STATUSX(n)	(n + 0x286)
+#define PCIE_9XX_MSIX_VEC		0x296
+#define PCIE_9XX_MSIX_VECX(n)		(n + 0x296)
+#define PCIE_9XX_INT_STATUS0		0x397
+#define PCIE_9XX_INT_STATUS1		0x398
+#define PCIE_9XX_INT_EN0		0x399
+#define PCIE_9XX_INT_EN1		0x39a
+
 /* other */
 #define PCIE_NLINKS			4

arch/mips/include/asm/netlogic/xlp-hal/pic.h +4 -0

index f10bf3b..41cefe9 100644
@@ -199,6 +199,10 @@
 #define PIC_IRT_PCIE_LINK_3_INDEX	81
 #define PIC_IRT_PCIE_LINK_INDEX(num)	((num) + PIC_IRT_PCIE_LINK_0_INDEX)
 
+#define PIC_9XX_IRT_PCIE_LINK_0_INDEX	191
+#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \
+				((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX)
+
 #define PIC_CLOCK_TIMER			7
 
 #if !defined(LOCORE) && !defined(__ASSEMBLY__)

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +3 -2

index 8f8afe0..c0b2a80 100644
@@ -70,8 +70,9 @@
 #define PIC_PCIE_MSIX_IRQ_BASE		48	/* 48 - 51 MSI-X IRQ */
 #define PIC_PCIE_MSIX_IRQ(i)		(48 + (i))
 
-#define NLM_MSIX_VEC_BASE		96	/* 96 - 127 - MSIX mapped */
-#define NLM_MSI_VEC_BASE		128	/* 128 -255 - MSI mapped */
+/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
+#define NLM_MSIX_VEC_BASE		96	/* 96 - 223 - MSIX mapped */
+#define NLM_MSI_VEC_BASE		224	/* 224 -351 - MSI mapped */
 
 #define NLM_PIC_INDIRECT_VEC_BASE	512
 #define NLM_GPIO_VEC_BASE		768

arch/mips/pci/msi-xlp.c +130 ~~-48~~

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1.7.9.5

Jayachandran C

author

2014-05-09 10:58 UTC #21 lore raw

PATCH v2 15/17 MIPS: Add MSI support for XLP9XX

From: Ganesan Ramalingam <[email protected]>

In XLP9XX, the interrupt routing table for MSI-X has been moved to the PCIe controller's config space from PIC. There are also 32 MSI-X interrupts available per link on XLP9XX.

Update XLP MSI/MSI-X code to handle this.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
[v2: Added correct MSI ack register for 9XX]

 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h |   14 ++
 arch/mips/include/asm/netlogic/xlp-hal/pic.h    |    4 +
 arch/mips/include/asm/netlogic/xlp-hal/xlp.h    |    5 +-
 arch/mips/pci/msi-xlp.c                         |  184 +++++++++++++++++------
 4 files changed, 156 insertions(+), 51 deletions(-)

arch/mips/include/asm/netlogic/xlp-hal/pcibus.h +14 -0

index d4deb87..91540f4 100644
@@ -69,6 +69,20 @@
 #define PCIE_9XX_BYTE_SWAP_IO_BASE	0x25e
 #define PCIE_9XX_BYTE_SWAP_IO_LIM	0x25f
 
+#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE	0x264
+#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT	0x265
+#define PCIE_9XX_MSI_STATUS		0x283
+#define PCIE_9XX_MSI_EN			0x284
+/* 128 MSIX vectors available in 9xx */
+#define PCIE_9XX_MSIX_STATUS0		0x286
+#define PCIE_9XX_MSIX_STATUSX(n)	(n + 0x286)
+#define PCIE_9XX_MSIX_VEC		0x296
+#define PCIE_9XX_MSIX_VECX(n)		(n + 0x296)
+#define PCIE_9XX_INT_STATUS0		0x397
+#define PCIE_9XX_INT_STATUS1		0x398
+#define PCIE_9XX_INT_EN0		0x399
+#define PCIE_9XX_INT_EN1		0x39a
+
 /* other */
 #define PCIE_NLINKS			4

arch/mips/include/asm/netlogic/xlp-hal/pic.h +4 -0

index f10bf3b..41cefe9 100644
@@ -199,6 +199,10 @@
 #define PIC_IRT_PCIE_LINK_3_INDEX	81
 #define PIC_IRT_PCIE_LINK_INDEX(num)	((num) + PIC_IRT_PCIE_LINK_0_INDEX)
 
+#define PIC_9XX_IRT_PCIE_LINK_0_INDEX	191
+#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \
+				((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX)
+
 #define PIC_CLOCK_TIMER			7
 
 #if !defined(LOCORE) && !defined(__ASSEMBLY__)

arch/mips/include/asm/netlogic/xlp-hal/xlp.h +3 -2

index 8f8afe0..c0b2a80 100644
@@ -70,8 +70,9 @@
 #define PIC_PCIE_MSIX_IRQ_BASE		48	/* 48 - 51 MSI-X IRQ */
 #define PIC_PCIE_MSIX_IRQ(i)		(48 + (i))
 
-#define NLM_MSIX_VEC_BASE		96	/* 96 - 127 - MSIX mapped */
-#define NLM_MSI_VEC_BASE		128	/* 128 -255 - MSI mapped */
+/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */
+#define NLM_MSIX_VEC_BASE		96	/* 96 - 223 - MSIX mapped */
+#define NLM_MSI_VEC_BASE		224	/* 224 -351 - MSI mapped */
 
 #define NLM_PIC_INDIRECT_VEC_BASE	512
 #define NLM_GPIO_VEC_BASE		768

arch/mips/pci/msi-xlp.c +135 ~~-49~~

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Jayachandran C

author

2014-04-29 14:32 UTC #22 lore raw

PATCH 16/17 MIPS: Netlogic: Support for XLP3XX on-chip SATA

In reply to Jayachandran C

From: Ganesan Ramalingam <[email protected]>

XLP3XX includes an on-chip SATA controller with 4 ports. The controller needs glue logic initialization and PCI fixup before it can be used with the standard AHCI driver.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/xlp/Makefile    |    1 +
 arch/mips/netlogic/xlp/ahci-init.c |  209 ++++++++++++++++++++++++++++++++++++
 2 files changed, 210 insertions(+)
 create mode 100644 arch/mips/netlogic/xlp/ahci-init.c

arch/mips/netlogic/xlp/Makefile +1 -0

index ed9a93c..0cb53af 100644
@@ -2,3 +2,4 @@ obj-y				+= setup.o nlm_hal.o cop2-ex.o dt.o
 obj-$(CONFIG_SMP)		+= wakeup.o
 obj-$(CONFIG_USB)		+= usb-init.o
 obj-$(CONFIG_USB)		+= usb-init-xlp2.o
+obj-$(CONFIG_SATA_AHCI)		+= ahci-init.o

arch/mips/netlogic/xlp/ahci-init.c new file +209 -0

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Jayachandran C

author

2014-04-29 14:32 UTC #23 lore raw

PATCH 17/17 MIPS: Netlogic: XLP9XX on-chip SATA support

In reply to Jayachandran C

From: Ganesan Ramalingam <[email protected]>

The XLP9XX SoC has an on-chip SATA controller with two ports. Add ahci-init-xlp2.c to initialize the controller, setup the glue logic registers, fixup PCI quirks and setup interrupt ack logic.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
 arch/mips/netlogic/xlp/Makefile         |    1 +
 arch/mips/netlogic/xlp/ahci-init-xlp2.c |  378 +++++++++++++++++++++++++++++++
 2 files changed, 379 insertions(+)
 create mode 100644 arch/mips/netlogic/xlp/ahci-init-xlp2.c

arch/mips/netlogic/xlp/Makefile +1 -0

index 0cb53af..be358a8 100644
@@ -3,3 +3,4 @@ obj-$(CONFIG_SMP)		+= wakeup.o
 obj-$(CONFIG_USB)		+= usb-init.o
 obj-$(CONFIG_USB)		+= usb-init-xlp2.o
 obj-$(CONFIG_SATA_AHCI)		+= ahci-init.o
+obj-$(CONFIG_SATA_AHCI)		+= ahci-init-xlp2.o

arch/mips/netlogic/xlp/ahci-init-xlp2.c new file +378 -0

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Jayachandran C

author

2014-05-09 10:59 UTC #24 lore raw

PATCH v2 17/17 MIPS: Netlogic: XLP9XX on-chip SATA support

From: Ganesan Ramalingam <[email protected]>

The XLP9XX SoC has an on-chip SATA controller with two ports. Add ahci-init-xlp2.c to initialize the controller, setup the glue logic registers, fixup PCI quirks and setup interrupt ack logic.

Signed-off-by Ganesan Ramalingam <[email protected]>

Signed-off-by Jayachandran C <[email protected]>

---
[v2: Change '#if 0' to use a variable, and fix code which was commented
with the macro]

 arch/mips/netlogic/xlp/Makefile         |    1 +
 arch/mips/netlogic/xlp/ahci-init-xlp2.c |  377 +++++++++++++++++++++++++++++++
 2 files changed, 378 insertions(+)
 create mode 100644 arch/mips/netlogic/xlp/ahci-init-xlp2.c

arch/mips/netlogic/xlp/Makefile +1 -0

index 0cb53af..be358a8 100644
@@ -3,3 +3,4 @@ obj-$(CONFIG_SMP)		+= wakeup.o
 obj-$(CONFIG_USB)		+= usb-init.o
 obj-$(CONFIG_USB)		+= usb-init-xlp2.o
 obj-$(CONFIG_SATA_AHCI)		+= ahci-init.o
+obj-$(CONFIG_SATA_AHCI)		+= ahci-init-xlp2.o

arch/mips/netlogic/xlp/ahci-init-xlp2.c new file +377 -0

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