ALSA: hda - restore BCLK from CDCLK for Haswell/Broadwell display audio

From: Jani Nikula <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

drivers/gpu/drm/i915/intel_pm.c +21 -0

index a90fdbd..21170e5 100644
@@ -6256,6 +6256,27 @@ int i915_release_power_well(void)
 }
 EXPORT_SYMBOL_GPL(i915_release_power_well);
 
+/*
+ * Private interface for the audio driver to get CDCLK in kHz.
+ *
+ * Caller must request power well using i915_request_power_well() prior to
+ * making the call.
+ */
+int i915_get_cdclk_freq(void)
+{
+	struct drm_i915_private *dev_priv;
+
+	if (!hsw_pwr)
+		return -ENODEV;
+
+	dev_priv = container_of(hsw_pwr, struct drm_i915_private,
+				power_domains);
+
+	return intel_ddi_get_cdclk_freq(dev_priv);
+}
+EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
+
+
 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 
 #define HSW_ALWAYS_ON_POWER_DOMAINS (			\

include/drm/i915_powerwell.h +1 -0

index 2baba99..baa6f11 100644
@@ -32,5 +32,6 @@
 /* For use by hda_i915 driver */
 extern int i915_request_power_well(void);
 extern int i915_release_power_well(void);
+extern int i915_get_cdclk_freq(void);
 
 #endif				/* _I915_POWERWELL_H_ */

Signature · 1 line

1.8.1.2

From: Mengdong Lin <[email protected]>

For HSW/BDW display HD-A controller, this patch restores BCLK by setting the M/N values as per the core display clock (CDCLK) queried from i915 display driver.

And the audio driver will also restore BCLK in azx_first_init() since the display driver can turn off the shared power in boot phase if only eDP is connected and M/N values will be lost and must be reprogrammed.

Signed-off-by Mengdong Lin <[email protected]>

sound/pci/hda/hda_intel.c +20 -12

index 25753db..c7dfd1d 100644
@@ -299,10 +299,6 @@ static char *driver_short_names[] = {
 
 struct hda_intel {
 	struct azx chip;
-
-	/* HSW/BDW display HDA controller to restore BCLK from CDCLK */
-	unsigned int bclk_m;
-	unsigned int bclk_n;
 };
 
 

@@ -598,20 +594,41 @@ static int param_set_xint(const char *val, const struct kernel_param *kp)
 #define azx_del_card_list(chip) /* NOP */
 #endif /* CONFIG_PM */
 
-static void haswell_save_bclk(struct azx *chip)
-{
-	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
-
-	hda->bclk_m = azx_readw(chip, EM4);
-	hda->bclk_n = azx_readw(chip, EM5);
-}
 
 static void haswell_restore_bclk(struct azx *chip)
 {
-	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
+	int cdclk_freq;
+	unsigned int bclk_m, bclk_n;
+
+	cdclk_freq = hda_get_display_clk();
+	switch (cdclk_freq) {
+	case 337500:
+		bclk_m = 16;
+		bclk_n = 225;
+		break;
+
+	case 450000: /* default CDCLK 450MHz */
+		bclk_m = 4;
+		bclk_n = 75;
+		break;
+
+	case 540000:
+		bclk_m = 4;
+		bclk_n = 90;
+		break;
+

-----Original Message-----
From: Takashi Iwai [mailto:[email protected]]
Sent: Wednesday, July 02, 2014 11:01 PM
To: Lin, Mengdong
Cc: [email protected]; Nikula, Jani
Subject: Re: [PATCH 3/3] ALSA: hda - restore BCLK M/N value as per CDCLK for HSW/BDW display HDA controller

At Wed, 2 Jul 2014 22:44:07 +0800,

Quoted 10 lines · [email protected] wrote:

From: Mengdong Lin <[email protected]>

For HSW/BDW display HD-A controller, this patch restores BCLK by setting the M/N values as per the core display clock (CDCLK) queried from i915 display driver.

And the audio driver will also restore BCLK in azx_first_init() since the display driver can turn off the shared power in boot phase if only eDP is connected and M/N values will be lost and must be

reprogrammed.

sound/pci/hda/hda_intel.c static int param_set_xint(const char *val,

Quoted 19 lines

Signed-off-by Mengdong Lin <[email protected]>

sound/pci/hda/hda_intel.c +0 -4

index 25753db..c7dfd1d 100644
@@ -299,10 +299,6 @@ static char *driver_short_names[] = {
 
 struct hda_intel {
 	struct azx chip;
-
-	/* HSW/BDW display HDA controller to restore BCLK from CDCLK */
-	unsigned int bclk_m;
-	unsigned int bclk_n;
 };
 
 

@@ -598,20 +594,41 @@ static int param_set_xint(const char *val,

const

Quoted 32 lines

struct kernel_param *kp) #define azx_del_card_list(chip) /* NOP */ #endif /* CONFIG_PM */

sound/pci/hda/hda_intel.c +20 -7

-static void haswell_save_bclk(struct azx *chip) -{
-	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
-
-	hda->bclk_m = azx_readw(chip, EM4);
-	hda->bclk_n = azx_readw(chip, EM5);
-}
 
 static void haswell_restore_bclk(struct azx *chip)  {
-	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
+	int cdclk_freq;
+	unsigned int bclk_m, bclk_n;
+
+	cdclk_freq = hda_get_display_clk();
+	switch (cdclk_freq) {
+	case 337500:
+		bclk_m = 16;
+		bclk_n = 225;
+		break;
+
+	case 450000: /* default CDCLK 450MHz */
+		bclk_m = 4;
+		bclk_n = 75;
+		break;
+
+	case 540000:
+		bclk_m = 4;
+		bclk_n = 90;
+		break;
+

sound/pci/hda/hda_intel.c static int param_set_xint(const char *val, const struct kernel_param *kp) · line 627

Quoted 10 lines

sound/pci/hda/hda_intel.c +7 -2

+	case 675000:
+		bclk_m = 8;
+		bclk_n = 225;
+		break;
 
-	azx_writew(chip, EM4, hda->bclk_m);
-	azx_writew(chip, EM5, hda->bclk_n);
+	default:
+		bclk_m = 4;
+		bclk_n = 75;

You can put "default:" around "case 45000:", and move the comment about default CDCLK there.

sound/pci/hda/hda_intel.c static int param_set_xint(const char *val, const struct kernel_param *kp) · line 632

Quoted 5 lines

sound/pci/hda/hda_intel.c +4 -0

+	}
+
+	azx_writew(chip, EM4, bclk_m);
+	azx_writew(chip, EM5, bclk_n);
 }

IMO, the whole function can be moved to hda_i915.c and provided as a function such as hda_set_display_clk(). Then you can drop hda_get_display_clk() but call get_cdclk() internally.

Also, all these patches may have Cc to stable, right?

thanks,

Takashi