Upgrade uclibc

This patch series updates uclibc and related packages core-image-minimal is tested on qemuarm, qemumips, qemuppc qemux86 and qemux86-64

The following changes since commit 217aa4d9802609d2c3628c8751a27a5d25900898:

autogen-native: inherit pkgconfig to fix a build failure (2014-08-25 10:25:54 +0100)

are available in the git repository at:

git://git.openembedded.org/openembedded-core-contrib kraj/uclibc-update
http://cgit.openembedded.org/cgit.cgi/openembedded-core-contrib/log/?h=kraj/uclibc-update

Khem Raj (2):
openssl: Re-add linux-uclibc tuple
uclibc: Upgrade to tip of master

 meta/recipes-connectivity/openssl/openssl.inc      |    1 +
 meta/recipes-core/uclibc/uclibc-git.inc            |    4 +-
 ...tl.h-Define-F_SETPIPE_SZ-and-F_GETPIPE_SZ.patch |  377 --------------------
 .../0004-Add-clock_adjtime-syscall.patch           |   75 ----
 .../uclibc-git/remove_attribute_optimize_Os.patch  |  125 +------
 meta/recipes-core/uclibc/uclibc.inc                |    6 +-
 6 files changed, 7 insertions(+), 581 deletions(-)
 delete mode 100644 meta/recipes-core/uclibc/uclibc-git/0003-fcntl.h-Define-F_SETPIPE_SZ-and-F_GETPIPE_SZ.patch
 delete mode 100644 meta/recipes-core/uclibc/uclibc-git/0004-Add-clock_adjtime-syscall.patch

1.7.10.4

With last restructuring for musl, some of uclibc targets got ignored fsl/ppc and ARM worked ok since they use special target triplets which were already considered but other like mips, x86 and so on failed

---
 meta/recipes-connectivity/openssl/openssl.inc |    1 +
 1 file changed, 1 insertion(+)

index b63d164..9ec884f 100644
@@ -62,6 +62,7 @@ do_configure () {
 
 	os=${HOST_OS}
 	case $os in
+	linux-uclibc |\
 	linux-uclibceabi |\
 	linux-gnueabi |\
 	linux-uclibcspe |\

1.7.10.4

Adjust mips to cater for new mips32r2 defaulttune
Remove upstreamed patches

---
 meta/recipes-core/uclibc/uclibc-git.inc            |    4 +-
 ...tl.h-Define-F_SETPIPE_SZ-and-F_GETPIPE_SZ.patch |  377 --------------------
 .../0004-Add-clock_adjtime-syscall.patch           |   75 ----
 .../uclibc-git/remove_attribute_optimize_Os.patch  |  125 +------
 meta/recipes-core/uclibc/uclibc.inc                |    6 +-
 5 files changed, 6 insertions(+), 581 deletions(-)
 delete mode 100644 meta/recipes-core/uclibc/uclibc-git/0003-fcntl.h-Define-F_SETPIPE_SZ-and-F_GETPIPE_SZ.patch
 delete mode 100644 meta/recipes-core/uclibc/uclibc-git/0004-Add-clock_adjtime-syscall.patch

index 69e834d..a6b9f65 100644
@@ -1,4 +1,4 @@
-SRCREV="5eddde8f094ef52dca06695cc598e3b2556dcccb"
+SRCREV = "48a0006012679ff0eda6f256da958d73a924fb57"
 
 PV = "0.9.33+git${SRCPV}"
 

@@ -23,7 +23,5 @@ SRC_URI = "git://uclibc.org/uClibc.git;branch=master \
 	file://0001-Revert-utent.c-wtent.c-move-functions-from-utxent.c.patch \
 	file://0001-Add-eventfd_read-and-eventfd_write.patch \
 	file://0002-wire-setns-syscall.patch \
-	file://0003-fcntl.h-Define-F_SETPIPE_SZ-and-F_GETPIPE_SZ.patch \
-	file://0004-Add-clock_adjtime-syscall.patch \ 
 	"
 S = "${WORKDIR}/git"

index a86ac3d..18587ca 100644
@@ -93,10 +93,10 @@ python () {
     # if we use TARGET_CC_ARCH="-march=mips32" we end up 
     # with conflicting march options to gcc. Here we
     # ask for MIPS32 ISA to match the chosen arch
-
-    if "mips32" in d.getVar("TUNE_FEATURES",True):
+    tune = d.getVar("DEFAULTTUNE", True)
+    if tune in ['mips32', 'mips32r2']:
         d.setVar('configmangle_append',
-                 "/^### MIPS32_CHECK$/a\\\nCONFIG_MIPS_ISA_MIPS32=y\n\n")
+                 "/^### MIPS32_CHECK$/a\\\nCONFIG_MIPS_ISA_%s=y\n\n" % (tune.upper()))
     if "${OE_FEATURES}":
         d.setVar('configmangle_append',
                    "/^### DISTRO FEATURES$/a\\\n%s\n\n" %

1.7.10.4