drm/i915: get backlight max from vbt
Subsystems (2)
cover drm/i915: get backlight max from vbt
Found this while cleaning up some old branches I have in my repo...
I'm posting this more as archival for posterity than as a serious attempt to get this merged. There was a bunch of archeology involved in figuring out the Hz to PWM modulation frequency conversion, so someone might find that useful.
Particularly the vlv setup could use some cleanup and only falling back to the hardcoded value if vbt is not set. And the hardcoded default could now be expressed in Hz instead of raw pwm value. But meh until someone really needs this.
BR,
Jani.
Jani Nikula (2):
drm/i915: move intel_hrawclk() to intel_display.c drm/i915: initialize backlight max from VBT
drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 33 ++++++++ drivers/gpu/drm/i915/intel_dp.c | 34 -------- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_panel.c | 160 +++++++++++++++++++++++++++++++++-- 6 files changed, 190 insertions(+), 41 deletions(-)
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2.1.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
RFC PATCH 1/2 drm/i915: move intel_hrawclk() to intel_display.c
Make it available outside of intel_dp.c.
--- drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dp.c | 34 ---------------------------------- drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 34 insertions(+), 34 deletions(-)
drivers/gpu/drm/i915/intel_display.c +33 -0
@@ -142,6 +142,39 @@ intel_pch_rawclk(struct drm_device *dev)return I915_READ (PCH_RAWCLK_FREQ ) &RAWCLK_FREQ_MASK ; } +/* hrawclock is 1/4 the FSB frequency */ +int intel_hrawclk (struct drm_device *dev) +{ +struct drm_i915_private *dev_priv = dev->dev_private; +uint32_t clkcfg; + +/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ +if (IS_VALLEYVIEW (dev)) +return 200 ; + + clkcfg =I915_READ (CLKCFG ); +switch (clkcfg &CLKCFG_FSB_MASK ) { +case CLKCFG_FSB_400 : +return 100 ; +case CLKCFG_FSB_533 : +return 133 ; +case CLKCFG_FSB_667 : +return 166 ; +case CLKCFG_FSB_800 : +return 200 ; +case CLKCFG_FSB_1067 : +return 266 ; +case CLKCFG_FSB_1333 : +return 333 ; +/* these two are just a guess; one of them might be right */ +case CLKCFG_FSB_1600 : +case CLKCFG_FSB_1600_ALT : +return 400 ; +default : +return 133 ; + } +} +static inline u32 /* units of 100MHz */ intel_fdi_link_freq (struct drm_device *dev) {
drivers/gpu/drm/i915/intel_dp.c +0 -34
@@ -254,40 +254,6 @@ static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) dst[i] = src >> ((3 -i) *8 ); } -/* hrawclock is 1/4 the FSB frequency */ -static int -intel_hrawclk (struct drm_device *dev) -{ -struct drm_i915_private *dev_priv = dev->dev_private; -uint32_t clkcfg; - -/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ -if (IS_VALLEYVIEW (dev)) -return 200 ; - - clkcfg =I915_READ (CLKCFG ); -switch (clkcfg &CLKCFG_FSB_MASK ) { -case CLKCFG_FSB_400 : -return 100 ; -case CLKCFG_FSB_533 : -return 133 ; -case CLKCFG_FSB_667 : -return 166 ; -case CLKCFG_FSB_800 : -return 200 ; -case CLKCFG_FSB_1067 : -return 266 ; -case CLKCFG_FSB_1333 : -return 333 ; -/* these two are just a guess; one of them might be right */ -case CLKCFG_FSB_1600 : -case CLKCFG_FSB_1600_ALT : -return 400 ; -default : -return 133 ; - } -} -static void intel_dp_init_panel_power_sequencer (struct drm_device *dev,struct intel_dp *intel_dp);
drivers/gpu/drm/i915/intel_drv.h +1 -0
@@ -981,6 +981,7 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);extern const struct drm_plane_funcs intel_plane_funcs;bool intel_has_pending_fb_unpin (struct drm_device *dev);int intel_pch_rawclk (struct drm_device *dev); +int intel_hrawclk (struct drm_device *dev);void intel_mark_busy (struct drm_device *dev);void intel_mark_idle (struct drm_device *dev);void intel_crtc_restore_mode (struct drm_crtc *crtc);
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2.1.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
RFC PATCH 2/2 drm/i915: initialize backlight max from VBT
In reply to Jani NikulaNormally we determine the backlight PWM modulation frequency (which we also use as backlight max value) from the backlight registers at module load time, expecting the registers have been initialized by the BIOS. If this is not the case, we fail.
The VBT contains the backlight modulation frequency in Hz. Add platform specific functions to convert the frequency in Hz to backlight PWM modulation frequency, and use them to initialize the backlight when the registers are not initialized by the BIOS.
--- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_panel.c | 160 +++++++++++++++++++++++++++++++++++-- 3 files changed, 156 insertions(+), 7 deletions(-)
drivers/gpu/drm/i915/i915_drv.h +2 -0
@@ -602,6 +602,8 @@ struct drm_i915_display_funcs { uint32_t level);void (*disable_backlight)(struct intel_connector *connector);void (*enable_backlight)(struct intel_connector *connector); +uint32_t (*backlight_hz_to_pwm)(struct intel_connector *connector, +uint32_t hz); };enum forcewake_domain_id {
drivers/gpu/drm/i915/i915_reg.h +1 -0
@@ -6168,6 +6168,7 @@ enum skl_disp_power_wells {#define SOUTH_CHICKEN2 0xc2004#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) +#define PWM_GRANULARITY (1<<5)/* LPT */ #define DPLS_EDP_PPS_FIX_DIS (1<<0)#define _FDI_RXA_CHICKEN 0xc200c
drivers/gpu/drm/i915/intel_panel.c +153 -7
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2.1.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx