Add configuration options for tlv320aic32x4

index ad6cb90..ce0972f 100644
@@ -500,13 +500,14 @@ static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
 
 	switch (level) {
 	case SND_SOC_BIAS_ON:
-		/* Switch on master clock */
-		ret = clk_prepare_enable(aic32x4->mclk);
-		if (ret) {
-			dev_err(codec->dev, "Failed to enable master clock\n");
-			return ret;
+		if (aic32x4->mclk) {
+			/* Switch on master clock */
+			ret = clk_prepare_enable(aic32x4->mclk);
+			if (ret) {
+				dev_err(codec->dev, "Failed to enable master clock\n");
+				return ret;
+			}
 		}
-
 		/* Switch on PLL */
 		snd_soc_update_bits(codec, AIC32X4_PLLPR,
 				    AIC32X4_PLLEN, AIC32X4_PLLEN);

@@ -558,8 +559,10 @@ static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
 		snd_soc_update_bits(codec, AIC32X4_PLLPR,
 				    AIC32X4_PLLEN, 0);
 
-		/* Switch off master clock */
-		clk_disable_unprepare(aic32x4->mclk);
+		if (aic32x4->mclk) {
+			/* Switch off master clock */
+			clk_disable_unprepare(aic32x4->mclk);
+		}
 		break;
 	case SND_SOC_BIAS_OFF:
 		break;

@@ -816,8 +819,8 @@ static int aic32x4_i2c_probe(struct i2c_client *i2c,
 
 	aic32x4->mclk = devm_clk_get(&i2c->dev, "mclk");
 	if (IS_ERR(aic32x4->mclk)) {
-		dev_err(&i2c->dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
-		return PTR_ERR(aic32x4->mclk);
+		dev_warn(&i2c->dev, "Failed getting the mclk.\n");
+		aic32x4->mclk = NULL;
 	}
 
 	if (gpio_is_valid(aic32x4->rstn_gpio)) {

index ce0972f..d3636c1 100644
@@ -353,17 +353,35 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 		return -EINVAL;
 	}
 
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_IB_NF:
+		iface_reg_3 |= (1 << 3); /* invert bit clock */
+		break;
+
+	case SND_SOC_DAIFMT_NB_IF:
+		break;
+
+	case SND_SOC_DAIFMT_IB_IF:
+		iface_reg_3 |= (1 << 3); /* invert bit clock */
+		break;
+
+	case SND_SOC_DAIFMT_NB_NF:
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+
 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 	case SND_SOC_DAIFMT_I2S:
 		break;
 	case SND_SOC_DAIFMT_DSP_A:
 		iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
-		iface_reg_3 |= (1 << 3); /* invert bit clock */
 		iface_reg_2 = 0x01; /* add offset 1 */
 		break;
 	case SND_SOC_DAIFMT_DSP_B:
 		iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
-		iface_reg_3 |= (1 << 3); /* invert bit clock */
 		break;
 	case SND_SOC_DAIFMT_RIGHT_J:
 		iface_reg_1 |=

index 24e5d99..43ea355 100644
@@ -18,13 +18,21 @@
 #define AIC32X4_PWR_AIC32X4_LDO_ENABLE		0x00000004
 #define AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36	0x00000008
 #define AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED	0x00000010
+#define AIC32X4_PWR_AIC32X4_LDO_DVDD_1_77	0x00000020
+#define AIC32X4_PWR_AIC32X4_LDO_AVDD_1_77	0x00000040
+#define AIC32X4_PWR_MICBIAS_OFF			0x00000080
+
+#define AIC32X4_PWR_AIC32X4_MASK		0x000000ff
 
 #define AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K	0x00000001
 #define AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K	0x00000002
+#define AIC32X4_MICPGA_ROUTE_MASK		0x00000003
 
 struct aic32x4_pdata {
 	u32 power_cfg;
 	u32 micpga_routing;
+	u32 inputs[6];
+	u32 cmode[2];
 	bool swapdacs;
 	int rstn_gpio;
 };

280 lines not on this page · raw message

index 995f033..75bb727 100644
@@ -104,6 +104,9 @@
 
 #define AIC32X4_AVDDWEAKDISABLE		0x08
 #define AIC32X4_LDOCTLEN		0x01
+#define AIC32X4_ANALOG_DISABLE		0x08
+#define AIC32X4_LDO_DVDD_1_77		0x80
+#define AIC32X4_LDO_AVDD_1_77		0x20
 
 #define AIC32X4_LDOIN_18_36		0x01
 #define AIC32X4_LDOIN2HP		0x02

@@ -124,6 +127,13 @@
 #define AIC32X4_RMICPGANIN_IN1L_10K	0x10
 #define AIC32X4_RMICPGANIN_CM1R_10K	0x40
 
+#define AIC32X4_MICPGA_IN1L_NO_FLOAT	0x80
+#define AIC32X4_MICPGA_IN1R_NO_FLOAT	0x40
+#define AIC32X4_MICPGA_IN2L_NO_FLOAT	0x20
+#define AIC32X4_MICPGA_IN2R_NO_FLOAT	0x10
+#define AIC32X4_MICPGA_IN3L_NO_FLOAT	0x08
+#define AIC32X4_MICPGA_IN3R_NO_FLOAT	0x04
+
 #define AIC32X4_LMICPGAVOL_NOGAIN	0x80
 #define AIC32X4_RMICPGAVOL_NOGAIN	0x80