net: stmmac: adding multiple buffers and routing

PATCH Superseded Joao Pinto 2 participants 8 messages Mar 16, 2017 – Mar 17, 2017

Subsystems (5)

Networking Network drivers Device tree bindings Arm STM32 +1 more subsystems

lore

Share & tools

lore

Joao Pinto

author

2017-03-16 10:57 UTC #0 lore raw

cover net: stmmac: adding multiple buffers and routing

As agreed with David Miller, this patch-set is the third and last to enable multiple queues in stmmac.

This third one focuses on:

a) Enable multiple buffering to the driver and queue independent data
b) Configuration of RX and TX queues' priority
c) Configuration of RX queues' routing

Joao Pinto (3):
net: stmmac: enable multiple buffers
net: stmmac: TX and RX queue priority configuration
net: stmmac: RX queue routing configuration

 Documentation/devicetree/bindings/net/stmmac.txt   |   24 +-
 drivers/net/ethernet/stmicro/stmmac/chain_mode.c   |   45 +-
 drivers/net/ethernet/stmicro/stmmac/common.h       |   13 +
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h       |   31 +
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  |  100 ++
 drivers/net/ethernet/stmicro/stmmac/ring_mode.c    |   46 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac.h       |   49 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 1379 ++++++++++++++------
 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c   |   12 +
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   65 +
 include/linux/stmmac.h                             |   16 +
 11 files changed, 1306 insertions(+), 474 deletions(-)

Signature · 1 line

2.9.3

Joao Pinto

author

2017-03-16 10:57 UTC #1 lore raw

PATCH 1/3 net: stmmac: enable multiple buffers

This patch creates 2 new structures (stmmac_tx_queue and stmmac_rx_queue) in include/linux/stmmac.h, enabling that each RX and TX queue has its own buffers and data.

Signed-off-by Joao Pinto <[email protected]>

---
 drivers/net/ethernet/stmicro/stmmac/chain_mode.c  |   45 +-
 drivers/net/ethernet/stmicro/stmmac/ring_mode.c   |   46 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac.h      |   49 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 1306 ++++++++++++++-------
 4 files changed, 973 insertions(+), 473 deletions(-)

drivers/net/ethernet/stmicro/stmmac/chain_mode.c +25 ~~-20~~

index 01a8c02..37881f8 100644
@@ -26,12 +26,15 @@
 
 static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum)
 {
-	struct stmmac_priv *priv = (struct stmmac_priv *)p;
-	unsigned int entry = priv->cur_tx;
-	struct dma_desc *desc = priv->dma_tx + entry;
+	struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)p;
 	unsigned int nopaged_len = skb_headlen(skb);
+	struct stmmac_priv *priv = tx_q->priv_data;
+	unsigned int entry = tx_q->cur_tx;
 	unsigned int bmax, des2;
 	unsigned int i = 1, len;
+	struct dma_desc *desc;
+
+	desc = tx_q->dma_tx + entry;
 
 	if (priv->plat->enh_desc)
 		bmax = BUF_SIZE_8KiB;

@@ -45,16 +48,16 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum)
 	desc->des2 = cpu_to_le32(des2);
 	if (dma_mapping_error(priv->device, des2))
 		return -1;
-	priv->tx_skbuff_dma[entry].buf = des2;
-	priv->tx_skbuff_dma[entry].len = bmax;
+	tx_q->tx_skbuff_dma[entry].buf = des2;
+	tx_q->tx_skbuff_dma[entry].len = bmax;
 	/* do not close the descriptor and do not set own bit */
 	priv->hw->desc->prepare_tx_desc(desc, 1, bmax, csum, STMMAC_CHAIN_MODE,
 					0, false);
 
 	while (len != 0) {
-		priv->tx_skbuff[entry] = NULL;
+		tx_q->tx_skbuff[entry] = NULL;
 		entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
-		desc = priv->dma_tx + entry;
+		desc = tx_q->dma_tx + entry;
 
 		if (len > bmax) {
 			des2 = dma_map_single(priv->device,

@@ -63,8 +66,8 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum)
 			desc->des2 = cpu_to_le32(des2);
 			if (dma_mapping_error(priv->device, des2))
 				return -1;
-			priv->tx_skbuff_dma[entry].buf = des2;
-			priv->tx_skbuff_dma[entry].len = bmax;
+			tx_q->tx_skbuff_dma[entry].buf = des2;
+			tx_q->tx_skbuff_dma[entry].len = bmax;
 			priv->hw->desc->prepare_tx_desc(desc, 0, bmax, csum,
 							STMMAC_CHAIN_MODE, 1,
 							false);

@@ -77,8 +80,8 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum)
 			desc->des2 = cpu_to_le32(des2);
 			if (dma_mapping_error(priv->device, des2))
 				return -1;
-			priv->tx_skbuff_dma[entry].buf = des2;
-			priv->tx_skbuff_dma[entry].len = len;
+			tx_q->tx_skbuff_dma[entry].buf = des2;
+			tx_q->tx_skbuff_dma[entry].len = len;
 			/* last descriptor can be set now */
 			priv->hw->desc->prepare_tx_desc(desc, 0, len, csum,
 							STMMAC_CHAIN_MODE, 1,

@@ -87,7 +90,7 @@ static int stmmac_jumbo_frm(void *p, struct sk_buff *skb, int csum)
 		}
 	}
 
-	priv->cur_tx = entry;
+	tx_q->cur_tx = entry;
 
 	return entry;
 }

@@ -136,32 +139,34 @@ static void stmmac_init_dma_chain(void *des, dma_addr_t phy_addr,
 
 static void stmmac_refill_desc3(void *priv_ptr, struct dma_desc *p)
 {
-	struct stmmac_priv *priv = (struct stmmac_priv *)priv_ptr;
+	struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)priv_ptr;
+	struct stmmac_priv *priv = rx_q->priv_data;
 
 	if (priv->hwts_rx_en && !priv->extend_desc)
 		/* NOTE: Device will overwrite des3 with timestamp value if
 		 * 1588-2002 time stamping is enabled, hence reinitialize it
 		 * to keep explicit chaining in the descriptor.
 		 */
-		p->des3 = cpu_to_le32((unsigned int)(priv->dma_rx_phy +
-				      (((priv->dirty_rx) + 1) %
+		p->des3 = cpu_to_le32((unsigned int)(rx_q->dma_rx_phy +
+				      (((rx_q->dirty_rx) + 1) %
 				       DMA_RX_SIZE) *
 				      sizeof(struct dma_desc)));
 }
 
 static void stmmac_clean_desc3(void *priv_ptr, struct dma_desc *p)
 {
-	struct stmmac_priv *priv = (struct stmmac_priv *)priv_ptr;
-	unsigned int entry = priv->dirty_tx;
+	struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)priv_ptr;
+	struct stmmac_priv *priv = tx_q->priv_data;
+	unsigned int entry = tx_q->dirty_tx;
 
-	if (priv->tx_skbuff_dma[entry].last_segment && !priv->extend_desc &&
+	if (tx_q->tx_skbuff_dma[entry].last_segment && !priv->extend_desc &&
 	    priv->hwts_tx_en)
 		/* NOTE: Device will overwrite des3 with timestamp value if
 		 * 1588-2002 time stamping is enabled, hence reinitialize it
 		 * to keep explicit chaining in the descriptor.
 		 */
-		p->des3 = cpu_to_le32((unsigned int)((priv->dma_tx_phy +
-				      ((priv->dirty_tx + 1) % DMA_TX_SIZE))
+		p->des3 = cpu_to_le32((unsigned int)((tx_q->dma_tx_phy +
+				      ((tx_q->dirty_tx + 1) % DMA_TX_SIZE))
 				      * sizeof(struct dma_desc)));
 }

drivers/net/ethernet/stmicro/stmmac/ring_mode.c +24 ~~-22~~

96 lines not on this page · raw message

drivers/net/ethernet/stmicro/stmmac/stmmac.h +35 ~~-14~~

77 lines not on this page · raw message

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +889 ~~-417~~

2,058 lines not on this page · raw message

Signature · 1 line

2.9.3

Joao Pinto

author

2017-03-16 10:57 UTC #2 lore raw

PATCH 2/3 net: stmmac: TX and RX queue priority configuration

In reply to Joao Pinto

This patch adds the configuration of RX and TX queues' priority.

Signed-off-by Joao Pinto <[email protected]>

---
 Documentation/devicetree/bindings/net/stmmac.txt   |  5 +++
 drivers/net/ethernet/stmicro/stmmac/common.h       |  4 ++
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h       | 13 ++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  | 37 +++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 48 ++++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c   |  4 ++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  | 16 ++++++++
 include/linux/stmmac.h                             |  4 ++
 8 files changed, 131 insertions(+)

Documentation/devicetree/bindings/net/stmmac.txt +5 -0

index a7b0e41..b9a9ae9 100644
@@ -83,6 +83,7 @@ Optional properties:
 			- snps,dcb-algorithm: Queue to be enabled as DCB
 			- snps,avb-algorithm: Queue to be enabled as AVB
 		- snps,map-to-dma-channel: Channel to map
+	- snps,priority: RX queue priority
 - Multiple TX Queues parameters: below the list of all the parameters to
 				 configure the multiple TX queues:
 	- snps,tx-queues-to-use: number of TX queues to be used in the driver

@@ -101,6 +102,7 @@ Optional properties:
 			- snps,idle_slope: unlock on WoL
 			- snps,high_credit: max write outstanding req. limit
 			- snps,low_credit: max read outstanding req. limit
+		- snps,priority: TX queue priority
 Examples:
 
 	stmmac_axi_setup: stmmac-axi-config {

@@ -115,6 +117,7 @@ Examples:
 		queue0 {
 			snps,dcb-algorithm;
 			snps,map-to-dma-channel = <0x0>;
+			snps,priority = <0x0>;
 		};
 	};

@@ -124,6 +127,7 @@ Examples:
 		queue0 {
 			snps,weight = <0x10>;
 			snps,dcb-algorithm;
+			snps,priority = <0x0>;
 		};
 
 		queue1 {

@@ -132,6 +136,7 @@ Examples:
 			snps,idle_slope = <0x1000>;
 			snps,high_credit = <0x3E800>;
 			snps,low_credit = <0xFFC18000>;
+			snps,priority = <0x1>;
 		};
 	};

drivers/net/ethernet/stmicro/stmmac/common.h +4 -0

index badc441..e0b31e7 100644
@@ -469,6 +469,10 @@ struct stmmac_ops {
 	int (*rx_ipc)(struct mac_device_info *hw);
 	/* Enable RX Queues */
 	void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
+	/* RX Queues Priority */
+	void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
+	/* TX Queues Priority */
+	void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
 	/* Program RX Algorithms */
 	void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
 	/* Program TX Algorithms */

drivers/net/ethernet/stmicro/stmmac/dwmac4.h +13 -0

index 54bcdb4..a6c382d 100644
@@ -22,7 +22,12 @@
 #define GMAC_HASH_TAB_32_63		0x00000014
 #define GMAC_RX_FLOW_CTRL		0x00000090
 #define GMAC_QX_TX_FLOW_CTRL(x)		(0x70 + x * 4)
+#define GMAC_TXQ_PRTY_MAP0		0x98
+#define GMAC_TXQ_PRTY_MAP1		0x9C
 #define GMAC_RXQ_CTRL0			0x000000a0
+#define GMAC_RXQ_CTRL1			0x000000a4
+#define GMAC_RXQ_CTRL2			0x000000a8
+#define GMAC_RXQ_CTRL3			0x000000ac
 #define GMAC_INT_STATUS			0x000000b0
 #define GMAC_INT_EN			0x000000b4
 #define GMAC_1US_TIC_COUNTER		0x000000dc

@@ -54,6 +59,14 @@
 /* MAC Flow Control RX */
 #define GMAC_RX_FLOW_CTRL_RFE		BIT(0)
 
+/* RX Queues Priorities */
+#define GMAC_RXQCTRL_PSRQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
+#define GMAC_RXQCTRL_PSRQX_SHIFT(x)	((x) * 8)
+
+/* TX Queues Priorities */
+#define GMAC_TXQCTRL_PSTQX_MASK(x)	GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
+#define GMAC_TXQCTRL_PSTQX_SHIFT(x)	((x) * 8)
+
 /* MAC Flow Control TX */
 #define GMAC_TX_FLOW_CTRL_TFE		BIT(1)
 #define GMAC_TX_FLOW_CTRL_PT_SHIFT	16

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +37 -0

index 10599db..342f62a 100644
@@ -74,6 +74,41 @@ static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
 	writel(value, ioaddr + GMAC_RXQ_CTRL0);
 }
 
+static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
+				     u32 prio, u32 queue)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 base_register;
+	u32 value;
+
+	base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
+
+	value = readl(ioaddr + base_register);
+
+	value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
+	value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
+						GMAC_RXQCTRL_PSRQX_MASK(queue);
+	writel(value, ioaddr + base_register);
+}
+
+static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
+				     u32 prio, u32 queue)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 base_register;
+	u32 value;
+
+	base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
+
+	value = readl(ioaddr + base_register);
+
+	value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
+	value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
+						GMAC_TXQCTRL_PSTQX_MASK(queue);
+
+	writel(value, ioaddr + base_register);
+}
+
 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 					  u32 rx_alg)
 {

@@ -603,6 +638,8 @@ static const struct stmmac_ops dwmac4_ops = {
 	.core_init = dwmac4_core_init,
 	.rx_ipc = dwmac4_rx_ipc_enable,
 	.rx_queue_enable = dwmac4_rx_queue_enable,
+	.rx_queue_prio = dwmac4_rx_queue_priority,
+	.tx_queue_prio = dwmac4_tx_queue_priority,
 	.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 	.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 	.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +48 -0

60 lines not on this page · raw message

drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +4 -0

index cea472a..ffe4fac 100644
@@ -92,6 +92,10 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat)
 	/* Set default number of RX and TX queues to use */
 	plat->tx_queues_to_use = 1;
 	plat->rx_queues_to_use = 1;
+
+	/* Disable Priority config by default */
+	plat->tx_queues_cfg[0].use_prio = false;
+	plat->rx_queues_cfg[0].use_prio = false;
 }
 
 static int quark_default_data(struct plat_stmmacenet_data *plat,

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +16 -0

index 37f550a..77b0468 100644
@@ -182,6 +182,14 @@ static void stmmac_mtl_setup(struct platform_device *pdev,
 			plat->rx_queues_cfg[queue].chan = queue;
 		/* TODO: Dynamic mapping to be included in the future */
 
+		if (of_property_read_u32(q_node, "snps,priority",
+					&plat->rx_queues_cfg[queue].prio)) {
+			plat->rx_queues_cfg[queue].prio = 0;
+			plat->rx_queues_cfg[queue].use_prio = false;
+		} else {
+			plat->rx_queues_cfg[queue].use_prio = true;
+		}
+
 		queue++;
 	}

@@ -235,6 +243,14 @@ static void stmmac_mtl_setup(struct platform_device *pdev,
 			plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_DCB;
 		}
 
+		if (of_property_read_u32(q_node, "snps,priority",
+					&plat->tx_queues_cfg[queue].prio)) {
+			plat->tx_queues_cfg[queue].prio = 0;
+			plat->tx_queues_cfg[queue].use_prio = false;
+		} else {
+			plat->tx_queues_cfg[queue].use_prio = true;
+		}
+
 		queue++;
 	}

include/linux/stmmac.h +4 -0

index be47b85..b7d5e7a 100644
@@ -127,6 +127,8 @@ struct stmmac_axi {
 struct stmmac_rxq_cfg {
 	u8 mode_to_use;
 	u8 chan;
+	bool use_prio;
+	u32 prio;
 };
 
 struct stmmac_txq_cfg {

@@ -137,6 +139,8 @@ struct stmmac_txq_cfg {
 	u32 idle_slope;
 	u32 high_credit;
 	u32 low_credit;
+	bool use_prio;
+	u32 prio;
 };
 
 struct plat_stmmacenet_data {

Signature · 1 line

2.9.3

Joao Pinto

author

2017-03-16 10:57 UTC #5 lore raw

PATCH 3/3 net: stmmac: RX queue routing configuration

In reply to Joao Pinto

This patch adds the configuration of RX queues' routing.

Signed-off-by Joao Pinto <[email protected]>

---
 Documentation/devicetree/bindings/net/stmmac.txt   | 19 ++++++-
 drivers/net/ethernet/stmicro/stmmac/common.h       |  9 ++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h       | 18 +++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  | 63 ++++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 25 +++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c   |  8 +++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  | 49 +++++++++++++++++
 include/linux/stmmac.h                             | 12 +++++
 8 files changed, 202 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/net/stmmac.txt +18 -1

index b9a9ae9..9c9e774 100644
@@ -84,6 +84,16 @@ Optional properties:
 			- snps,avb-algorithm: Queue to be enabled as AVB
 		- snps,map-to-dma-channel: Channel to map
 	- snps,priority: RX queue priority
+	- Specifiy RX Queue for processing certain types of packets:
+		- snps,avcp-to-queue: AV Untagged Control packets
+		- snps,ptp-to-queue: PTP Packets
+		- snps,dcbcp-to-queue: DCB Control Packets
+		- snps,up-to-queue: Untagged Packets
+		- snps,multi-broad-cast-queue: Multicast & Broadcast Packets
+		- snps,tpqc-queue: Tagged PTPoE Packets Queuing Control. Values:
+			0x0 - Priority based (RX queues non-AV)
+			0x1 - Routes to queue indicated in "snps,ptp-to-queue"
+			0x2 - Priority based (RX queues AV enabled)
 - Multiple TX Queues parameters: below the list of all the parameters to
 				 configure the multiple TX queues:
 	- snps,tx-queues-to-use: number of TX queues to be used in the driver

@@ -112,8 +122,15 @@ Examples:
 	};
 
 	mtl_rx_setup: rx-queues-config {
-		snps,rx-queues-to-use = <1>;
+		snps,rx-queues-to-use = <0>;
 		snps,rx-sched-sp;
+		snps,avcp-to-queue = <0>;
+		snps,ptp-to-queue = <0>;
+		snps,dcbcp-to-queue = <0>;
+		snps,up-to-queue = <0>;
+		snps,multi-broad-cast-queue = <0>;
+		snps,tpqc-queue = <0>;
+
 		queue0 {
 			snps,dcb-algorithm;
 			snps,map-to-dma-channel = <0x0>;

drivers/net/ethernet/stmicro/stmmac/common.h +9 -0

index e0b31e7..e08c4c4 100644
@@ -473,6 +473,15 @@ struct stmmac_ops {
 	void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
 	/* TX Queues Priority */
 	void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
+	/* RX Queues Routing */
+	void (*rx_queue_routing)(struct mac_device_info *hw,
+				 bool route_avcp_enable, u8 route_avcp_queue,
+				 bool route_ptp_enable, u8 route_ptp_queue,
+				 bool route_dcbcp_enable, u8 route_dcbcp_queue,
+				 bool route_up_enable, u8 route_up_queue,
+				 bool route_multi_broad_enable,
+				 u8 route_multi_broad_queue,
+				 bool route_tpqc_enable, u8 route_tpqc_queue);
 	/* Program RX Algorithms */
 	void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
 	/* Program TX Algorithms */

drivers/net/ethernet/stmicro/stmmac/dwmac4.h +18 -0

index a6c382d..93cc3f6 100644
@@ -44,6 +44,24 @@
 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
 #define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
 
+/* RX Queues Routing */
+#define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
+#define GMAC_RXQCTRL_AVCPQ_SHIFT	0
+#define GMAC_RXQCTRL_PTPQ_MASK		GENMASK(6, 4)
+#define GMAC_RXQCTRL_PTPQ_SHIFT		4
+#define GMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(10, 8)
+#define GMAC_RXQCTRL_DCBCPQ_SHIFT	8
+#define GMAC_RXQCTRL_UPQ_MASK		GENMASK(14, 12)
+#define GMAC_RXQCTRL_UPQ_SHIFT		12
+#define GMAC_RXQCTRL_MCBCQ_MASK		GENMASK(18, 16)
+#define GMAC_RXQCTRL_MCBCQ_SHIFT	16
+#define GMAC_RXQCTRL_MCBCQEN		BIT(20)
+#define GMAC_RXQCTRL_MCBCQEN_SHIFT	20
+#define GMAC_RXQCTRL_TACPQE		BIT(21)
+#define GMAC_RXQCTRL_TACPQE_SHIFT	21
+#define GMAC_RXQCTRL_TPQC_MASK		GENMASK(24, 22)
+#define GMAC_RXQCTRL_TPQC_SHIFT		22
+
 /* MAC Packet Filtering */
 #define GMAC_PACKET_FILTER_PR		BIT(0)
 #define GMAC_PACKET_FILTER_HMC		BIT(2)

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +63 -0

75 lines not on this page · raw message

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +25 -0

index 0f2c0d7..07c8ad1 100644
@@ -2333,6 +2333,27 @@ static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
 }
 
 /**
+ *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
+ *  @priv: driver private structure
+ *  Description: It is used for configuring the RX queue routing
+ */
+static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
+{
+	priv->hw->mac->rx_queue_routing(priv->hw, priv->plat->route_avcp_enable,
+					priv->plat->route_avcp_queue,
+					priv->plat->route_ptp_enable,
+					priv->plat->route_ptp_queue,
+					priv->plat->route_dcbcp_enable,
+					priv->plat->route_dcbcp_queue,
+					priv->plat->route_up_enable,
+					priv->plat->route_up_queue,
+					priv->plat->route_multi_broad_enable,
+					priv->plat->route_multi_broad_queue,
+					priv->plat->route_tpqc_enable,
+					priv->plat->route_tpqc_queue);
+}
+
+/**
  *  stmmac_mtl_configuration - Configure MTL
  *  @priv: driver private structure
  *  Description: It is used for configurring MTL

@@ -2377,6 +2398,10 @@ static void stmmac_mtl_configuration(struct stmmac_priv *priv)
 	/* Set TX priorities */
 	if (tx_queues_count > 1 && priv->hw->mac->tx_queue_prio)
 		stmmac_mac_config_tx_queues_prio(priv);
+
+	/* Set RX routing */
+	if (rx_queues_count > 1 && priv->hw->mac->rx_queue_routing)
+		stmmac_mac_config_rx_queues_routing(priv);
 }
 
 /**

drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +8 -0

index ffe4fac..119ff0c 100644
@@ -96,6 +96,14 @@ static void stmmac_default_data(struct plat_stmmacenet_data *plat)
 	/* Disable Priority config by default */
 	plat->tx_queues_cfg[0].use_prio = false;
 	plat->rx_queues_cfg[0].use_prio = false;
+
+	/* Disable RX queues routing by default */
+	plat->route_avcp_enable = false;
+	plat->route_ptp_enable = false;
+	plat->route_dcbcp_enable = false;
+	plat->route_up_enable = false;
+	plat->route_multi_broad_enable = false;
+	plat->route_tpqc_enable = false;
 }
 
 static int quark_default_data(struct plat_stmmacenet_data *plat,

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +49 -0

55 lines not on this page · raw message

include/linux/stmmac.h +12 -0

index b7d5e7a..8f5ebf5 100644
@@ -171,6 +171,18 @@ struct plat_stmmacenet_data {
 	u8 tx_queues_to_use;
 	u8 rx_sched_algorithm;
 	u8 tx_sched_algorithm;
+	bool route_avcp_enable;
+	u8 route_avcp_queue;
+	bool route_ptp_enable;
+	u8 route_ptp_queue;
+	bool route_dcbcp_enable;
+	u8 route_dcbcp_queue;
+	bool route_up_enable;
+	u8 route_up_queue;
+	bool route_multi_broad_enable;
+	u8 route_multi_broad_queue;
+	bool route_tpqc_enable;
+	u8 route_tpqc_queue;
 	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
 	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
 	void (*fix_mac_speed)(void *priv, unsigned int speed);

Signature · 1 line

2.9.3

Florian Fainelli

2017-03-16 16:55 UTC #3 lore raw

Re: [PATCH net-next 2/3] net: stmmac: TX and RX queue priority configuration

In reply to Joao Pinto

Quoted 19 lines · Joao Pinto

This patch adds the configuration of RX and TX queues' priority.

Signed-off-by Joao Pinto <[email protected]>

---
 Documentation/devicetree/bindings/net/stmmac.txt   |  5 +++
 drivers/net/ethernet/stmicro/stmmac/common.h       |  4 ++
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h       | 13 ++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  | 37 +++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 48 ++++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c   |  4 ++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  | 16 ++++++++
 include/linux/stmmac.h                             |  4 ++
 8 files changed, 131 insertions(+)

Documentation/devicetree/bindings/net/stmmac.txt +0 -0

index a7b0e41..b9a9ae9 100644

Documentation/devicetree/bindings/net/stmmac.txt Optional properties: · line 86

Quoted 4 lines

Documentation/devicetree/bindings/net/stmmac.txt +1 -0

@@ -83,6 +83,7 @@ Optional properties:
 			- snps,dcb-algorithm: Queue to be enabled as DCB
 			- snps,avb-algorithm: Queue to be enabled as AVB
 		- snps,map-to-dma-channel: Channel to map
+	- snps,priority: RX queue priority

You need to be more verbose about how this property is constructed and what are the acceptable values: type, size, range.

Signature · 1 line

Florian

Florian Fainelli

2017-03-16 18:08 UTC #6 lore raw

Re: [PATCH net-next 3/3] net: stmmac: RX queue routing configuration

In reply to Joao Pinto

Quoted 25 lines · Joao Pinto

This patch adds the configuration of RX queues' routing.

Signed-off-by Joao Pinto <[email protected]>

---
 Documentation/devicetree/bindings/net/stmmac.txt   | 19 ++++++-
 drivers/net/ethernet/stmicro/stmmac/common.h       |  9 ++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h       | 18 +++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  | 63 ++++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 25 +++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c   |  8 +++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  | 49 +++++++++++++++++
 include/linux/stmmac.h                             | 12 +++++
 8 files changed, 202 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/net/stmmac.txt +3 -0

index b9a9ae9..9c9e774 100644
@@ -84,6 +84,16 @@ Optional properties:
 			- snps,avb-algorithm: Queue to be enabled as AVB
 		- snps,map-to-dma-channel: Channel to map
 	- snps,priority: RX queue priority
+	- Specifiy RX Queue for processing certain types of packets:
+		- snps,avcp-to-queue: AV Untagged Control packets
+		- snps,ptp-to-queue: PTP Packets

Documentation/devicetree/bindings/net/stmmac.txt Optional properties: · line 99

Quoted 10 lines

Documentation/devicetree/bindings/net/stmmac.txt +7 -0

+		- snps,dcbcp-to-queue: DCB Control Packets
+		- snps,up-to-queue: Untagged Packets
+		- snps,multi-broad-cast-queue: Multicast & Broadcast Packets
+		- snps,tpqc-queue: Tagged PTPoE Packets Queuing Control. Values:
+			0x0 - Priority based (RX queues non-AV)
+			0x1 - Routes to queue indicated in "snps,ptp-to-queue"
+			0x2 - Priority based (RX queues AV enabled)
 - Multiple TX Queues parameters: below the list of all the parameters to
 				 configure the multiple TX queues:
 	- snps,tx-queues-to-use: number of TX queues to be used in the driver

You are allowing a policy to be defined with Device Tree here which is usually frowned upon. Can you look into existing facilities offered by tc offloads, e.g: mqprio etc. to allow users to dynamically configure the queue mappings at runtime?

Quoted 78 lines

Documentation/devicetree/bindings/net/stmmac.txt +8 -1

@@ -112,8 +122,15 @@ Examples:
 	};
 
 	mtl_rx_setup: rx-queues-config {
-		snps,rx-queues-to-use = <1>;
+		snps,rx-queues-to-use = <0>;
 		snps,rx-sched-sp;
+		snps,avcp-to-queue = <0>;
+		snps,ptp-to-queue = <0>;
+		snps,dcbcp-to-queue = <0>;
+		snps,up-to-queue = <0>;
+		snps,multi-broad-cast-queue = <0>;
+		snps,tpqc-queue = <0>;
+
 		queue0 {
 			snps,dcb-algorithm;
 			snps,map-to-dma-channel = <0x0>;

drivers/net/ethernet/stmicro/stmmac/common.h +9 -0

index e0b31e7..e08c4c4 100644
@@ -473,6 +473,15 @@ struct stmmac_ops {
 	void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
 	/* TX Queues Priority */
 	void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
+	/* RX Queues Routing */
+	void (*rx_queue_routing)(struct mac_device_info *hw,
+				 bool route_avcp_enable, u8 route_avcp_queue,
+				 bool route_ptp_enable, u8 route_ptp_queue,
+				 bool route_dcbcp_enable, u8 route_dcbcp_queue,
+				 bool route_up_enable, u8 route_up_queue,
+				 bool route_multi_broad_enable,
+				 u8 route_multi_broad_queue,
+				 bool route_tpqc_enable, u8 route_tpqc_queue);
 	/* Program RX Algorithms */
 	void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
 	/* Program TX Algorithms */

drivers/net/ethernet/stmicro/stmmac/dwmac4.h +18 -0

index a6c382d..93cc3f6 100644
@@ -44,6 +44,24 @@
 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
 #define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
 
+/* RX Queues Routing */
+#define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
+#define GMAC_RXQCTRL_AVCPQ_SHIFT	0
+#define GMAC_RXQCTRL_PTPQ_MASK		GENMASK(6, 4)
+#define GMAC_RXQCTRL_PTPQ_SHIFT		4
+#define GMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(10, 8)
+#define GMAC_RXQCTRL_DCBCPQ_SHIFT	8
+#define GMAC_RXQCTRL_UPQ_MASK		GENMASK(14, 12)
+#define GMAC_RXQCTRL_UPQ_SHIFT		12
+#define GMAC_RXQCTRL_MCBCQ_MASK		GENMASK(18, 16)
+#define GMAC_RXQCTRL_MCBCQ_SHIFT	16
+#define GMAC_RXQCTRL_MCBCQEN		BIT(20)
+#define GMAC_RXQCTRL_MCBCQEN_SHIFT	20
+#define GMAC_RXQCTRL_TACPQE		BIT(21)
+#define GMAC_RXQCTRL_TACPQE_SHIFT	21
+#define GMAC_RXQCTRL_TPQC_MASK		GENMASK(24, 22)
+#define GMAC_RXQCTRL_TPQC_SHIFT		22
+
 /* MAC Packet Filtering */
 #define GMAC_PACKET_FILTER_PR		BIT(0)
 #define GMAC_PACKET_FILTER_HMC		BIT(2)

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +4 -0

index 342f62a..8fc1f56 100644
@@ -109,6 +109,68 @@ static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 	writel(value, ioaddr + base_register);
 }
 
+static void dwmac4_tx_queue_routing(struct mac_device_info *hw,
+				    bool route_avcp_enable,
+				    u8 route_avcp_queue,
+				    bool route_ptp_enable,

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c static void dwmac4_tx_queue_priority(struct mac_device_info *hw, · line 125

Quoted 10 lines

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +10 -0

+				    u8 route_ptp_queue,
+				    bool route_dcbcp_enable,
+				    u8 route_dcbcp_queue,
+				    bool route_up_enable,
+				    u8 route_up_queue,
+				    bool route_multi_broad_enable,
+				    u8 route_multi_broad_queue,
+				    bool route_tpqc_enable,
+				    u8 route_tpqc_queue)
+{

This is not looking good at all 13 parameters passed here... thankfully this is not called in a hot path.

So here is what I would suggest:

- put the bool, u8, and masks, shifts, offsets parameters in a structure, define an array of structures holding these variables in your driver's private context, index them with an enumeration for each queue

- pass a reference to this structure here, and iterate over the array of structures and do the programming based on what this structure contains for MASK, SHIFT, base register etc...

Quoted 13 lines

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +5 -0

+	void __iomem *ioaddr = hw->pcsr;
+	u32 value;
+
+	value = readl(ioaddr + GMAC_RXQ_CTRL1);
+
 
 static int quark_default_data(struct plat_stmmacenet_data *plat,

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +0 -0

index 77b0468..5e82379 100644
@@ -165,6 +165,55 @@ static void stmmac_mtl_setup(struct platform_device *pdev,
 	else

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c static void stmmac_mtl_setup(struct platform_device *pdev, · line 175

Quoted 10 lines

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +8 -0

 		plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
 
+	/* RX routing configuration */
+	if (of_property_read_u8(rx_node, "snps,avcp-to-queue",
+				&plat->route_avcp_queue)) {
+		plat->route_avcp_queue = 0;
+		plat->route_avcp_enable = false;
+	} else {
+		plat->route_avcp_enable = true;
+	}

This is very redundant too, see the suggestion above, define an array of property names and look them up in a loop using the queue enumeration.

Quoted 54 lines

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +41 -0

+
+	if (of_property_read_u8(rx_node, "snps,ptp-to-queue",
+				&plat->route_ptp_queue)) {
+		plat->route_ptp_queue = 0;
+		plat->route_ptp_enable = false;
+	} else {
+		plat->route_ptp_enable = true;
+	}
+
+	if (of_property_read_u8(rx_node, "snps,dcbcp-to-queue",
+				&plat->route_dcbcp_queue)) {
+		plat->route_dcbcp_queue = 0;
+		plat->route_dcbcp_enable = false;
+	} else {
+		plat->route_dcbcp_enable = true;
+	}
+
+	if (of_property_read_u8(rx_node, "snps,up-to-queue",
+				&plat->route_up_queue)) {
+		plat->route_up_queue = 0;
+		plat->route_up_enable = false;
+	} else {
+		plat->route_up_enable = true;
+	}
+
+	if (of_property_read_u8(rx_node, "snps,multi-broad-cast-queue",
+				&plat->route_multi_broad_queue)) {
+		plat->route_multi_broad_queue = 0;
+		plat->route_multi_broad_enable = false;
+	} else {
+		plat->route_multi_broad_enable = true;
+	}
+
+	if (of_property_read_u8(rx_node, "snps,tpqc-queue",
+				&plat->route_tpqc_queue)) {
+		plat->route_tpqc_queue = 0;
+		plat->route_tpqc_enable = false;
+	} else {
+		plat->route_tpqc_enable = true;
+	}
+
 	/* Processing individual RX queue config */
 	for_each_child_of_node(rx_node, q_node) {
 		if (queue >= plat->rx_queues_to_use)

include/linux/stmmac.h +2 -0

index b7d5e7a..8f5ebf5 100644
@@ -171,6 +171,18 @@ struct plat_stmmacenet_data {
 	u8 tx_queues_to_use;
 	u8 rx_sched_algorithm;
 	u8 tx_sched_algorithm;
+	bool route_avcp_enable;
+	u8 route_avcp_queue;

include/linux/stmmac.h struct plat_stmmacenet_data { · line 185

Quoted 10 lines

include/linux/stmmac.h +10 -0

+	bool route_ptp_enable;
+	u8 route_ptp_queue;
+	bool route_dcbcp_enable;
+	u8 route_dcbcp_queue;
+	bool route_up_enable;
+	u8 route_up_queue;
+	bool route_multi_broad_enable;
+	u8 route_multi_broad_queue;
+	bool route_tpqc_enable;
+	u8 route_tpqc_queue;

Same here, this absolutely does not scale.

Quoted 4 lines

include/linux/stmmac.h +0 -0

 	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
 	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
 	void (*fix_mac_speed)(void *priv, unsigned int speed);

Signature · 1 line

Florian

Joao Pinto

author

2017-03-17 11:16 UTC #4 lore raw

Re: [PATCH net-next 2/3] net: stmmac: TX and RX queue priority configuration

In reply to Florian Fainelli

Às 4:55 PM de 3/16/2017, Florian Fainelli escreveu:

Quoted 15 lines · Joao Pinto

Quoted 14 lines

This patch adds the configuration of RX and TX queues' priority.

Signed-off-by Joao Pinto <[email protected]>

---
 Documentation/devicetree/bindings/net/stmmac.txt   |  5 +++
 drivers/net/ethernet/stmicro/stmmac/common.h       |  4 ++
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h       | 13 ++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  | 37 +++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 48 ++++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c   |  4 ++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  | 16 ++++++++
 include/linux/stmmac.h                             |  4 ++
 8 files changed, 131 insertions(+)

Quoted 12 lines

Documentation/devicetree/bindings/net/stmmac.txt Optional properties: · line 86
Quoted 9 lines
Documentation/devicetree/bindings/net/stmmac.txt +1 -0
index a7b0e41..b9a9ae9 100644
@@ -83,6 +83,7 @@ Optional properties:
 			- snps,dcb-algorithm: Queue to be enabled as DCB
 			- snps,avb-algorithm: Queue to be enabled as AVB
 		- snps,map-to-dma-channel: Channel to map
+	- snps,priority: RX queue priority
You need to be more verbose about how this property is constructed and what are the acceptable values: type, size, range.

Ok, I will do that. Thanks.

Joao Pinto

author

2017-03-17 11:43 UTC #7 lore raw

Re: [PATCH net-next 3/3] net: stmmac: RX queue routing configuration

In reply to Florian Fainelli

Às 5:12 PM de 3/16/2017, Florian Fainelli escreveu:

Quoted 33 lines · Joao Pinto

Quoted 32 lines

This patch adds the configuration of RX queues' routing.

Signed-off-by Joao Pinto <[email protected]>

---
 Documentation/devicetree/bindings/net/stmmac.txt   | 19 ++++++-
 drivers/net/ethernet/stmicro/stmmac/common.h       |  9 ++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h       | 18 +++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c  | 63 ++++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 25 +++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c   |  8 +++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  | 49 +++++++++++++++++
 include/linux/stmmac.h                             | 12 +++++
 8 files changed, 202 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/net/stmmac.txt +10 -0

index b9a9ae9..9c9e774 100644
@@ -84,6 +84,16 @@ Optional properties:
 			- snps,avb-algorithm: Queue to be enabled as AVB
 		- snps,map-to-dma-channel: Channel to map
 	- snps,priority: RX queue priority
+	- Specifiy RX Queue for processing certain types of packets:
+		- snps,avcp-to-queue: AV Untagged Control packets
+		- snps,ptp-to-queue: PTP Packets
+		- snps,dcbcp-to-queue: DCB Control Packets
+		- snps,up-to-queue: Untagged Packets
+		- snps,multi-broad-cast-queue: Multicast & Broadcast Packets
+		- snps,tpqc-queue: Tagged PTPoE Packets Queuing Control. Values:
+			0x0 - Priority based (RX queues non-AV)
+			0x1 - Routes to queue indicated in "snps,ptp-to-queue"
+			0x2 - Priority based (RX queues AV enabled)

Quoted 8 lines

Documentation/devicetree/bindings/net/stmmac.txt Optional properties: · line 99
Quoted 3 lines
Documentation/devicetree/bindings/net/stmmac.txt +0 -0
 - Multiple TX Queues parameters: below the list of all the parameters to
 				 configure the multiple TX queues:
 	- snps,tx-queues-to-use: number of TX queues to be used in the driver
You are allowing a policy to be defined with Device Tree here which is usually frowned upon. Can you look into existing facilities offered by tc offloads, e.g: mqprio etc. to allow users to dynamically configure the queue mappings at runtime?

We are planning also to have these configurable in runtime by a standard tool like ethtool, but I think we should have the DT possibility also. Makes sense for you?

Quoted 95 lines

Quoted 79 lines

Documentation/devicetree/bindings/net/stmmac.txt +8 -1

@@ -112,8 +122,15 @@ Examples:
 	};
 
 	mtl_rx_setup: rx-queues-config {
-		snps,rx-queues-to-use = <1>;
+		snps,rx-queues-to-use = <0>;
 		snps,rx-sched-sp;
+		snps,avcp-to-queue = <0>;
+		snps,ptp-to-queue = <0>;
+		snps,dcbcp-to-queue = <0>;
+		snps,up-to-queue = <0>;
+		snps,multi-broad-cast-queue = <0>;
+		snps,tpqc-queue = <0>;
+
 		queue0 {
 			snps,dcb-algorithm;
 			snps,map-to-dma-channel = <0x0>;

drivers/net/ethernet/stmicro/stmmac/common.h +9 -0

index e0b31e7..e08c4c4 100644
@@ -473,6 +473,15 @@ struct stmmac_ops {
 	void (*rx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
 	/* TX Queues Priority */
 	void (*tx_queue_prio)(struct mac_device_info *hw, u32 prio, u32 queue);
+	/* RX Queues Routing */
+	void (*rx_queue_routing)(struct mac_device_info *hw,
+				 bool route_avcp_enable, u8 route_avcp_queue,
+				 bool route_ptp_enable, u8 route_ptp_queue,
+				 bool route_dcbcp_enable, u8 route_dcbcp_queue,
+				 bool route_up_enable, u8 route_up_queue,
+				 bool route_multi_broad_enable,
+				 u8 route_multi_broad_queue,
+				 bool route_tpqc_enable, u8 route_tpqc_queue);
 	/* Program RX Algorithms */
 	void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
 	/* Program TX Algorithms */

drivers/net/ethernet/stmicro/stmmac/dwmac4.h +18 -0

index a6c382d..93cc3f6 100644
@@ -44,6 +44,24 @@
 #define GMAC_ADDR_HIGH(reg)		(0x300 + reg * 8)
 #define GMAC_ADDR_LOW(reg)		(0x304 + reg * 8)
 
+/* RX Queues Routing */
+#define GMAC_RXQCTRL_AVCPQ_MASK		GENMASK(2, 0)
+#define GMAC_RXQCTRL_AVCPQ_SHIFT	0
+#define GMAC_RXQCTRL_PTPQ_MASK		GENMASK(6, 4)
+#define GMAC_RXQCTRL_PTPQ_SHIFT		4
+#define GMAC_RXQCTRL_DCBCPQ_MASK	GENMASK(10, 8)
+#define GMAC_RXQCTRL_DCBCPQ_SHIFT	8
+#define GMAC_RXQCTRL_UPQ_MASK		GENMASK(14, 12)
+#define GMAC_RXQCTRL_UPQ_SHIFT		12
+#define GMAC_RXQCTRL_MCBCQ_MASK		GENMASK(18, 16)
+#define GMAC_RXQCTRL_MCBCQ_SHIFT	16
+#define GMAC_RXQCTRL_MCBCQEN		BIT(20)
+#define GMAC_RXQCTRL_MCBCQEN_SHIFT	20
+#define GMAC_RXQCTRL_TACPQE		BIT(21)
+#define GMAC_RXQCTRL_TACPQE_SHIFT	21
+#define GMAC_RXQCTRL_TPQC_MASK		GENMASK(24, 22)
+#define GMAC_RXQCTRL_TPQC_SHIFT		22
+
 /* MAC Packet Filtering */
 #define GMAC_PACKET_FILTER_PR		BIT(0)
 #define GMAC_PACKET_FILTER_HMC		BIT(2)

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +4 -0

index 342f62a..8fc1f56 100644
@@ -109,6 +109,68 @@ static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 	writel(value, ioaddr + base_register);
 }
 
+static void dwmac4_tx_queue_routing(struct mac_device_info *hw,
+				    bool route_avcp_enable,
+				    u8 route_avcp_queue,
+				    bool route_ptp_enable,

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c static void dwmac4_tx_queue_priority(struct mac_device_info *hw, · line 125

Quoted 10 lines

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +10 -0

+				    u8 route_ptp_queue,
+				    bool route_dcbcp_enable,
+				    u8 route_dcbcp_queue,
+				    bool route_up_enable,
+				    u8 route_up_queue,
+				    bool route_multi_broad_enable,
+				    u8 route_multi_broad_queue,
+				    bool route_tpqc_enable,
+				    u8 route_tpqc_queue)
+{

This is not looking good at all 13 parameters passed here... thankfully this is not called in a hot path.

So here is what I would suggest:

Quoted 7 lines

- put the bool, u8, and masks, shifts, offsets parameters in a structure, define an array of structures holding these variables in your driver's private context, index them with an enumeration for each queue
- pass a reference to this structure here, and iterate over the array of structures and do the programming based on what this structure contains for MASK, SHIFT, base register etc...

Good suggestion, I will follow that, thanks.

Quoted 101 lines

Quoted 14 lines

drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +5 -0

+	void __iomem *ioaddr = hw->pcsr;
+	u32 value;
+
+	value = readl(ioaddr + GMAC_RXQ_CTRL1);
+
 
 static int quark_default_data(struct plat_stmmacenet_data *plat,

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +0 -0

index 77b0468..5e82379 100644
@@ -165,6 +165,55 @@ static void stmmac_mtl_setup(struct platform_device *pdev,
 	else

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c static void stmmac_mtl_setup(struct platform_device *pdev, · line 175

Quoted 10 lines

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +8 -0

 		plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
 
+	/* RX routing configuration */
+	if (of_property_read_u8(rx_node, "snps,avcp-to-queue",
+				&plat->route_avcp_queue)) {
+		plat->route_avcp_queue = 0;
+		plat->route_avcp_enable = false;
+	} else {
+		plat->route_avcp_enable = true;
+	}

This is very redundant too, see the suggestion above, define an array of property names and look them up in a loop using the queue enumeration.

Quoted 54 lines

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +41 -0

+
+	if (of_property_read_u8(rx_node, "snps,ptp-to-queue",
+				&plat->route_ptp_queue)) {
+		plat->route_ptp_queue = 0;
+		plat->route_ptp_enable = false;
+	} else {
+		plat->route_ptp_enable = true;
+	}
+
+	if (of_property_read_u8(rx_node, "snps,dcbcp-to-queue",
+				&plat->route_dcbcp_queue)) {
+		plat->route_dcbcp_queue = 0;
+		plat->route_dcbcp_enable = false;
+	} else {
+		plat->route_dcbcp_enable = true;
+	}
+
+	if (of_property_read_u8(rx_node, "snps,up-to-queue",
+				&plat->route_up_queue)) {
+		plat->route_up_queue = 0;
+		plat->route_up_enable = false;
+	} else {
+		plat->route_up_enable = true;
+	}
+
+	if (of_property_read_u8(rx_node, "snps,multi-broad-cast-queue",
+				&plat->route_multi_broad_queue)) {
+		plat->route_multi_broad_queue = 0;
+		plat->route_multi_broad_enable = false;
+	} else {
+		plat->route_multi_broad_enable = true;
+	}
+
+	if (of_property_read_u8(rx_node, "snps,tpqc-queue",
+				&plat->route_tpqc_queue)) {
+		plat->route_tpqc_queue = 0;
+		plat->route_tpqc_enable = false;
+	} else {
+		plat->route_tpqc_enable = true;
+	}
+
 	/* Processing individual RX queue config */
 	for_each_child_of_node(rx_node, q_node) {
 		if (queue >= plat->rx_queues_to_use)

include/linux/stmmac.h +2 -0

index b7d5e7a..8f5ebf5 100644
@@ -171,6 +171,18 @@ struct plat_stmmacenet_data {
 	u8 tx_queues_to_use;
 	u8 rx_sched_algorithm;
 	u8 tx_sched_algorithm;
+	bool route_avcp_enable;
+	u8 route_avcp_queue;

include/linux/stmmac.h struct plat_stmmacenet_data { · line 185

Quoted 10 lines

include/linux/stmmac.h +10 -0

+	bool route_ptp_enable;
+	u8 route_ptp_queue;
+	bool route_dcbcp_enable;
+	u8 route_dcbcp_queue;
+	bool route_up_enable;
+	u8 route_up_queue;
+	bool route_multi_broad_enable;
+	u8 route_multi_broad_queue;
+	bool route_tpqc_enable;
+	u8 route_tpqc_queue;

Same here, this absolutely does not scale.

Quoted 4 lines

include/linux/stmmac.h +0 -0

 	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
 	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
 	void (*fix_mac_speed)(void *priv, unsigned int speed);