Skip to contentSkip to conversation

Introduce DCU support for Vybrid

PATCH New Sanchayan Maity 5 participants 17 messages Apr 11, 2017 – Apr 14, 2017

Subsystems (3)
Arm (32-bit) Arm i.MX and Layerscape Framebuffer layer
lore
Share & tools
lore

Sanchayan Maity

author
#0 lore raw

v3 cover Introduce DCU support for Vybrid

Hello,

This patchset adds support for the Freescale/NXP Display Controller Unit (DCU4) for Vybrid which is found on the LS1021A and Vybrid SoC.

Patch series is based on top of latest u-boot master.

First patch in the series renames existing CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and then converts it to Kconfig. All board defconfigs affected by this patch have been compile tested.

Patch 2-5 introduce incremental changes for supporting DCU on Vybrid.

Patch 6 in the series adds DCU support to Vybrid and has been tested on Toradex Colibri VF61 module.

Will appreciate it if the maintainers or users of LS1021 SoC can test this to check and report regressions if any.

Changes since v2:
1. Rebase on top of latest u-boot master
2. Drop the fourth patch in earlier series and replace it with a fix for DCU_MODE_BLEND_ITER and use the existing DCU_LAYER_MAX_NUM instead of introducing DCU_TOTAL_LAYER_NUM as earlier incoporating Stefan's feedback.

Changes since v1:
1. Rebase of top of latest u-boot master
2. Fix a bug present in v1 patch series which resulted in noisy screen when switching from u-boot to Linux. Patch fixed is second in this series.

v1:
https://lists.denx.de/pipermail/u-boot/2017-February/280281.html

v2:
https://www.mail-archive.com/u-boot at lists.denx.de/msg243132.html

Thanks & Regards,
Sanchayan.

Sanchayan Maity (1):
Convert CONFIG_FSL_DCU_FB to Kconfig

Stefan Agner (5):
video: fsl_dcu_fb: fix framebuffer to the end of memory
video: fsl_dcu_fb: Enable pixel clock after initialization
video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER setting
video: fsl_dcu_fb: add additional modes for DCU
board: toradex: colibri_vf: Add DCU support for Colibri Vybrid

 arch/arm/cpu/armv7/ls102xa/soc.c                   |   2 +-
 arch/arm/include/asm/arch-vf610/crm_regs.h         |  14 +++
 arch/arm/include/asm/arch-vf610/imx-regs.h         |   2 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h      |  31 ++++++
 arch/arm/include/asm/imx-common/iomux-v3.h         |   3 +
 board/freescale/ls1021aiot/Makefile                |   2 +-
 board/freescale/ls1021aqds/Makefile                |   2 +-
 board/freescale/ls1021atwr/Makefile                |   2 +-
 board/toradex/colibri_vf/Makefile                  |   1 +
 board/toradex/colibri_vf/colibri_vf.c              |  76 ++++++++++---
 board/toradex/colibri_vf/dcu.c                     |  38 +++++++
 configs/colibri_vf_defconfig                       |   4 +
 configs/ls1021aqds_ddr4_nor_defconfig              |   1 +
 configs/ls1021aqds_ddr4_nor_lpuart_defconfig       |   1 +
 configs/ls1021aqds_nand_defconfig                  |   1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig       |   1 +
 configs/ls1021aqds_nor_defconfig                   |   1 +
 configs/ls1021aqds_nor_lpuart_defconfig            |   1 +
 configs/ls1021aqds_qspi_defconfig                  |   1 +
 configs/ls1021aqds_sdcard_ifc_defconfig            |   1 +
 configs/ls1021aqds_sdcard_qspi_defconfig           |   1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig       |   1 +
 configs/ls1021atwr_nor_defconfig                   |   1 +
 configs/ls1021atwr_nor_lpuart_defconfig            |   1 +
 configs/ls1021atwr_qspi_defconfig                  |   1 +
 .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig    |   1 +
 configs/ls1021atwr_sdcard_ifc_defconfig            |   1 +
 configs/ls1021atwr_sdcard_qspi_defconfig           |   1 +
 drivers/video/Kconfig                              |  15 +++
 drivers/video/Makefile                             |   2 +-
 drivers/video/fsl_dcu_fb.c                         | 121 ++++++++++++++++++---
 include/configs/colibri_vf.h                       |  13 +++
 include/configs/ls1021aqds.h                       |   4 +-
 include/configs/ls1021atwr.h                       |   4 +-
 include/fsl_dcu_fb.h                               |   1 +
 scripts/config_whitelist.txt                       |   1 -
 36 files changed, 313 insertions(+), 41 deletions(-)
 create mode 100644 board/toradex/colibri_vf/dcu.c
Signature · 1 line
2.12.2
author
#1 lore raw

PATCH v3 1/6 Convert CONFIG_FSL_DCU_FB to Kconfig

Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig.

Signed-off-by Sanchayan Maity <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                    | 2 +-
 board/freescale/ls1021aiot/Makefile                 | 2 +-
 board/freescale/ls1021aqds/Makefile                 | 2 +-
 board/freescale/ls1021atwr/Makefile                 | 2 +-
 configs/ls1021aqds_ddr4_nor_defconfig               | 1 +
 configs/ls1021aqds_ddr4_nor_lpuart_defconfig        | 1 +
 configs/ls1021aqds_nand_defconfig                   | 1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig        | 1 +
 configs/ls1021aqds_nor_defconfig                    | 1 +
 configs/ls1021aqds_nor_lpuart_defconfig             | 1 +
 configs/ls1021aqds_qspi_defconfig                   | 1 +
 configs/ls1021aqds_sdcard_ifc_defconfig             | 1 +
 configs/ls1021aqds_sdcard_qspi_defconfig            | 1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig        | 1 +
 configs/ls1021atwr_nor_defconfig                    | 1 +
 configs/ls1021atwr_nor_lpuart_defconfig             | 1 +
 configs/ls1021atwr_qspi_defconfig                   | 1 +
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
 configs/ls1021atwr_sdcard_ifc_defconfig             | 1 +
 configs/ls1021atwr_sdcard_qspi_defconfig            | 1 +
 drivers/video/Kconfig                               | 7 +++++++
 drivers/video/Makefile                              | 2 +-
 include/configs/ls1021aqds.h                        | 4 +---
 include/configs/ls1021atwr.h                        | 4 +---
 scripts/config_whitelist.txt                        | 1 -
 25 files changed, 30 insertions(+), 12 deletions(-)
arch/arm/cpu/armv7/ls102xa/soc.c +1 -1
index 52fb6f8d51..b84a1a686a 100644
@@ -91,7 +91,7 @@ int arch_soc_init(void)
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 #endif
board/freescale/ls1021aiot/Makefile +1 -1
index 05709e685c..6b960aa61c 100644
@@ -5,5 +5,5 @@
 #
 
 obj-y += ls1021aiot.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
board/freescale/ls1021aqds/Makefile +1 -1
index f0390c129f..1e50e468a3 100644
@@ -7,5 +7,5 @@
 obj-y += ls1021aqds.o
 obj-y += ddr.o
 obj-y += eth.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
board/freescale/ls1021atwr/Makefile +1 -1
index 5238b158d7..d9a2f52f2b 100644
@@ -5,5 +5,5 @@
 #
 
 obj-y += ls1021atwr.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
configs/ls1021aqds_ddr4_nor_defconfig +1 -0
index 8434870af3..5566053ae9 100644
@@ -43,3 +43,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_ddr4_nor_lpuart_defconfig +1 -0
index ece220bf94..9582662e53 100644
@@ -44,3 +44,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_nand_defconfig +1 -0
index dc547b5e0d..73f2fb070d 100644
@@ -57,3 +57,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_nor_SECURE_BOOT_defconfig +1 -0
index d1760ed742..74e1241974 100644
@@ -43,5 +43,6 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
configs/ls1021aqds_nor_defconfig +1 -0
index 8de90b0757..14a2b7f562 100644
@@ -44,3 +44,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_nor_lpuart_defconfig +1 -0
index a9efdc56ac..9ed301cedd 100644
@@ -45,3 +45,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_qspi_defconfig +1 -0
index 735f517cf9..9ec21c58a3 100644
@@ -50,3 +50,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_sdcard_ifc_defconfig +1 -0
index 027d368157..492676a2c1 100644
@@ -55,3 +55,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_sdcard_qspi_defconfig +1 -0
index f9ea99bac1..ed0b17be7c 100644
@@ -61,3 +61,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_nor_SECURE_BOOT_defconfig +1 -0
index 5b6ca220b3..6af8dbd928 100644
@@ -42,5 +42,6 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
configs/ls1021atwr_nor_defconfig +1 -0
index 3fb507f18c..93b646796b 100644
@@ -42,3 +42,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_nor_lpuart_defconfig +1 -0
index 725720d3f4..c176e8377a 100644
@@ -43,3 +43,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_qspi_defconfig +1 -0
index 46f7e26d8f..548d574fa0 100644
@@ -50,3 +50,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +1 -0
index 783787afff..bd001700a5 100644
@@ -57,5 +57,6 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
configs/ls1021atwr_sdcard_ifc_defconfig +1 -0
index b558e838fa..107011163c 100644
@@ -54,3 +54,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_sdcard_qspi_defconfig +1 -0
index ef073759ba..5eddabd020 100644
@@ -61,3 +61,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
drivers/video/Kconfig +7 -0
index 2069576958..6aab8af1b3 100644
@@ -395,6 +395,13 @@ config VIDEO_IVYBRIDGE_IGD
 	  a special tool which configures the VGA ROM, but the graphics
 	  resolution can be selected in U-Boot.
 
+config VIDEO_FSL_DCU_FB
+	bool "Enable Freescale Display Control Unit"
+	depends on VIDEO
+	help
+	 This enables support for Freescale Display Control Unit (DCU4)
+	 module found on Freescale Vybrid and QorIQ family of SoCs.
+
 config VIDEO_ROCKCHIP
 	bool "Enable Rockchip video support"
 	depends on DM_VIDEO
drivers/video/Makefile +1 -1
index db34904a9a..7cd6d28658 100644
@@ -27,7 +27,7 @@ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
 obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
-obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
 obj-$(CONFIG_L5F31188) += l5f31188.o
 obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
include/configs/ls1021aqds.h +1 -3
index b349b367eb..97b81274b0 100644
@@ -421,9 +421,7 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Video
  */
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_CMD_BMP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
include/configs/ls1021atwr.h +1 -3
index fcf035b86a..a60b4b2990 100644
@@ -300,9 +300,7 @@
 /*
  * Video
  */
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_CMD_BMP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
scripts/config_whitelist.txt +0 -1
index 330bc5897a..9d238bd443 100644
@@ -1041,7 +1041,6 @@ CONFIG_FSLDMAFEC
 CONFIG_FSL_CADMUS
 CONFIG_FSL_CORENET
 CONFIG_FSL_CPLD
-CONFIG_FSL_DCU_FB
 CONFIG_FSL_DCU_SII9022A
 CONFIG_FSL_DDR_BIST
 CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
Signature · 1 line
2.12.2
author
#4 lore raw

PATCH v3 2/6 video: fsl_dcu_fb: fix framebuffer to the end of memory

In reply to Sanchayan Maity

From: Stefan Agner <[email protected]>

Fix the framebuffer location to the very end of the available memory. This allows to remove the area from available memory for the kernel, which in turn allows to display the splash screen through the while Linux kernel boot process.

Ideas has been taken from the sunxi display driver, e.g. 20779ec3a5 ("sunxi: video: Dynamically reserve framebuffer memory")

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 drivers/video/Kconfig      |  8 ++++++++
 drivers/video/fsl_dcu_fb.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
 include/fsl_dcu_fb.h       |  1 +
 3 files changed, 51 insertions(+), 3 deletions(-)
drivers/video/Kconfig +8 -0
index 6aab8af1b3..d1b017cfad 100644
@@ -402,6 +402,14 @@ config VIDEO_FSL_DCU_FB
 	 This enables support for Freescale Display Control Unit (DCU4)
 	 module found on Freescale Vybrid and QorIQ family of SoCs.
 
+config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
+	int "Freescale DCU framebuffer size"
+	depends on VIDEO_FSL_DCU_FB
+	default 4194304
+	help
+	 Set maximum framebuffer size to be used for Freescale Display
+	 Controller Unit (DCU4).
+
 config VIDEO_ROCKCHIP
 	bool "Enable Rockchip video support"
 	depends on DM_VIDEO
drivers/video/fsl_dcu_fb.c +42 -3

74 lines not on this page · raw message

include/fsl_dcu_fb.h +1 -0
index 42632984d3..67e29e74e6 100644
@@ -9,6 +9,7 @@
 
 int fsl_dcu_init(unsigned int xres, unsigned int yres,
 		 unsigned int pixel_format);
+int fsl_dcu_fixedfb_setup(void *blob);
 
 /* Prototypes for external board-specific functions */
 int platform_dcu_init(unsigned int xres, unsigned int yres,
Signature · 1 line
2.12.2
author
#5 lore raw

PATCH v3 3/6 video: fsl_dcu_fb: Enable pixel clock after initialization

In reply to Sanchayan Maity

From: Stefan Agner <[email protected]>

When enabling the DCU and pixel clock, the test mode is activated since this is the reset configuration. The test mode immediately shows a red screen on a LCD. A moment later, the DCU gets initialized properly.

This patch enables the pixel clock after initialization of the DCU control register. This avoids this initial flicker on LCD screens.

While at it change the polarity of pixel clock to display samples data on the rising edge.

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 drivers/video/fsl_dcu_fb.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)
drivers/video/fsl_dcu_fb.c +6 -7
index 801bf3db95..a922a91fb2 100644
@@ -41,7 +41,7 @@
 #define DCU_VSYN_PARA_BP(x)		((x) << 22)
 #define DCU_VSYN_PARA_PW(x)		((x) << 11)
 #define DCU_VSYN_PARA_FP(x)		(x)
-#define DCU_SYN_POL_INV_PXCK_FALL	(0 << 6)
+#define DCU_SYN_POL_INV_PXCK_FALL	(1 << 6)
 #define DCU_SYN_POL_NEG_REMAIN		(0 << 5)
 #define DCU_SYN_POL_INV_VS_LOW		(1 << 1)
 #define DCU_SYN_POL_INV_HS_LOW		(1)

@@ -191,8 +191,6 @@ static void reset_total_layers(void)
 		dcu_write32(&regs->ctrldescl[i][9], 0);
 		dcu_write32(&regs->ctrldescl[i][10], 0);
 	}
-
-	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
 }
 
 static int layer_ctrldesc_init(int index, u32 pixel_format)

@@ -246,8 +244,6 @@ static int layer_ctrldesc_init(int index, u32 pixel_format)
 	dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
 	dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
 
-	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
-
 	return 0;
 }
 

@@ -273,8 +269,6 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
 	memset(info.screen_base, 0, info.screen_size);
 
 	reset_total_layers();
-	div = dcu_set_pixel_clock(info.var.pixclock);
-	dcu_write32(&regs->div_ratio, (div - 1));
 
 	dcu_write32(&regs->disp_size,
 		    DCU_DISP_SIZE_DELTA_Y(info.var.yres) |

@@ -313,6 +307,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
 
 	layer_ctrldesc_init(0, pixel_format);
 
+	div = dcu_set_pixel_clock(info.var.pixclock);
+	dcu_write32(&regs->div_ratio, (div - 1));
+
+	dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
+
 	return 0;
 }
Signature · 1 line
2.12.2
author
#7 lore raw

PATCH v3 4/6 video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER setting

In reply to Sanchayan Maity

From: Stefan Agner <[email protected]>

DCU_LAYER_MAX_NUM is currently used for DCU_MODE_BLEND_ITER and it actually overflows the maximum value of BLEND_ITER for Vybrid and LS102XA. Fix this by using a default value of 2.

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 drivers/video/fsl_dcu_fb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/video/fsl_dcu_fb.c +1 -1
index a922a91fb2..6e65d84903 100644
@@ -294,7 +294,7 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
 		    DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
 
 	dcu_write32(&regs->mode,
-		    DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) |
+		    DCU_MODE_BLEND_ITER(2) |
 		    DCU_MODE_RASTER_EN);
 
 	dcu_write32(&regs->threshold,
Signature · 1 line
2.12.2
author
#8 lore raw

PATCH v3 5/6 video: fsl_dcu_fb: add additional modes for DCU

In reply to Sanchayan Maity

From: Stefan Agner <[email protected]>

Add common widescreen modes 800x480 and 1024x600.

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 drivers/video/fsl_dcu_fb.c | 61 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 59 insertions(+), 2 deletions(-)
drivers/video/fsl_dcu_fb.c +59 -2
index 6e65d84903..85f98dc73c 100644
@@ -104,7 +104,7 @@ static struct fb_videomode fsl_dcu_mode_480_272 = {
 /*
  * This setting is used for Siliconimage SiI9022A HDMI
  */
-static struct fb_videomode fsl_dcu_mode_640_480 = {
+static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
 	.name		= "640x480-60",
 	.refresh	= 60,
 	.xres		= 640,

@@ -120,6 +120,54 @@ static struct fb_videomode fsl_dcu_mode_640_480 = {
 	.vmode		= FB_VMODE_NONINTERLACED,
 };
 
+static struct fb_videomode fsl_dcu_mode_640_480 = {
+	.name		= "640x480-60",
+	.refresh	= 60,
+	.xres		= 640,
+	.yres		= 480,
+	.pixclock	= 25175,
+	.left_margin	= 40,
+	.right_margin	= 24,
+	.upper_margin	= 32,
+	.lower_margin	= 11,
+	.hsync_len	= 96,
+	.vsync_len	= 2,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_800_480 = {
+	.name		= "800x480-60",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 33260,
+	.left_margin	= 216,
+	.right_margin	= 40,
+	.upper_margin	= 35,
+	.lower_margin	= 10,
+	.hsync_len	= 128,
+	.vsync_len	= 2,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_videomode fsl_dcu_mode_1024_600 = {
+	.name		= "1024x600-60",
+	.refresh	= 60,
+	.xres		= 1024,
+	.yres		= 600,
+	.pixclock	= 48000,
+	.left_margin	= 104,
+	.right_margin	= 43,
+	.upper_margin	= 24,
+	.lower_margin	= 20,
+	.hsync_len	= 5,
+	.vsync_len	= 5,
+	.sync		= 0,
+	.vmode		= FB_VMODE_NONINTERLACED,
+};
+
 /*
  * DCU register map
  */

@@ -342,7 +390,16 @@ void *video_hw_init(void)
 		fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
 		break;
 	case RESOLUTION(640, 480):
-		fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+		if (!strncmp(options, "monitor=hdmi", 12))
+			fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
+		else
+			fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
+		break;
+	case RESOLUTION(800, 480):
+		fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
+		break;
+	case RESOLUTION(1024, 600):
+		fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
 		break;
 	default:
 		printf("unsupported resolution %ux%u\n",
Signature · 1 line
2.12.2
author
#10 lore raw

PATCH v3 6/6 board: toradex: colibri_vf: Add DCU support for Colibri Vybrid

In reply to Sanchayan Maity

From: Stefan Agner <[email protected]>

The Vybrid SoC family has the same display controller unit (DCU) like the LS1021A SoC. This patch adds platform data, pinmux defines and clock control to enable the driver for Toradex Colibri Vybrid module.

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 arch/arm/include/asm/arch-vf610/crm_regs.h    | 14 +++++
 arch/arm/include/asm/arch-vf610/imx-regs.h    |  2 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 +++++++++++
 arch/arm/include/asm/imx-common/iomux-v3.h    |  3 ++
 board/toradex/colibri_vf/Makefile             |  1 +
 board/toradex/colibri_vf/colibri_vf.c         | 76 +++++++++++++++++++++------
 board/toradex/colibri_vf/dcu.c                | 38 ++++++++++++++
 configs/colibri_vf_defconfig                  |  4 ++
 include/configs/colibri_vf.h                  | 13 +++++
 9 files changed, 166 insertions(+), 16 deletions(-)
 create mode 100644 board/toradex/colibri_vf/dcu.c
arch/arm/include/asm/arch-vf610/crm_regs.h +14 -0
index a46e396f1d..73b1dd2f14 100644
@@ -9,6 +9,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/types.h>
+
 /* Clock Controller Module (CCM) */
 struct ccm_reg {
 	u32 ccr;

@@ -150,6 +152,9 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
 
+#define CCM_CSCMR1_DCU1_CLK_SEL			(1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL			(1 << 28)
+
 #define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
 #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
 #define CCM_CSCMR1_QSPI0_CLK_SEL(v)		(((v) & 0x3) << 22)

@@ -174,6 +179,13 @@ struct anadig_reg {
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_DCU1_EN			(1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK		(0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v)			(((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN			(1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK		(0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v)			(((v) & 0x7) << 16)
+
 #define CCM_CSCDR3_NFC_PRE_DIV_OFFSET		13
 #define CCM_CSCDR3_NFC_PRE_DIV_MASK		(0x7 << 13)
 #define CCM_CSCDR3_NFC_PRE_DIV(v)		(((v) & 0x7) << 13)

@@ -193,6 +205,7 @@ struct anadig_reg {
 #define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)

@@ -203,6 +216,7 @@ struct anadig_reg {
 #define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
 #define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
arch/arm/include/asm/arch-vf610/imx-regs.h +2 -0
index cac68efde2..ca97462c35 100644
@@ -69,6 +69,7 @@
 #define USB_PHY0_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050800)
 #define USB_PHY1_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050C00)
 #define SCSC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00058000)
 #define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
 #define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)

@@ -98,6 +99,7 @@
 #define USBC1_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00034000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00058000)
 #define NFC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00060000)
 
 #define QSPI0_AMBA_BASE		0x20000000
arch/arm/include/asm/arch-vf610/iomux-vf610.h +31 -0
index a140be05f1..5af071a4db 100644
@@ -40,6 +40,8 @@
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
 #define VF610_DSPI_SIN_PAD_CTRL	(PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DCU_PAD_CTRL     (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE)
 
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),

@@ -166,6 +168,35 @@ enum {
 
 	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
+	VF610_PAD_PTE0__DCU0_HSYNC		= IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE1__DCU0_VSYNC		= IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE2__DCU0_PCLK		= IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE4__DCU0_DE			= IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE5__DCU0_R0			= IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE6__DCU0_R1			= IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE7__DCU0_R2			= IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE8__DCU0_R3			= IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE9__DCU0_R4			= IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE10__DCU0_R5		= IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE11__DCU0_R6		= IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE12__DCU0_R7		= IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE13__DCU0_G0		= IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE14__DCU0_G1		= IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE15__DCU0_G2		= IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE16__DCU0_G3		= IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE17__DCU0_G4		= IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE18__DCU0_G5		= IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE19__DCU0_G6		= IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE20__DCU0_G7		= IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE21__DCU0_B0		= IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE22__DCU0_B1		= IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE23__DCU0_B2		= IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE24__DCU0_B3		= IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE25__DCU0_B4		= IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE26__DCU0_B5		= IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE27__DCU0_B6		= IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE28__DCU0_B7		= IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+
 	VF610_PAD_DDR_RESETB			= IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
arch/arm/include/asm/imx-common/iomux-v3.h +3 -0
index 7587cbbf95..ba0ed43811 100644
@@ -165,7 +165,10 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_ODE		(1 << 10)
 
 #define PAD_CTL_DSE_150ohm	(1 << 6)
+#define PAD_CTL_DSE_75ohm	(2 << 6)
 #define PAD_CTL_DSE_50ohm	(3 << 6)
+#define PAD_CTL_DSE_37ohm	(4 << 6)
+#define PAD_CTL_DSE_30ohm	(5 << 6)
 #define PAD_CTL_DSE_25ohm	(6 << 6)
 #define PAD_CTL_DSE_20ohm	(7 << 6)
board/toradex/colibri_vf/Makefile +1 -0
index c7e5134ba1..4d6287f14a 100644
@@ -5,3 +5,4 @@
 #
 
 obj-y	:= colibri_vf.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
board/toradex/colibri_vf/colibri_vf.c +60 -16

118 lines not on this page · raw message

board/toradex/colibri_vf/dcu.c new file +38 -0
new file mode 100644
index 0000000000..3fa6a763d8
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * FSL DCU platform driver
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	unsigned long long div;
+
+	clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
+	clrsetbits_le32(&ccm->cscdr3,
+			CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
+			CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
+	div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
+	do_div(div, pixclock);
+
+	return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	fsl_dcu_init(xres, yres, 32);
+
+	return 0;
+}
configs/colibri_vf_defconfig +4 -0
index 0474abc3c5..1f0f929ce5 100644
@@ -52,3 +52,7 @@ CONFIG_G_DNL_MANUFACTURER="Toradex"
 CONFIG_G_DNL_VENDOR_NUM=0x1b67
 CONFIG_G_DNL_PRODUCT_NUM=0x4000
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_FSL_DCU_FB=y
+CONFIG_SYS_CONSOLE_FG_COL=0x00
+CONFIG_SYS_CONSOLE_BG_COL=0x00
include/configs/colibri_vf.h +13 -0
index 73b43bd7ad..5dc5ed0b71 100644
@@ -25,6 +25,17 @@
 #define CONFIG_MXC_OCOTP
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_FSL_DCU_LE
+
+#define CONFIG_SYS_DCU_ADDR		DCU0_BASE_ADDR
+#define DCU_LAYER_MAX_NUM		64
+#endif
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 

@@ -130,6 +141,8 @@
 	"setupdate=run setsdupdate || run setusbupdate\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+	"video-mode=dcufb:640x480-16 at 60,monitor=lcd\0" \
+	"splashpos=m,m\0" \
 	SD_BOOTCMD \
 	NFS_BOOTCMD \
 	UBI_BOOTCMD
Signature · 1 line
2.12.2
#2 lore raw

PATCH v3 1/6 Convert CONFIG_FSL_DCU_FB to Kconfig

In reply to Sanchayan Maity
Quoted 2 lines · Sanchayan Maity

Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig.

Looks good to me.

Reviewed-by Stefan Agner <[email protected]>

--
Stefan

Quoted 316 lines
Signed-off-by Sanchayan Maity <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                    | 2 +-
 board/freescale/ls1021aiot/Makefile                 | 2 +-
 board/freescale/ls1021aqds/Makefile                 | 2 +-
 board/freescale/ls1021atwr/Makefile                 | 2 +-
 configs/ls1021aqds_ddr4_nor_defconfig               | 1 +
 configs/ls1021aqds_ddr4_nor_lpuart_defconfig        | 1 +
 configs/ls1021aqds_nand_defconfig                   | 1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig        | 1 +
 configs/ls1021aqds_nor_defconfig                    | 1 +
 configs/ls1021aqds_nor_lpuart_defconfig             | 1 +
 configs/ls1021aqds_qspi_defconfig                   | 1 +
 configs/ls1021aqds_sdcard_ifc_defconfig             | 1 +
 configs/ls1021aqds_sdcard_qspi_defconfig            | 1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig        | 1 +
 configs/ls1021atwr_nor_defconfig                    | 1 +
 configs/ls1021atwr_nor_lpuart_defconfig             | 1 +
 configs/ls1021atwr_qspi_defconfig                   | 1 +
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
 configs/ls1021atwr_sdcard_ifc_defconfig             | 1 +
 configs/ls1021atwr_sdcard_qspi_defconfig            | 1 +
 drivers/video/Kconfig                               | 7 +++++++
 drivers/video/Makefile                              | 2 +-
 include/configs/ls1021aqds.h                        | 4 +---
 include/configs/ls1021atwr.h                        | 4 +---
 scripts/config_whitelist.txt                        | 1 -
 25 files changed, 30 insertions(+), 12 deletions(-)
arch/arm/cpu/armv7/ls102xa/soc.c +1 -1
index 52fb6f8d51..b84a1a686a 100644
@@ -91,7 +91,7 @@ int arch_soc_init(void)
 	out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 #endif
board/freescale/ls1021aiot/Makefile +1 -1
index 05709e685c..6b960aa61c 100644
@@ -5,5 +5,5 @@
 #
 
 obj-y += ls1021aiot.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
board/freescale/ls1021aqds/Makefile +1 -1
index f0390c129f..1e50e468a3 100644
@@ -7,5 +7,5 @@
 obj-y += ls1021aqds.o
 obj-y += ddr.o
 obj-y += eth.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
board/freescale/ls1021atwr/Makefile +1 -1
index 5238b158d7..d9a2f52f2b 100644
@@ -5,5 +5,5 @@
 #
 
 obj-y += ls1021atwr.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
configs/ls1021aqds_ddr4_nor_defconfig +1 -0
index 8434870af3..5566053ae9 100644
@@ -43,3 +43,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_ddr4_nor_lpuart_defconfig +1 -0
index ece220bf94..9582662e53 100644
@@ -44,3 +44,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_nand_defconfig +1 -0
index dc547b5e0d..73f2fb070d 100644
@@ -57,3 +57,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_nor_SECURE_BOOT_defconfig +1 -0
index d1760ed742..74e1241974 100644
@@ -43,5 +43,6 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
configs/ls1021aqds_nor_defconfig +1 -0
index 8de90b0757..14a2b7f562 100644
@@ -44,3 +44,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_nor_lpuart_defconfig +1 -0
index a9efdc56ac..9ed301cedd 100644
@@ -45,3 +45,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_qspi_defconfig +1 -0
index 735f517cf9..9ec21c58a3 100644
@@ -50,3 +50,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_sdcard_ifc_defconfig +1 -0
index 027d368157..492676a2c1 100644
@@ -55,3 +55,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021aqds_sdcard_qspi_defconfig +1 -0
index f9ea99bac1..ed0b17be7c 100644
@@ -61,3 +61,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_nor_SECURE_BOOT_defconfig +1 -0
index 5b6ca220b3..6af8dbd928 100644
@@ -42,5 +42,6 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
configs/ls1021atwr_nor_defconfig +1 -0
index 3fb507f18c..93b646796b 100644
@@ -42,3 +42,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_nor_lpuart_defconfig +1 -0
index 725720d3f4..c176e8377a 100644
@@ -43,3 +43,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_qspi_defconfig +1 -0
index 46f7e26d8f..548d574fa0 100644
@@ -50,3 +50,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +1 -0
index 783787afff..bd001700a5 100644
@@ -57,5 +57,6 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
configs/ls1021atwr_sdcard_ifc_defconfig +1 -0
index b558e838fa..107011163c 100644
@@ -54,3 +54,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
configs/ls1021atwr_sdcard_qspi_defconfig +1 -0
index ef073759ba..5eddabd020 100644
@@ -61,3 +61,4 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_VIDEO_FSL_DCU_FB=y
drivers/video/Kconfig +7 -0
index 2069576958..6aab8af1b3 100644
@@ -395,6 +395,13 @@ config VIDEO_IVYBRIDGE_IGD
 	  a special tool which configures the VGA ROM, but the graphics
 	  resolution can be selected in U-Boot.
 
+config VIDEO_FSL_DCU_FB
+	bool "Enable Freescale Display Control Unit"
+	depends on VIDEO
+	help
+	 This enables support for Freescale Display Control Unit (DCU4)
+	 module found on Freescale Vybrid and QorIQ family of SoCs.
+
 config VIDEO_ROCKCHIP
 	bool "Enable Rockchip video support"
 	depends on DM_VIDEO
drivers/video/Makefile +1 -1
index db34904a9a..7cd6d28658 100644
@@ -27,7 +27,7 @@ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
 obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
-obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
 obj-$(CONFIG_L5F31188) += l5f31188.o
 obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
 obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
include/configs/ls1021aqds.h +1 -3
index b349b367eb..97b81274b0 100644
@@ -421,9 +421,7 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Video
  */
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_CMD_BMP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
include/configs/ls1021atwr.h +1 -3
index fcf035b86a..a60b4b2990 100644
@@ -300,9 +300,7 @@
 /*
  * Video
  */
-#define CONFIG_FSL_DCU_FB
-
-#ifdef CONFIG_FSL_DCU_FB
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
 #define CONFIG_CMD_BMP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
scripts/config_whitelist.txt +0 -1
index 330bc5897a..9d238bd443 100644
@@ -1041,7 +1041,6 @@ CONFIG_FSLDMAFEC
 CONFIG_FSL_CADMUS
 CONFIG_FSL_CORENET
 CONFIG_FSL_CPLD
-CONFIG_FSL_DCU_FB
 CONFIG_FSL_DCU_SII9022A
 CONFIG_FSL_DDR_BIST
 CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#14 lore raw

v3 cover Introduce DCU support for Vybrid

In reply to Sanchayan Maity

Stefano,

This patchset has been on the ML for a quite a while, any chance to get this still into v2017.05?

--
Stefan

Quoted 87 lines · Sanchayan Maity

Hello,

This patchset adds support for the Freescale/NXP Display Controller Unit (DCU4) for Vybrid which is found on the LS1021A and Vybrid SoC.

Patch series is based on top of latest u-boot master.

First patch in the series renames existing CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and then converts it to Kconfig. All board defconfigs affected by this patch have been compile tested.

Patch 2-5 introduce incremental changes for supporting DCU on Vybrid.

Patch 6 in the series adds DCU support to Vybrid and has been tested on Toradex Colibri VF61 module.

Will appreciate it if the maintainers or users of LS1021 SoC can test this to check and report regressions if any.

Changes since v2:
1. Rebase on top of latest u-boot master
2. Drop the fourth patch in earlier series and replace it with a fix for DCU_MODE_BLEND_ITER and use the existing DCU_LAYER_MAX_NUM instead of introducing DCU_TOTAL_LAYER_NUM as earlier incoporating Stefan's feedback.

Changes since v1:
1. Rebase of top of latest u-boot master
2. Fix a bug present in v1 patch series which resulted in noisy screen when switching from u-boot to Linux. Patch fixed is second in this series.

v1:
https://lists.denx.de/pipermail/u-boot/2017-February/280281.html

v2:
https://www.mail-archive.com/u-boot at lists.denx.de/msg243132.html

Thanks & Regards,
Sanchayan.

Sanchayan Maity (1):
Convert CONFIG_FSL_DCU_FB to Kconfig

Stefan Agner (5):
video: fsl_dcu_fb: fix framebuffer to the end of memory
video: fsl_dcu_fb: Enable pixel clock after initialization
video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER setting
video: fsl_dcu_fb: add additional modes for DCU
board: toradex: colibri_vf: Add DCU support for Colibri Vybrid

 arch/arm/cpu/armv7/ls102xa/soc.c                   |   2 +-
 arch/arm/include/asm/arch-vf610/crm_regs.h         |  14 +++
 arch/arm/include/asm/arch-vf610/imx-regs.h         |   2 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h      |  31 ++++++
 arch/arm/include/asm/imx-common/iomux-v3.h         |   3 +
 board/freescale/ls1021aiot/Makefile                |   2 +-
 board/freescale/ls1021aqds/Makefile                |   2 +-
 board/freescale/ls1021atwr/Makefile                |   2 +-
 board/toradex/colibri_vf/Makefile                  |   1 +
 board/toradex/colibri_vf/colibri_vf.c              |  76 ++++++++++---
 board/toradex/colibri_vf/dcu.c                     |  38 +++++++
 configs/colibri_vf_defconfig                       |   4 +
 configs/ls1021aqds_ddr4_nor_defconfig              |   1 +
 configs/ls1021aqds_ddr4_nor_lpuart_defconfig       |   1 +
 configs/ls1021aqds_nand_defconfig                  |   1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig       |   1 +
 configs/ls1021aqds_nor_defconfig                   |   1 +
 configs/ls1021aqds_nor_lpuart_defconfig            |   1 +
 configs/ls1021aqds_qspi_defconfig                  |   1 +
 configs/ls1021aqds_sdcard_ifc_defconfig            |   1 +
 configs/ls1021aqds_sdcard_qspi_defconfig           |   1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig       |   1 +
 configs/ls1021atwr_nor_defconfig                   |   1 +
 configs/ls1021atwr_nor_lpuart_defconfig            |   1 +
 configs/ls1021atwr_qspi_defconfig                  |   1 +
 .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig    |   1 +
 configs/ls1021atwr_sdcard_ifc_defconfig            |   1 +
 configs/ls1021atwr_sdcard_qspi_defconfig           |   1 +
 drivers/video/Kconfig                              |  15 +++
 drivers/video/Makefile                             |   2 +-
 drivers/video/fsl_dcu_fb.c                         | 121 ++++++++++++++++++---
 include/configs/colibri_vf.h                       |  13 +++
 include/configs/ls1021aqds.h                       |   4 +-
 include/configs/ls1021atwr.h                       |   4 +-
 include/fsl_dcu_fb.h                               |   1 +
 scripts/config_whitelist.txt                       |   1 -
 36 files changed, 313 insertions(+), 41 deletions(-)
 create mode 100644 board/toradex/colibri_vf/dcu.c
#3 lore raw

PATCH v3 1/6 Convert CONFIG_FSL_DCU_FB to Kconfig

In reply to Sanchayan Maity
Quoted 34 lines

-----Original Message-----
From: Sanchayan Maity [mailto:maitysanchayan at gmail.com]
Sent: Tuesday, April 11, 2017 1:42 PM
To: u-boot at lists.denx.de; sbabic at denx.de; agust at denx.de
Cc: albert.u.boot at aribaud.net; Feng Li <[email protected]>; alison.wang at freescale.com; Sumit Garg <[email protected]>; Stefan Agner <[email protected]>; york sun <[email protected]>; Z.Q. Hou <[email protected]>; Xiaoliang Yang <[email protected]>; Sanchayan Maity <[email protected]>
Subject: [PATCH v3 1/6] Convert CONFIG_FSL_DCU_FB to Kconfig

Rename CONFIG_FSL_DCU_FB to CONFIG_VIDEO_FSL_DCU_FB and convert it to Kconfig.

Signed-off-by Sanchayan Maity <[email protected]>
---
 arch/arm/cpu/armv7/ls102xa/soc.c                    | 2 +-
 board/freescale/ls1021aiot/Makefile                 | 2 +-
 board/freescale/ls1021aqds/Makefile                 | 2 +-
 board/freescale/ls1021atwr/Makefile                 | 2 +-
 configs/ls1021aqds_ddr4_nor_defconfig               | 1 +
 configs/ls1021aqds_ddr4_nor_lpuart_defconfig        | 1 +
 configs/ls1021aqds_nand_defconfig                   | 1 +
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig        | 1 +
 configs/ls1021aqds_nor_defconfig                    | 1 +
 configs/ls1021aqds_nor_lpuart_defconfig             | 1 +
 configs/ls1021aqds_qspi_defconfig                   | 1 +
 configs/ls1021aqds_sdcard_ifc_defconfig             | 1 +
 configs/ls1021aqds_sdcard_qspi_defconfig            | 1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig        | 1 +
 configs/ls1021atwr_nor_defconfig                    | 1 +
 configs/ls1021atwr_nor_lpuart_defconfig             | 1 +
 configs/ls1021atwr_qspi_defconfig                   | 1 +
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
Quoted 8 lines
 configs/ls1021atwr_sdcard_ifc_defconfig             | 1 +
 configs/ls1021atwr_sdcard_qspi_defconfig            | 1 +
 drivers/video/Kconfig                               | 7 +++++++
 drivers/video/Makefile                              | 2 +-
 include/configs/ls1021aqds.h                        | 4 +---
 include/configs/ls1021atwr.h                        | 4 +---
 scripts/config_whitelist.txt                        | 1 -
 25 files changed, 30 insertions(+), 12 deletions(-)
Reviewed-by Alison Wang <[email protected]>

Best Regards,
Alison Wang

#6 lore raw

PATCH v3 3/6 video: fsl_dcu_fb: Enable pixel clock after initialization

In reply to Sanchayan Maity
Quoted 22 lines

-----Original Message-----
From: Sanchayan Maity [mailto:maitysanchayan at gmail.com]
Sent: Tuesday, April 11, 2017 1:42 PM
To: u-boot at lists.denx.de; sbabic at denx.de; agust at denx.de
Cc: albert.u.boot at aribaud.net; Feng Li <[email protected]>; alison.wang at freescale.com; Sumit Garg <[email protected]>; Stefan Agner <[email protected]>; york sun <[email protected]>; Z.Q. Hou <[email protected]>; Xiaoliang Yang <[email protected]>; Sanchayan Maity <[email protected]>
Subject: [PATCH v3 3/6] video: fsl_dcu_fb: Enable pixel clock after initialization

From: Stefan Agner <[email protected]>

When enabling the DCU and pixel clock, the test mode is activated since this is the reset configuration. The test mode immediately shows a red screen on a LCD. A moment later, the DCU gets initialized properly.

This patch enables the pixel clock after initialization of the DCU control register. This avoids this initial flicker on LCD screens.

Quoted 9 lines

While at it change the polarity of pixel clock to display samples data on the rising edge.

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 drivers/video/fsl_dcu_fb.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)
Reviewed-by Alison Wang <[email protected]>

Best Regards,
Alison Wang

#9 lore raw

PATCH v3 5/6 video: fsl_dcu_fb: add additional modes for DCU

In reply to Sanchayan Maity
Quoted 13 lines

-----Original Message-----
From: Sanchayan Maity [mailto:maitysanchayan at gmail.com]
Sent: Tuesday, April 11, 2017 1:42 PM
To: u-boot at lists.denx.de; sbabic at denx.de; agust at denx.de
Cc: albert.u.boot at aribaud.net; Feng Li <[email protected]>; alison.wang at freescale.com; Sumit Garg <[email protected]>; Stefan Agner <[email protected]>; york sun <[email protected]>; Z.Q. Hou <[email protected]>; Xiaoliang Yang <[email protected]>; Sanchayan Maity <[email protected]>
Subject: [PATCH v3 5/6] video: fsl_dcu_fb: add additional modes for DCU

From: Stefan Agner <[email protected]>

Quoted 9 lines

Add common widescreen modes 800x480 and 1024x600.

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 drivers/video/fsl_dcu_fb.c | 61
++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 59 insertions(+), 2 deletions(-)
Reviewed-by Alison Wang <[email protected]>

Best Regards,
Alison Wang

#15 lore raw

v3 cover Introduce DCU support for Vybrid

In reply to Stefan Agner

Hi Stefan,

Quoted 5 lines · Stefan Agner

Stefano,

This patchset has been on the ML for a quite a while, any chance to get this still into v2017.05?

I was in last days not in office, but I am now sorting patches that can go into 2017.05. I will start to merge them today - and I will pick up this series.

Regards,
Stefano

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
#11 lore raw

PATCH v3 6/6 board: toradex: colibri_vf: Add DCU support for Colibri Vybrid

In reply to Sanchayan Maity

Hi Stefan,

Quoted 2 lines · Sanchayan Maity

From: Stefan Agner <[email protected]>

The series is assigned to Anatolji, that the reason I do not merge. Other patches are related to Video, for this one:

Quoted 375 lines

The Vybrid SoC family has the same display controller unit (DCU) like the LS1021A SoC. This patch adds platform data, pinmux defines and clock control to enable the driver for Toradex Colibri Vybrid module.

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 arch/arm/include/asm/arch-vf610/crm_regs.h    | 14 +++++
 arch/arm/include/asm/arch-vf610/imx-regs.h    |  2 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 +++++++++++
 arch/arm/include/asm/imx-common/iomux-v3.h    |  3 ++
 board/toradex/colibri_vf/Makefile             |  1 +
 board/toradex/colibri_vf/colibri_vf.c         | 76 +++++++++++++++++++++------
 board/toradex/colibri_vf/dcu.c                | 38 ++++++++++++++
 configs/colibri_vf_defconfig                  |  4 ++
 include/configs/colibri_vf.h                  | 13 +++++
 9 files changed, 166 insertions(+), 16 deletions(-)
 create mode 100644 board/toradex/colibri_vf/dcu.c
arch/arm/include/asm/arch-vf610/crm_regs.h +14 -0
index a46e396f1d..73b1dd2f14 100644
@@ -9,6 +9,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/types.h>
+
 /* Clock Controller Module (CCM) */
 struct ccm_reg {
 	u32 ccr;

@@ -150,6 +152,9 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
 
+#define CCM_CSCMR1_DCU1_CLK_SEL			(1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL			(1 << 28)
+
 #define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
 #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
 #define CCM_CSCMR1_QSPI0_CLK_SEL(v)		(((v) & 0x3) << 22)

@@ -174,6 +179,13 @@ struct anadig_reg {
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_DCU1_EN			(1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK		(0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v)			(((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN			(1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK		(0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v)			(((v) & 0x7) << 16)
+
 #define CCM_CSCDR3_NFC_PRE_DIV_OFFSET		13
 #define CCM_CSCDR3_NFC_PRE_DIV_MASK		(0x7 << 13)
 #define CCM_CSCDR3_NFC_PRE_DIV(v)		(((v) & 0x7) << 13)

@@ -193,6 +205,7 @@ struct anadig_reg {
 #define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)

@@ -203,6 +216,7 @@ struct anadig_reg {
 #define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
 #define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
arch/arm/include/asm/arch-vf610/imx-regs.h +2 -0
index cac68efde2..ca97462c35 100644
@@ -69,6 +69,7 @@
 #define USB_PHY0_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050800)
 #define USB_PHY1_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050C00)
 #define SCSC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00058000)
 #define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
 #define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)

@@ -98,6 +99,7 @@
 #define USBC1_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00034000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00058000)
 #define NFC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00060000)
 
 #define QSPI0_AMBA_BASE		0x20000000
arch/arm/include/asm/arch-vf610/iomux-vf610.h +31 -0
index a140be05f1..5af071a4db 100644
@@ -40,6 +40,8 @@
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
 #define VF610_DSPI_SIN_PAD_CTRL	(PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DCU_PAD_CTRL     (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE)
 
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),

@@ -166,6 +168,35 @@ enum {
 
 	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
+	VF610_PAD_PTE0__DCU0_HSYNC		= IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE1__DCU0_VSYNC		= IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE2__DCU0_PCLK		= IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE4__DCU0_DE			= IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE5__DCU0_R0			= IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE6__DCU0_R1			= IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE7__DCU0_R2			= IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE8__DCU0_R3			= IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE9__DCU0_R4			= IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE10__DCU0_R5		= IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE11__DCU0_R6		= IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE12__DCU0_R7		= IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE13__DCU0_G0		= IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE14__DCU0_G1		= IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE15__DCU0_G2		= IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE16__DCU0_G3		= IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE17__DCU0_G4		= IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE18__DCU0_G5		= IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE19__DCU0_G6		= IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE20__DCU0_G7		= IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE21__DCU0_B0		= IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE22__DCU0_B1		= IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE23__DCU0_B2		= IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE24__DCU0_B3		= IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE25__DCU0_B4		= IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE26__DCU0_B5		= IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE27__DCU0_B6		= IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE28__DCU0_B7		= IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+
 	VF610_PAD_DDR_RESETB			= IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
arch/arm/include/asm/imx-common/iomux-v3.h +3 -0
index 7587cbbf95..ba0ed43811 100644
@@ -165,7 +165,10 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_ODE		(1 << 10)
 
 #define PAD_CTL_DSE_150ohm	(1 << 6)
+#define PAD_CTL_DSE_75ohm	(2 << 6)
 #define PAD_CTL_DSE_50ohm	(3 << 6)
+#define PAD_CTL_DSE_37ohm	(4 << 6)
+#define PAD_CTL_DSE_30ohm	(5 << 6)
 #define PAD_CTL_DSE_25ohm	(6 << 6)
 #define PAD_CTL_DSE_20ohm	(7 << 6)
board/toradex/colibri_vf/Makefile +1 -0
index c7e5134ba1..4d6287f14a 100644
@@ -5,3 +5,4 @@
 #
 
 obj-y	:= colibri_vf.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
board/toradex/colibri_vf/colibri_vf.c +60 -16
index 7b74eb7e9d..46dd15bac8 100644
@@ -17,6 +17,7 @@
 #include <mmc.h>
 #include <fdt_support.h>
 #include <fsl_esdhc.h>
+#include <fsl_dcu_fb.h>
 #include <jffs2/load_kernel.h>
 #include <miiphy.h>
 #include <mtd_node.h>

@@ -295,6 +296,49 @@ static void setup_iomux_gpio(void)
 }
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+static void setup_iomux_fsl_dcu(void)
+{
+	static const iomux_v3_cfg_t dcu0_pads[] = {
+		VF610_PAD_PTE0__DCU0_HSYNC,
+		VF610_PAD_PTE1__DCU0_VSYNC,
+		VF610_PAD_PTE2__DCU0_PCLK,
+		VF610_PAD_PTE4__DCU0_DE,
+		VF610_PAD_PTE5__DCU0_R0,
+		VF610_PAD_PTE6__DCU0_R1,
+		VF610_PAD_PTE7__DCU0_R2,
+		VF610_PAD_PTE8__DCU0_R3,
+		VF610_PAD_PTE9__DCU0_R4,
+		VF610_PAD_PTE10__DCU0_R5,
+		VF610_PAD_PTE11__DCU0_R6,
+		VF610_PAD_PTE12__DCU0_R7,
+		VF610_PAD_PTE13__DCU0_G0,
+		VF610_PAD_PTE14__DCU0_G1,
+		VF610_PAD_PTE15__DCU0_G2,
+		VF610_PAD_PTE16__DCU0_G3,
+		VF610_PAD_PTE17__DCU0_G4,
+		VF610_PAD_PTE18__DCU0_G5,
+		VF610_PAD_PTE19__DCU0_G6,
+		VF610_PAD_PTE20__DCU0_G7,
+		VF610_PAD_PTE21__DCU0_B0,
+		VF610_PAD_PTE22__DCU0_B1,
+		VF610_PAD_PTE23__DCU0_B2,
+		VF610_PAD_PTE24__DCU0_B3,
+		VF610_PAD_PTE25__DCU0_B4,
+		VF610_PAD_PTE26__DCU0_B5,
+		VF610_PAD_PTE27__DCU0_B6,
+		VF610_PAD_PTE28__DCU0_B7,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
+}
+
+static void setup_tcon(void)
+{
+	setbits_le32(TCON0_BASE_ADDR, (1 << 29));
+}
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{ESDHC1_BASE_ADDR},

@@ -431,6 +475,11 @@ static void clock_init(void)
 			CCM_CSCDR3_NFC_PRE_DIV(3));
 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 			CCM_CSCMR2_RMII_CLK_SEL(2));
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+		setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
+		setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
+#endif
 }
 
 static void mscm_init(void)

@@ -470,6 +519,11 @@ int board_early_init_f(void)
 	setup_iomux_dspi();
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+	setup_tcon();
+	setup_iomux_fsl_dcu();
+#endif
+
 	return 0;
 }
 

@@ -478,22 +532,6 @@ int board_late_init(void)
 {
 	struct src *src = (struct src *)SRC_BASE_ADDR;
 
-	/* Default memory arguments */
-	if (!getenv("memargs")) {
-		switch (gd->ram_size) {
-		case 0x08000000:
-			/* 128 MB */
-			setenv("memargs", "mem=128M");
-			break;
-		case 0x10000000:
-			/* 256 MB */
-			setenv("memargs", "mem=256M");
-			break;
-		default:
-			printf("Failed detecting RAM size.\n");
-		}
-	}
-
 	if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
 			== SRC_SBMR2_BMOD_SERIAL) {
 		printf("Serial Downloader recovery mode, disable autoboot\n");

@@ -541,6 +579,7 @@ int checkboard(void)
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	int ret = 0;
 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 	static struct node_info nodes[] = {
 		{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */

@@ -550,6 +589,11 @@ int ft_board_setup(void *blob, bd_t *bd)
 	puts("   Updating MTD partitions...\n");
 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 #endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+	ret = fsl_dcu_fixedfb_setup(blob);
+	if (ret)
+		return ret;
+#endif
 
 	return ft_common_board_setup(blob, bd);
 }
board/toradex/colibri_vf/dcu.c new file +38 -0
new file mode 100644
index 0000000000..3fa6a763d8
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * FSL DCU platform driver
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	unsigned long long div;
+
+	clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
+	clrsetbits_le32(&ccm->cscdr3,
+			CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
+			CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
+	div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
+	do_div(div, pixclock);
+
+	return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	fsl_dcu_init(xres, yres, 32);
+
+	return 0;
+}
configs/colibri_vf_defconfig +4 -0
index 0474abc3c5..1f0f929ce5 100644
@@ -52,3 +52,7 @@ CONFIG_G_DNL_MANUFACTURER="Toradex"
 CONFIG_G_DNL_VENDOR_NUM=0x1b67
 CONFIG_G_DNL_PRODUCT_NUM=0x4000
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_FSL_DCU_FB=y
+CONFIG_SYS_CONSOLE_FG_COL=0x00
+CONFIG_SYS_CONSOLE_BG_COL=0x00
include/configs/colibri_vf.h +11 -0
index 73b43bd7ad..5dc5ed0b71 100644
@@ -25,6 +25,17 @@
 #define CONFIG_MXC_OCOTP
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_FSL_DCU_LE
+
+#define CONFIG_SYS_DCU_ADDR		DCU0_BASE_ADDR
+#define DCU_LAYER_MAX_NUM		64
+#endif
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)

include/configs/colibri_vf.h line 148

Quoted 8 lines
include/configs/colibri_vf.h +2 -0
@@ -130,6 +141,8 @@
 	"setupdate=run setsdupdate || run setusbupdate\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+	"video-mode=dcufb:640x480-16 at 60,monitor=lcd\0" \
+	"splashpos=m,m\0" \
 	SD_BOOTCMD \
 	NFS_BOOTCMD \
 	UBI_BOOTCMD
Reviewed-by Stefano Babic <[email protected]>

Best regards,
Stefano

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
#12 lore raw

PATCH v3 6/6 board: toradex: colibri_vf: Add DCU support for Colibri Vybrid

Quoted 7 lines · Stefano Babic

Hi Stefan,

Quoted 2 lines · Sanchayan Maity

From: Stefan Agner <[email protected]>

The series is assigned to Anatolji, that the reason I do not merge.

Oh I see, in this case, Anatolij, any chance to merge in this window?

Quoted 1 line

Other patches are related to Video, for this one:

Thanks Stefano for reviewing!

--
Stefan

Quoted 389 lines
Quoted 376 lines

The Vybrid SoC family has the same display controller unit (DCU) like the LS1021A SoC. This patch adds platform data, pinmux defines and clock control to enable the driver for Toradex Colibri Vybrid module.

Signed-off-by Stefan Agner <[email protected]>
Signed-off-by Sanchayan Maity <[email protected]>
---
 arch/arm/include/asm/arch-vf610/crm_regs.h    | 14 +++++
 arch/arm/include/asm/arch-vf610/imx-regs.h    |  2 +
 arch/arm/include/asm/arch-vf610/iomux-vf610.h | 31 +++++++++++
 arch/arm/include/asm/imx-common/iomux-v3.h    |  3 ++
 board/toradex/colibri_vf/Makefile             |  1 +
 board/toradex/colibri_vf/colibri_vf.c         | 76 +++++++++++++++++++++------
 board/toradex/colibri_vf/dcu.c                | 38 ++++++++++++++
 configs/colibri_vf_defconfig                  |  4 ++
 include/configs/colibri_vf.h                  | 13 +++++
 9 files changed, 166 insertions(+), 16 deletions(-)
 create mode 100644 board/toradex/colibri_vf/dcu.c
arch/arm/include/asm/arch-vf610/crm_regs.h +14 -0
index a46e396f1d..73b1dd2f14 100644
@@ -9,6 +9,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/types.h>
+
 /* Clock Controller Module (CCM) */
 struct ccm_reg {
 	u32 ccr;

@@ -150,6 +152,9 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
 
+#define CCM_CSCMR1_DCU1_CLK_SEL			(1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL			(1 << 28)
+
 #define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
 #define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
 #define CCM_CSCMR1_QSPI0_CLK_SEL(v)		(((v) & 0x3) << 22)

@@ -174,6 +179,13 @@ struct anadig_reg {
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_DCU1_EN			(1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK		(0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v)			(((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN			(1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK		(0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v)			(((v) & 0x7) << 16)
+
 #define CCM_CSCDR3_NFC_PRE_DIV_OFFSET		13
 #define CCM_CSCDR3_NFC_PRE_DIV_MASK		(0x7 << 13)
 #define CCM_CSCDR3_NFC_PRE_DIV(v)		(((v) & 0x7) << 13)

@@ -193,6 +205,7 @@ struct anadig_reg {
 #define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)

@@ -203,6 +216,7 @@ struct anadig_reg {
 #define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
 #define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
arch/arm/include/asm/arch-vf610/imx-regs.h +2 -0
index cac68efde2..ca97462c35 100644
@@ -69,6 +69,7 @@
 #define USB_PHY0_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050800)
 #define USB_PHY1_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050C00)
 #define SCSC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00058000)
 #define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
 #define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)

@@ -98,6 +99,7 @@
 #define USBC1_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00034000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00058000)
 #define NFC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00060000)
 
 #define QSPI0_AMBA_BASE		0x20000000
arch/arm/include/asm/arch-vf610/iomux-vf610.h +31 -0
index a140be05f1..5af071a4db 100644
@@ -40,6 +40,8 @@
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
 #define VF610_DSPI_SIN_PAD_CTRL	(PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
 				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DCU_PAD_CTRL     (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE)
 
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),

@@ -166,6 +168,35 @@ enum {
 
 	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
+	VF610_PAD_PTE0__DCU0_HSYNC		= IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE1__DCU0_VSYNC		= IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE2__DCU0_PCLK		= IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE4__DCU0_DE			= IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE5__DCU0_R0			= IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE6__DCU0_R1			= IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE7__DCU0_R2			= IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE8__DCU0_R3			= IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE9__DCU0_R4			= IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE10__DCU0_R5		= IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE11__DCU0_R6		= IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE12__DCU0_R7		= IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE13__DCU0_G0		= IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE14__DCU0_G1		= IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE15__DCU0_G2		= IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE16__DCU0_G3		= IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE17__DCU0_G4		= IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE18__DCU0_G5		= IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE19__DCU0_G6		= IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE20__DCU0_G7		= IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE21__DCU0_B0		= IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE22__DCU0_B1		= IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE23__DCU0_B2		= IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE24__DCU0_B3		= IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE25__DCU0_B4		= IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE26__DCU0_B5		= IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE27__DCU0_B6		= IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE28__DCU0_B7		= IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+
 	VF610_PAD_DDR_RESETB			= IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
arch/arm/include/asm/imx-common/iomux-v3.h +3 -0
index 7587cbbf95..ba0ed43811 100644
@@ -165,7 +165,10 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_ODE		(1 << 10)
 
 #define PAD_CTL_DSE_150ohm	(1 << 6)
+#define PAD_CTL_DSE_75ohm	(2 << 6)
 #define PAD_CTL_DSE_50ohm	(3 << 6)
+#define PAD_CTL_DSE_37ohm	(4 << 6)
+#define PAD_CTL_DSE_30ohm	(5 << 6)
 #define PAD_CTL_DSE_25ohm	(6 << 6)
 #define PAD_CTL_DSE_20ohm	(7 << 6)
board/toradex/colibri_vf/Makefile +1 -0
index c7e5134ba1..4d6287f14a 100644
@@ -5,3 +5,4 @@
 #
 
 obj-y	:= colibri_vf.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
board/toradex/colibri_vf/colibri_vf.c +60 -16
index 7b74eb7e9d..46dd15bac8 100644
@@ -17,6 +17,7 @@
 #include <mmc.h>
 #include <fdt_support.h>
 #include <fsl_esdhc.h>
+#include <fsl_dcu_fb.h>
 #include <jffs2/load_kernel.h>
 #include <miiphy.h>
 #include <mtd_node.h>

@@ -295,6 +296,49 @@ static void setup_iomux_gpio(void)
 }
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+static void setup_iomux_fsl_dcu(void)
+{
+	static const iomux_v3_cfg_t dcu0_pads[] = {
+		VF610_PAD_PTE0__DCU0_HSYNC,
+		VF610_PAD_PTE1__DCU0_VSYNC,
+		VF610_PAD_PTE2__DCU0_PCLK,
+		VF610_PAD_PTE4__DCU0_DE,
+		VF610_PAD_PTE5__DCU0_R0,
+		VF610_PAD_PTE6__DCU0_R1,
+		VF610_PAD_PTE7__DCU0_R2,
+		VF610_PAD_PTE8__DCU0_R3,
+		VF610_PAD_PTE9__DCU0_R4,
+		VF610_PAD_PTE10__DCU0_R5,
+		VF610_PAD_PTE11__DCU0_R6,
+		VF610_PAD_PTE12__DCU0_R7,
+		VF610_PAD_PTE13__DCU0_G0,
+		VF610_PAD_PTE14__DCU0_G1,
+		VF610_PAD_PTE15__DCU0_G2,
+		VF610_PAD_PTE16__DCU0_G3,
+		VF610_PAD_PTE17__DCU0_G4,
+		VF610_PAD_PTE18__DCU0_G5,
+		VF610_PAD_PTE19__DCU0_G6,
+		VF610_PAD_PTE20__DCU0_G7,
+		VF610_PAD_PTE21__DCU0_B0,
+		VF610_PAD_PTE22__DCU0_B1,
+		VF610_PAD_PTE23__DCU0_B2,
+		VF610_PAD_PTE24__DCU0_B3,
+		VF610_PAD_PTE25__DCU0_B4,
+		VF610_PAD_PTE26__DCU0_B5,
+		VF610_PAD_PTE27__DCU0_B6,
+		VF610_PAD_PTE28__DCU0_B7,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
+}
+
+static void setup_tcon(void)
+{
+	setbits_le32(TCON0_BASE_ADDR, (1 << 29));
+}
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{ESDHC1_BASE_ADDR},

@@ -431,6 +475,11 @@ static void clock_init(void)
 			CCM_CSCDR3_NFC_PRE_DIV(3));
 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 			CCM_CSCMR2_RMII_CLK_SEL(2));
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+		setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
+		setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
+#endif
 }
 
 static void mscm_init(void)

@@ -470,6 +519,11 @@ int board_early_init_f(void)
 	setup_iomux_dspi();
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+	setup_tcon();
+	setup_iomux_fsl_dcu();
+#endif
+
 	return 0;
 }
 

@@ -478,22 +532,6 @@ int board_late_init(void)
 {
 	struct src *src = (struct src *)SRC_BASE_ADDR;
 
-	/* Default memory arguments */
-	if (!getenv("memargs")) {
-		switch (gd->ram_size) {
-		case 0x08000000:
-			/* 128 MB */
-			setenv("memargs", "mem=128M");
-			break;
-		case 0x10000000:
-			/* 256 MB */
-			setenv("memargs", "mem=256M");
-			break;
-		default:
-			printf("Failed detecting RAM size.\n");
-		}
-	}
-
 	if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
 			== SRC_SBMR2_BMOD_SERIAL) {
 		printf("Serial Downloader recovery mode, disable autoboot\n");

@@ -541,6 +579,7 @@ int checkboard(void)
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	int ret = 0;
 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 	static struct node_info nodes[] = {
 		{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */

@@ -550,6 +589,11 @@ int ft_board_setup(void *blob, bd_t *bd)
 	puts("   Updating MTD partitions...\n");
 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 #endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+	ret = fsl_dcu_fixedfb_setup(blob);
+	if (ret)
+		return ret;
+#endif
 
 	return ft_common_board_setup(blob, bd);
 }
board/toradex/colibri_vf/dcu.c new file +38 -0
new file mode 100644
index 0000000000..3fa6a763d8
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * FSL DCU platform driver
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	unsigned long long div;
+
+	clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
+	clrsetbits_le32(&ccm->cscdr3,
+			CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
+			CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
+	div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
+	do_div(div, pixclock);
+
+	return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	fsl_dcu_init(xres, yres, 32);
+
+	return 0;
+}
configs/colibri_vf_defconfig +4 -0
index 0474abc3c5..1f0f929ce5 100644
@@ -52,3 +52,7 @@ CONFIG_G_DNL_MANUFACTURER="Toradex"
 CONFIG_G_DNL_VENDOR_NUM=0x1b67
 CONFIG_G_DNL_PRODUCT_NUM=0x4000
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_FSL_DCU_FB=y
+CONFIG_SYS_CONSOLE_FG_COL=0x00
+CONFIG_SYS_CONSOLE_BG_COL=0x00
include/configs/colibri_vf.h +11 -0
index 73b43bd7ad..5dc5ed0b71 100644
@@ -25,6 +25,17 @@
 #define CONFIG_MXC_OCOTP
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_FSL_DCU_LE
+
+#define CONFIG_SYS_DCU_ADDR		DCU0_BASE_ADDR
+#define DCU_LAYER_MAX_NUM		64
+#endif
+
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)

include/configs/colibri_vf.h line 148

Quoted 8 lines
include/configs/colibri_vf.h +2 -0
@@ -130,6 +141,8 @@
 	"setupdate=run setsdupdate || run setusbupdate\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+	"video-mode=dcufb:640x480-16 at 60,monitor=lcd\0" \
+	"splashpos=m,m\0" \
 	SD_BOOTCMD \
 	NFS_BOOTCMD \
 	UBI_BOOTCMD
Reviewed-by Stefano Babic <[email protected]>

Best regards,
Stefano

#13 lore raw

PATCH v3 6/6 board: toradex: colibri_vf: Add DCU support for Colibri Vybrid

Hi Stefan,

Quoted 10 lines · On Wed, 12 Apr 2017 10:53:01 -0700 Stefan Agner stefan at agner.ch wrote:
Quoted 7 lines · Stefano Babic

Hi Stefan,

Quoted 2 lines · Sanchayan Maity

From: Stefan Agner <[email protected]>

The series is assigned to Anatolji, that the reason I do not merge.

Oh I see, in this case, Anatolij, any chance to merge in this window?

I'll submit a pull request after build-testing. Thanks!

--
Anatolij

#16 lore raw

v3 cover Introduce DCU support for Vybrid

In reply to Sanchayan Maity

On Tue, 11 Apr 2017 11:12:08 +0530 Sanchayan Maity maitysanchayan at gmail.com wrote:
...

Quoted 9 lines

Sanchayan Maity (1):
Convert CONFIG_FSL_DCU_FB to Kconfig

Stefan Agner (5):
video: fsl_dcu_fb: fix framebuffer to the end of memory
video: fsl_dcu_fb: Enable pixel clock after initialization
video: fsl_dcu_fb: Fix DCU_MODE_BLEND_ITER setting
video: fsl_dcu_fb: add additional modes for DCU
board: toradex: colibri_vf: Add DCU support for Colibri Vybrid

applied to u-boot-video/master. Thanks!

--
Anatolij