add MFD support for MediaTek audio subsystem
Subsystems (3)
v2 cover add MFD support for MediaTek audio subsystem
Hi,
This is the 2nd version of the patch sets which modify clock driver to adapt audio subsystem. I still keeping 'simple-mfd' in the binding for discussion. Rob, let me know if there is any problem with this.
changes since v2:
- Drop useless changes in clk-mt7622-aud.c.
- Revise binding text:
- Add more information about audio subsystem.
- Separate clock node and AFE node.
- Update license header.
changes since v1:
- To avoid writing an MFD driver, we add "simple-mfd" in the audsys binding.
- Move three top clocks to audio driver [1] as we remove mfd/mtk-audsys.c in v1.
Ryder Lee (5):
clk: mediatek: update missing clock data for MT7622 audsys
clk: mediatek: modify MT7622 audsys to adapt MFD device
clk: mediatek: add audsys support for MT2701
dt-bindings: clock: mediatek: update audsys documentation to adapt MFD
device
arm: dts: mediatek: add audio-subsystem node for both MT2701 and
MT7623
.../bindings/arm/mediatek/mediatek,audsys.txt | 37 +++- arch/arm/boot/dts/mt2701.dtsi | 192 ++++++++++---------- arch/arm/boot/dts/mt7623.dtsi | 193 ++++++++++----------- drivers/clk/mediatek/Kconfig | 6 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt2701-aud.c | 175 +++++++++++++++++++ drivers/clk/mediatek/clk-mt7622-aud.c | 4 +- include/dt-bindings/clock/mt7622-clk.h | 3 +- 8 files changed, 406 insertions(+), 205 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt2701-aud.c
Signature · 1 line
1.9.1
PATCH v2 1/5 clk: mediatek: update missing clock data for MT7622 audsys
Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys.
--- drivers/clk/mediatek/clk-mt7622-aud.c | 1 + include/dt-bindings/clock/mt7622-clk.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-)
drivers/clk/mediatek/clk-mt7622-aud.c +1 -0
@@ -106,6 +106,7 @@GATE_AUDIO1 (CLK_AUDIO_INTDIR ,"audio_intdir" ,"intdir_sel" ,20 ),GATE_AUDIO1 (CLK_AUDIO_A1SYS ,"audio_a1sys" ,"a1sys_hp_sel" ,21 ),GATE_AUDIO1 (CLK_AUDIO_A2SYS ,"audio_a2sys" ,"a2sys_hp_sel" ,22 ), +GATE_AUDIO1 (CLK_AUDIO_AFE_CONN ,"audio_afe_conn" ,"a1sys_hp_sel" ,23 ),/* AUDIO2 */ GATE_AUDIO2 (CLK_AUDIO_UL1 ,"audio_ul1" ,"a1sys_hp_sel" ,0 ), GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
include/dt-bindings/clock/mt7622-clk.h +2 -1
@@ -235,7 +235,8 @@#define CLK_AUDIO_MEM_ASRC3 43#define CLK_AUDIO_MEM_ASRC4 44#define CLK_AUDIO_MEM_ASRC5 45 -#define CLK_AUDIO_NR_CLK 46 +#define CLK_AUDIO_AFE_CONN 46 +#define CLK_AUDIO_NR_CLK 47/* SSUSBSYS */
Signature · 1 line
1.9.1
PATCH v2 2/5 clk: mediatek: modify MT7622 audsys to adapt MFD device
In reply to Ryder LeeAs the new MFD parent is in place, switch probing method to adapt it.
--- drivers/clk/mediatek/clk-mt7622-aud.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/mediatek/clk-mt7622-aud.c +2 -1
@@ -142,11 +142,12 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) {struct clk_onecell_data *clk_data;struct device_node *node = pdev->dev.of_node; +struct device_node *pnode = pdev->dev.parent->of_node;int r; clk_data =mtk_alloc_clk_data (CLK_AUDIO_NR_CLK ); -mtk_clk_register_gates (node, audio_clks,ARRAY_SIZE (audio_clks), +mtk_clk_register_gates (pnode, audio_clks,ARRAY_SIZE (audio_clks), clk_data); r =of_clk_add_provider (node, of_clk_src_onecell_get, clk_data);
Signature · 1 line
1.9.1
PATCH v2 3/5 clk: mediatek: add audsys support for MT2701
In reply to Ryder LeeAdd clock driver support for MT2701 audsys.
--- drivers/clk/mediatek/Kconfig | 6 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt2701-aud.c | 175 ++++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt2701-aud.c
drivers/clk/mediatek/Kconfig +6 -0
@@ -50,6 +50,12 @@ config COMMON_CLK_MT2701_BDPSYS ---help--- This driver supports Mediatek MT2701 bdpsys clocks. +config COMMON_CLK_MT2701_AUDSYS + bool "Clock driver for Mediatek MT2701 audsys" + depends on COMMON_CLK_MT2701 + ---help--- + This driver supports Mediatek MT2701 audsys clocks. + config COMMON_CLK_MT2712 bool "Clock driver for Mediatek MT2712" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
drivers/clk/mediatek/Makefile +1 -0
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o +obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
drivers/clk/mediatek/clk-mt2701-aud.c new file +175 -0
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Signature · 1 line
1.9.1
PATCH v2 4/5 dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
In reply to Ryder LeeAs the MediaTek audio hardware block that expose functionalities that are handled by separate subsystems in the kernel, and there are registers that are shared between related drivers.
Switch the current device to an MFD device, add more descriptions about the subsystem and modify example accordingly.
--- .../bindings/arm/mediatek/mediatek,audsys.txt | 37 ++++++++++++++++++---- 1 file changed, 30 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +30 -7
@@ -1,22 +1,45 @@ -MediaTek AUDSYS controller +MediaTek Audio Subsystem ============================ +The audio subsystem is one of the multi-function blocks of MediaTek SoCs. +It contains a system controller, which provides a number registers giving +access to two features: AUDSYS clocks and Audio Front End (AFE) components. +For the top level node: +- compatible: must be: "syscon", "simple-mfd"; +- reg: register area of the Audio Subsystem + +Required sub-nodes: + +AUDSYS clocks: +------- The MediaTek AUDSYS controller provides various clocks to the system. Required Properties: - compatible: Should be one of: - - "mediatek,mt7622-audsys", "syscon" + - "mediatek,mt2701-audsys"; + - "mediatek,mt7622-audsys"; - #clock-cells: Must be 1 The AUDSYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. +AFE components: +------- +For common binding part and usage, refer to +../sonud/mt2701-afe-pcm.txt. + Example: -audsys: audsys at 11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x1000>; - #clock-cells = <1>; -}; + audio-subsystem at 11220000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x11220000 0 0x2000>; + + audsys: clock { + compatible = "mediatek,mt2701-audsys"; + #clock-cells = <1>; + }; + + ... + };
Signature · 1 line
1.9.1
PATCH v2 5/5 arm: dts: mediatek: add audio-subsystem node for both MT2701 and MT7623
In reply to Ryder LeeAdd audio-subsystem node and its clock support for both MT2701/MT7623. Then modify afe node to adapt it.
--- arch/arm/boot/dts/mt2701.dtsi | 192 ++++++++++++++++++++--------------------- arch/arm/boot/dts/mt7623.dtsi | 193 +++++++++++++++++++++--------------------- 2 files changed, 189 insertions(+), 196 deletions(-)
arch/arm/boot/dts/mt2701.dtsi +94 -98
@@ -426,104 +426,100 @@ status = "disabled"; }; - afe: audio-controller at 11220000 { - compatible = "mediatek,mt2701-audio"; - reg = <0 0x11220000 0 0x2000>, - <0 0x112a0000 0 0x20000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "afe", "asys"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_MUX1_DIV>, - <&topckgen CLK_TOP_AUD_MUX2_DIV>, - <&topckgen CLK_TOP_AUD_48K_TIMING>, - <&topckgen CLK_TOP_AUD_44K_TIMING>, - <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, - <&topckgen CLK_TOP_APLL_SEL>, - <&topckgen CLK_TOP_AUD1PLL_98M>, - <&topckgen CLK_TOP_AUD2PLL_90M>, - <&topckgen CLK_TOP_HADDS2PLL_98M>, - <&topckgen CLK_TOP_HADDS2PLL_294M>, - <&topckgen CLK_TOP_AUDPLL>, - <&topckgen CLK_TOP_AUDPLL_D4>, - <&topckgen CLK_TOP_AUDPLL_D8>, - <&topckgen CLK_TOP_AUDPLL_D16>, - <&topckgen CLK_TOP_AUDPLL_D24>, - <&topckgen CLK_TOP_AUDINTBUS_SEL>, - <&clk26m>, - <&topckgen CLK_TOP_SYSPLL1_D4>, - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, - <&topckgen CLK_TOP_AUD_I2S1_MCLK>, - <&topckgen CLK_TOP_AUD_I2S2_MCLK>, - <&topckgen CLK_TOP_AUD_I2S3_MCLK>, - <&topckgen CLK_TOP_AUD_I2S4_MCLK>, - <&topckgen CLK_TOP_AUD_I2S5_MCLK>, - <&topckgen CLK_TOP_AUD_I2S6_MCLK>, - <&topckgen CLK_TOP_ASM_M_SEL>, - <&topckgen CLK_TOP_ASM_H_SEL>, - <&topckgen CLK_TOP_UNIVPLL2_D4>, - <&topckgen CLK_TOP_UNIVPLL2_D2>, - <&topckgen CLK_TOP_SYSPLL_D5>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_mux1_div", - "top_audio_mux2_div", - "top_audio_48k_timing", - "top_audio_44k_timing", - "top_audpll_mux_sel", - "top_apll_sel", - "top_aud1_pll_98M", - "top_aud2_pll_90M", - "top_hadds2_pll_98M", - "top_hadds2_pll_294M", - "top_audpll", - "top_audpll_d4", - "top_audpll_d8", - "top_audpll_d16", - "top_audpll_d24", - "top_audintbus_sel", - "clk_26m", - "top_syspll1_d4", - "top_aud_k1_src_sel", - "top_aud_k2_src_sel", - "top_aud_k3_src_sel", - "top_aud_k4_src_sel", - "top_aud_k5_src_sel", - "top_aud_k6_src_sel", - "top_aud_k1_src_div", - "top_aud_k2_src_div", - "top_aud_k3_src_div", - "top_aud_k4_src_div", - "top_aud_k5_src_div", - "top_aud_k6_src_div", - "top_aud_i2s1_mclk", - "top_aud_i2s2_mclk", - "top_aud_i2s3_mclk", - "top_aud_i2s4_mclk", - "top_aud_i2s5_mclk", - "top_aud_i2s6_mclk", - "top_asm_m_sel", - "top_asm_h_sel", - "top_univpll2_d4", - "top_univpll2_d2", - "top_syspll_d5"; + audio-subsystem at 11220000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x11220000 0 0x2000>; + + audsys: clock { + compatible = "mediatek,mt2701-audsys"; + #clock-cells = <1>; + }; + + afe: audio { + compatible = "mediatek,mt2701-audio"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&audsys CLK_AUD_I2SO1>, + <&audsys CLK_AUD_I2SO2>, + <&audsys CLK_AUD_I2SO3>, + <&audsys CLK_AUD_I2SO4>, + <&audsys CLK_AUD_I2SIN1>, + <&audsys CLK_AUD_I2SIN2>, + <&audsys CLK_AUD_I2SIN3>, + <&audsys CLK_AUD_I2SIN4>, + <&audsys CLK_AUD_ASRCO1>, + <&audsys CLK_AUD_ASRCO2>, + <&audsys CLK_AUD_ASRCO3>, + <&audsys CLK_AUD_ASRCO4>, + <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_AFE_CONN>, + <&audsys CLK_AUD_A1SYS>, + <&audsys CLK_AUD_A2SYS>, + <&audsys CLK_AUD_AFE_MRGIF>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_a1sys_hp", + "top_audio_a2sys_hp", + "i2s0_src_sel", + "i2s1_src_sel", + "i2s2_src_sel", + "i2s3_src_sel", + "i2s0_src_div", + "i2s1_src_div", + "i2s2_src_div", + "i2s3_src_div", + "i2s0_mclk_en", + "i2s1_mclk_en", + "i2s2_mclk_en", + "i2s3_mclk_en", + "i2so0_hop_ck", + "i2so1_hop_ck", + "i2so2_hop_ck", + "i2so3_hop_ck", + "i2si0_hop_ck", + "i2si1_hop_ck", + "i2si2_hop_ck", + "i2si3_hop_ck", + "asrc0_out_ck", + "asrc1_out_ck", + "asrc2_out_ck", + "asrc3_out_ck", + "audio_afe_pd", + "audio_afe_conn_pd", + "audio_a1sys_pd", + "audio_a2sys_pd", + "audio_mrgif_pd"; + + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>; + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>; + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; + }; }; mmsys: syscon at 14000000 {
arch/arm/boot/dts/mt7623.dtsi +95 -98
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Signature · 1 line
1.9.1
Matthias Brugger
maintainerRe: [PATCH v2 2/5] clk: mediatek: modify MT7622 audsys to adapt MFD device
In reply to Ryder LeeQuoted 12 lines · Ryder Lee
As the new MFD parent is in place, switch probing method to adapt it.
Signed-off-by Ryder Lee <[email protected]>--- drivers/clk/mediatek/clk-mt7622-aud.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/clk/mediatek/clk-mt7622-aud.c +0
-0
drivers/clk/mediatek/clk-mt7622-aud.c static int clk_mt7622_audiosys_init(struct platform_device *pdev) · line 150
Quoted 10 lines
drivers/clk/mediatek/clk-mt7622-aud.c +2
-1@@ -142,11 +142,12 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) {struct clk_onecell_data *clk_data;struct device_node *node = pdev->dev.of_node; +struct device_node *pnode = pdev->dev.parent->of_node;int r; clk_data =mtk_alloc_clk_data (CLK_AUDIO_NR_CLK ); - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), + mtk_clk_register_gates(pnode, audio_clks, ARRAY_SIZE(audio_clks),
We will need a fallback here for older device tree bindings.
Regards,
Matthias
Quoted 4 lines
drivers/clk/mediatek/clk-mt7622-aud.c +0
-0clk_data); r =of_clk_add_provider (node, of_clk_src_onecell_get, clk_data);
Re: [PATCH v2 2/5] clk: mediatek: modify MT7622 audsys to adapt MFD device
Quoted 22 lines · Matthias Brugger
Quoted 20 lines · Ryder Lee
As the new MFD parent is in place, switch probing method to adapt it.
Signed-off-by Ryder Lee <[email protected]>--- drivers/clk/mediatek/clk-mt7622-aud.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/clk/mediatek/clk-mt7622-aud.c +1
-0@@ -142,11 +142,12 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) {struct clk_onecell_data *clk_data;struct device_node *node = pdev->dev.of_node; +struct device_node *pnode = pdev->dev.parent->of_node;int r; clk_data =mtk_alloc_clk_data (CLK_AUDIO_NR_CLK );
Quoted 7 lines
drivers/clk/mediatek/clk-mt7622-aud.c static int clk_mt7622_audiosys_init(struct platform_device *pdev) · line 150
Quoted 2 lines
drivers/clk/mediatek/clk-mt7622-aud.c +1
-1- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), + mtk_clk_register_gates(pnode, audio_clks, ARRAY_SIZE(audio_clks),We will need a fallback here for older device tree bindings.
Regards,
Matthias
Up to now, I didn't see both driver and bindings are used anywhere. Should I still care about that?
Thanks.
Re: [PATCH v2 1/5] clk: mediatek: update missing clock data for MT7622 audsys
In reply to Ryder LeeQuoted 7 lines · Ryder Lee
Add missing clock data '
CLK_AUDIO_AFE_CONN' for MT7622 audsys.Signed-off-by Ryder Lee <[email protected]>--- drivers/clk/mediatek/clk-mt7622-aud.c | 1 + include/dt-bindings/clock/mt7622-clk.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-)
Rob Herring
maintainerRe: [PATCH v2 4/5] dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
In reply to Ryder LeeQuoted 17 lines · Ryder Lee
As the MediaTek audio hardware block that expose functionalities that are handled by separate subsystems in the kernel, and there are registers that are shared between related drivers.
Switch the current device to an MFD device, add more descriptions about the subsystem and modify example accordingly.
Signed-off-by Ryder Lee <[email protected]>--- .../bindings/arm/mediatek/mediatek,audsys.txt | 37 ++++++++++++++++++---- 1 file changed, 30 insertions(+), 7 deletions(-)Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +0
-0
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt line 8
Quoted 9 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +6
-1@@ -1,22 +1,45 @@ -MediaTek AUDSYS controller +MediaTek Audio Subsystem ============================ +The audio subsystem is one of the multi-function blocks of MediaTek SoCs. +It contains a system controller, which provides a number registers giving +access to two features: AUDSYS clocks and Audio Front End (AFE) components. +For the top level node: +- compatible: must be: "syscon", "simple-mfd";
This should have some SoC specific compatible.
Quoted 9 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +6
-0+- reg: register area of the Audio Subsystem + +Required sub-nodes: + +AUDSYS clocks: +------- The MediaTek AUDSYS controller provides various clocks to the system. Required Properties:
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt line 26
Quoted 10 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +2
-1- compatible: Should be one of: - - "mediatek,mt7622-audsys", "syscon" + - "mediatek,mt2701-audsys"; + - "mediatek,mt7622-audsys"; - #clock-cells: Must be 1 The AUDSYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h.
There's no register range associated with the clocks? If there is, add a reg property.
Quoted 27 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +16
-5+AFE components: +------- +For common binding part and usage, refer to +../sonud/mt2701-afe-pcm.txt. + Example: -audsys: audsys at 11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x1000>; - #clock-cells = <1>; -}; + audio-subsystem at 11220000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x11220000 0 0x2000>; + + audsys: clock { + compatible = "mediatek,mt2701-audsys"; + #clock-cells = <1>; + }; + + ... + };Signature · 1 line
1.9.1
Re: [PATCH v2 4/5] dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
Quoted 25 lines · Rob Herring
Quoted 24 lines · Ryder Lee
As the MediaTek audio hardware block that expose functionalities that are handled by separate subsystems in the kernel, and there are registers that are shared between related drivers.
Switch the current device to an MFD device, add more descriptions about the subsystem and modify example accordingly.
Signed-off-by Ryder Lee <[email protected]>--- .../bindings/arm/mediatek/mediatek,audsys.txt | 37 ++++++++++++++++++---- 1 file changed, 30 insertions(+), 7 deletions(-)Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +4
-1@@ -1,22 +1,45 @@ -MediaTek AUDSYS controller +MediaTek Audio Subsystem ============================ +The audio subsystem is one of the multi-function blocks of MediaTek SoCs. +It contains a system controller, which provides a number registers giving +access to two features: AUDSYS clocks and Audio Front End (AFE) components.
Quoted 4 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt line 8
Quoted 2 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +2
-0+For the top level node: +- compatible: must be: "syscon", "simple-mfd";This should have some SoC specific compatible.
As we don't have a specific driver (compatible string) for it and if we need to add that I think the term '*-audsys' is very suitable here, but unfortunately, it has already picked for clock driver (see child node).
I also took ../../marvell/*-system-controller.txt as examples for my case. Thus, I'm not sure should we still need a new one here?
Quoted 16 lines
Quoted 16 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +8
-1+- reg: register area of the Audio Subsystem + +Required sub-nodes: + +AUDSYS clocks: +------- The MediaTek AUDSYS controller provides various clocks to the system. Required Properties: - compatible: Should be one of: - - "mediatek,mt7622-audsys", "syscon" + - "mediatek,mt2701-audsys"; + - "mediatek,mt7622-audsys"; - #clock-cells: Must be 1
Quoted 6 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt line 26
Quoted 3 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +0
-0The AUDSYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h.There's no register range associated with the clocks? If there is, add a reg property.
No, we don't need reg property here, as the two sub-drivers will obtain the regmap which is propagated from the parent.
Thanks
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +16
-5+AFE components: +------- +For common binding part and usage, refer to +../sonud/mt2701-afe-pcm.txt. + Example: -audsys: audsys at 11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x1000>; - #clock-cells = <1>; -}; + audio-subsystem at 11220000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x11220000 0 0x2000>; + + audsys: clock { + compatible = "mediatek,mt2701-audsys"; + #clock-cells = <1>; + }; + + ... + };Signature · 1 line
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Matthias Brugger
maintainerRe: [PATCH v2 2/5] clk: mediatek: modify MT7622 audsys to adapt MFD device
In reply to Ryder LeeQuoted 28 lines · Ryder Lee
Quoted 27 lines · Matthias Brugger
Quoted 12 lines · Ryder Lee
As the new MFD parent is in place, switch probing method to adapt it.
Signed-off-by Ryder Lee <[email protected]>--- drivers/clk/mediatek/clk-mt7622-aud.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/clk/mediatek/clk-mt7622-aud.c +0
-0drivers/clk/mediatek/clk-mt7622-aud.c static int clk_mt7622_audiosys_init(struct platform_device *pdev) · line 150
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drivers/clk/mediatek/clk-mt7622-aud.c +2
-1@@ -142,11 +142,12 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) {struct clk_onecell_data *clk_data;struct device_node *node = pdev->dev.of_node; +struct device_node *pnode = pdev->dev.parent->of_node;int r; clk_data =mtk_alloc_clk_data (CLK_AUDIO_NR_CLK ); - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), + mtk_clk_register_gates(pnode, audio_clks, ARRAY_SIZE(audio_clks),We will need a fallback here for older device tree bindings.
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Regards,
MatthiasUp to now, I didn't see both driver and bindings are used anywhere. Should I still care about that?
Yes please, we have to ensure that newer kernel work with older bindings and vice-versa.
Thanks,
Matthias
Rob Herring
maintainerRe: [PATCH v2 4/5] dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
In reply to Ryder LeeQuoted 26 lines · Ryder Lee
Quoted 25 lines · Rob Herring
Quoted 24 lines · Ryder Lee
As the MediaTek audio hardware block that expose functionalities that are handled by separate subsystems in the kernel, and there are registers that are shared between related drivers.
Switch the current device to an MFD device, add more descriptions about the subsystem and modify example accordingly.
Signed-off-by Ryder Lee <[email protected]>--- .../bindings/arm/mediatek/mediatek,audsys.txt | 37 ++++++++++++++++++---- 1 file changed, 30 insertions(+), 7 deletions(-)Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +4
-1@@ -1,22 +1,45 @@ -MediaTek AUDSYS controller +MediaTek Audio Subsystem ============================ +The audio subsystem is one of the multi-function blocks of MediaTek SoCs. +It contains a system controller, which provides a number registers giving +access to two features: AUDSYS clocks and Audio Front End (AFE) components.
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt line 8
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +2
-0+For the top level node: +- compatible: must be: "syscon", "simple-mfd";This should have some SoC specific compatible.
As we don't have a specific driver (compatible string) for it and if we need to add that I think the term '*-audsys' is very suitable here, but unfortunately, it has already picked for clock driver (see child node).
Perhaps the clocks block should have "-clk" on the end or something.
Why do you really need to change this in the first place? You don't have to have DT child nodes to create child (struct) devices and child drivers.
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I also took
../../marvell/*-system-controller.txtas examples for my case. Thus, I'm not sure should we still need a new one here?Quoted 16 lines
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +8
-1+- reg: register area of the Audio Subsystem + +Required sub-nodes: + +AUDSYS clocks: +------- The MediaTek AUDSYS controller provides various clocks to the system. Required Properties: - compatible: Should be one of: - - "mediatek,mt7622-audsys", "syscon" + - "mediatek,mt2701-audsys"; + - "mediatek,mt7622-audsys"; - #clock-cells: Must be 1Quoted 6 lines
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt line 26
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +0
-0The AUDSYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h.There's no register range associated with the clocks? If there is, add a reg property.
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No, we don't need reg property here, as the two sub-drivers will obtain the regmap which is propagated from the parent.
I know regmap doesn't need it. That's not what I asked. If you have a range of registers for the clocks, then define that in reg. Only if the clock control bits are mixed up with other functions within the same registers, then you can omit it.
Rob
Re: [PATCH v2 4/5] dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
Quoted 21 lines · Rob Herring
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +4
-1@@ -1,22 +1,45 @@ -MediaTek AUDSYS controller +MediaTek Audio Subsystem ============================ +The audio subsystem is one of the multi-function blocks of MediaTek SoCs. +It contains a system controller, which provides a number registers giving +access to two features: AUDSYS clocks and Audio Front End (AFE) components.Quoted 8 lines
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt line 8
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +2
-0+For the top level node: +- compatible: must be: "syscon", "simple-mfd";This should have some SoC specific compatible.
As we don't have a specific driver (compatible string) for it and if we need to add that I think the term '*-audsys' is very suitable here, but unfortunately, it has already picked for clock driver (see child node).
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Perhaps the clocks block should have "-clk" on the end or something.
Why do you really need to change this in the first place? You don't have to have DT child nodes to create child (struct) devices and child drivers.
I'm not sure I get your point. Did you mean that we could have a parent (which represents clock and its compatible is something like "*-audsys","syscon","simple-mfd") with a subnode for audio function?
If so, there's no special reason. I just think it more specifically to let people know we have an MFD (top node) and it has two sub-functions (children) share the same region.
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +4
-0+Required sub-nodes: + +AUDSYS clocks: +------- The MediaTek AUDSYS controller provides various clocks to the system. Required Properties:Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt line 26
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Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +2
-1- compatible: Should be one of: - - "mediatek,mt7622-audsys", "syscon" + - "mediatek,mt2701-audsys"; + - "mediatek,mt7622-audsys"; - #clock-cells: Must be 1 The AUDSYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h.There's no register range associated with the clocks? If there is, add a reg property.
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No, we don't need reg property here, as the two sub-drivers will obtain the regmap which is propagated from the parent.
I know regmap doesn't need it. That's not what I asked. If you have a range of registers for the clocks, then define that in reg. Only if the clock control bits are mixed up with other functions within the same registers, then you can omit it.
Oh okay, I didn't read the mail well. We have four or five registers for the clocks, but one of them (offset:0x634) is mixed up with the audio function (bit 17-19), so I omit it.
Ryder.
Re: [PATCH v2 2/5] clk: mediatek: modify MT7622 audsys to adapt MFD device
In reply to Matthias BruggerQuoted 33 lines · Matthias Brugger
Quoted 31 lines · Ryder Lee
Quoted 29 lines · Matthias Brugger
Quoted 12 lines · Ryder Lee
As the new MFD parent is in place, switch probing method to adapt it.
Signed-off-by Ryder Lee <[email protected]>--- drivers/clk/mediatek/clk-mt7622-aud.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/clk/mediatek/clk-mt7622-aud.c +0
-0drivers/clk/mediatek/clk-mt7622-aud.c static int clk_mt7622_audiosys_init(struct platform_device *pdev) · line 150
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drivers/clk/mediatek/clk-mt7622-aud.c +2
-1@@ -142,11 +142,12 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) {struct clk_onecell_data *clk_data;struct device_node *node = pdev->dev.of_node; +struct device_node *pnode = pdev->dev.parent->of_node;int r; clk_data =mtk_alloc_clk_data (CLK_AUDIO_NR_CLK ); - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), + mtk_clk_register_gates(pnode, audio_clks, ARRAY_SIZE(audio_clks),We will need a fallback here for older device tree bindings.
Regards,
Matthias
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Up to now, I didn't see both driver and bindings are used anywhere. Should I still care about that?
Yes please, we have to ensure that newer kernel work with older bindings and vice-versa.
OKay. An unrelated question - is it possible to change the compatible string (*-audsys-clk) without breaking backward compatible?
Matthias Brugger
maintainerRe: [PATCH v2 2/5] clk: mediatek: modify MT7622 audsys to adapt MFD device
Quoted 38 lines · Ryder Lee
Quoted 37 lines · Matthias Brugger
Quoted 34 lines · Ryder Lee
Quoted 22 lines · Matthias Brugger
Quoted 20 lines · Ryder Lee
As the new MFD parent is in place, switch probing method to adapt it.
Signed-off-by Ryder Lee <[email protected]>--- drivers/clk/mediatek/clk-mt7622-aud.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)drivers/clk/mediatek/clk-mt7622-aud.c +1
-0@@ -142,11 +142,12 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) {struct clk_onecell_data *clk_data;struct device_node *node = pdev->dev.of_node; +struct device_node *pnode = pdev->dev.parent->of_node;int r; clk_data =mtk_alloc_clk_data (CLK_AUDIO_NR_CLK );Quoted 7 lines
drivers/clk/mediatek/clk-mt7622-aud.c static int clk_mt7622_audiosys_init(struct platform_device *pdev) · line 150
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drivers/clk/mediatek/clk-mt7622-aud.c +1
-1- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), + mtk_clk_register_gates(pnode, audio_clks, ARRAY_SIZE(audio_clks),We will need a fallback here for older device tree bindings.
Regards,
MatthiasUp to now, I didn't see both driver and bindings are used anywhere. Should I still care about that?
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Yes please, we have to ensure that newer kernel work with older bindings and vice-versa.
OKay. An unrelated question - is it possible to change the compatible string (*-audsys-clk) without breaking backward compatible?
You can't change the compatible string, but you can add a new one, if the DT maintainer are ok with that. Beware that you won't be able to re-use the old one in a different driver.
Regards,
Matthias