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ARM64: dts: Fix incomplete cooling-maps

PATCH Applied Viresh Kumar 9 participants 20 messages Nov 16, 2018 – Nov 29, 2018

Subsystems (11)
Device tree bindings Arm Qualcomm mailing list Arm i.MX and Layerscape Arm/Amlogic Meson SoC support +7 more subsystems
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Viresh Kumar

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#0 lore raw

cover ARM64: dts: Fix incomplete cooling-maps

Hello,

Now that the below commit are merged in mainline, we can start fixing the ARM64 platform specific DT files:

commit d7a4303b8d1f ("dt-bindings: thermal: Allow multiple devices to share cooling map")

commit a92bab8919e3 ("of: thermal: Allow multiple devices to share cooling map")

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Individual maintainers can take the patches through their tree.

--
viresh

Viresh Kumar (10):
ARM64: dts: amlogic: Add all CPUs in cooling maps
ARM64: dts: exynos: Add all CPUs in cooling maps
ARM64: dts: fsl: Add all CPUs in cooling maps
arm64: dts: hi3660: Add missing cooling device properties for CPUs
ARM64: dts: hisilicon: Add all CPUs in cooling maps
ARM64: dts: mediatek: Add all CPUs in cooling maps
ARM64: dts: msm8916: Add all CPUs in cooling maps
ARM64: dts: renesas: Add all CPUs in cooling maps
ARM64: dts: rockchip: Add all CPUs in cooling maps
ARM64: dts: uniphier: Add all CPUs in cooling maps

 .../dts/amlogic/meson-gxm-khadas-vim2.dts     | 22 +++++-------
 .../arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 36 ++++++++++++-------
 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  6 ++--
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  6 ++--
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 17 +++++----
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 28 +++++----------
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi     | 16 +++++++--
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi     |  9 ++++-
 arch/arm64/boot/dts/mediatek/mt7622.dtsi      |  9 +++--
 arch/arm64/boot/dts/mediatek/mt8173.dtsi      |  6 ++--
 arch/arm64/boot/dts/qcom/msm8916.dtsi         | 10 ++++--
 arch/arm64/boot/dts/renesas/r8a7795.dtsi      | 15 ++++++--
 arch/arm64/boot/dts/renesas/r8a7796.dtsi      |  6 ++--
 arch/arm64/boot/dts/rockchip/rk3328.dtsi      |  5 ++-
 arch/arm64/boot/dts/rockchip/rk3368.dtsi      | 15 ++++++--
 .../boot/dts/rockchip/rk3399-gru-kevin.dts    |  8 +++--
 arch/arm64/boot/dts/rockchip/rk3399.dtsi      | 12 +++++--
 .../boot/dts/socionext/uniphier-ld20.dtsi     | 11 +++---
 18 files changed, 147 insertions(+), 90 deletions(-)
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#1 lore raw

PATCH 1/10 ARM64: dts: amlogic: Add all CPUs in cooling maps

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 .../dts/amlogic/meson-gxm-khadas-vim2.dts     | 22 ++++++++-----------
 1 file changed, 9 insertions(+), 13 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +9 -13
index 313f88f8759e..cfc92d06a28f 100644
@@ -132,19 +132,15 @@
 
 				map1 {
 					trip = <&cpu_alert1>;
-					cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>;
-				};
-
-				map2 {
-					trip = <&cpu_alert1>;
-					cooling-device =
-						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-
-				map3 {
-					trip = <&cpu_alert1>;
-					cooling-device =
-						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
+							 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#4 lore raw

PATCH 2/10 ARM64: dts: exynos: Add all CPUs in cooling maps

In reply to Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 .../arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 36 ++++++++++++-------
 1 file changed, 24 insertions(+), 12 deletions(-)
arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi +24 -12
index fe3a0b14bee6..81b72393dd0d 100644
@@ -55,37 +55,44 @@ thermal-zones {
 			map0 {
 				/* Set maximum frequency as 1800MHz  */
 				trip = <&atlas0_alert_0>;
-				cooling-device = <&cpu4 1 2>;
+				cooling-device = <&cpu4 1 2>, <&cpu5 1 2>,
+						 <&cpu6 1 2>, <&cpu7 1 2>;
 			};
 			map1 {
 				/* Set maximum frequency as 1700MHz  */
 				trip = <&atlas0_alert_1>;
-				cooling-device = <&cpu4 2 3>;
+				cooling-device = <&cpu4 2 3>, <&cpu5 2 3>,
+						 <&cpu6 2 3>, <&cpu7 2 3>;
 			};
 			map2 {
 				/* Set maximum frequency as 1600MHz  */
 				trip = <&atlas0_alert_2>;
-				cooling-device = <&cpu4 3 4>;
+				cooling-device = <&cpu4 3 4>, <&cpu5 3 4>,
+						 <&cpu6 3 4>, <&cpu7 3 4>;
 			};
 			map3 {
 				/* Set maximum frequency as 1500MHz  */
 				trip = <&atlas0_alert_3>;
-				cooling-device = <&cpu4 4 5>;
+				cooling-device = <&cpu4 4 5>, <&cpu5 4 5>,
+						 <&cpu6 4 5>, <&cpu7 4 5>;
 			};
 			map4 {
 				/* Set maximum frequency as 1400MHz  */
 				trip = <&atlas0_alert_4>;
-				cooling-device = <&cpu4 5 7>;
+				cooling-device = <&cpu4 5 7>, <&cpu5 5 7>,
+						 <&cpu6 5 7>, <&cpu7 5 7>;
 			};
 			map5 {
 				/* Set maximum frequencyas 1200MHz  */
 				trip = <&atlas0_alert_5>;
-				cooling-device = <&cpu4 7 9>;
+				cooling-device = <&cpu4 7 9>, <&cpu5 7 9>,
+						 <&cpu6 7 9>, <&cpu7 7 9>;
 			};
 			map6 {
 				/* Set maximum frequency as 1000MHz  */
 				trip = <&atlas0_alert_6>;
-				cooling-device = <&cpu4 9 14>;
+				cooling-device = <&cpu4 9 14>, <&cpu5 9 14>,
+						 <&cpu6 9 14>, <&cpu7 9 14>;
 			};
 		};
 	};

@@ -222,27 +229,32 @@ thermal-zones {
 			map0 {
 				/* Set maximum frequency as 1200MHz  */
 				trip = <&apollo_alert_2>;
-				cooling-device = <&cpu0 1 2>;
+				cooling-device = <&cpu0 1 2>, <&cpu1 1 2>,
+						 <&cpu2 1 2>, <&cpu3 1 2>;
 			};
 			map1 {
 				/* Set maximum frequency as 1100MHz  */
 				trip = <&apollo_alert_3>;
-				cooling-device = <&cpu0 2 3>;
+				cooling-device = <&cpu0 2 3>, <&cpu1 2 3>,
+						 <&cpu2 2 3>, <&cpu3 2 3>;
 			};
 			map2 {
 				/* Set maximum frequency as 1000MHz  */
 				trip = <&apollo_alert_4>;
-				cooling-device = <&cpu0 3 4>;
+				cooling-device = <&cpu0 3 4>, <&cpu1 3 4>,
+						 <&cpu2 3 4>, <&cpu3 3 4>;
 			};
 			map3 {
 				/* Set maximum frequency as 900MHz  */
 				trip = <&apollo_alert_5>;
-				cooling-device = <&cpu0 4 5>;
+				cooling-device = <&cpu0 4 5>, <&cpu1 4 5>,
+						 <&cpu2 4 5>, <&cpu3 4 5>;
 			};
 			map4 {
 				/* Set maximum frequency as 800MHz  */
 				trip = <&apollo_alert_6>;
-				cooling-device = <&cpu0 5 9>;
+				cooling-device = <&cpu0 5 9>, <&cpu1 5 9>,
+						 <&cpu2 5 9>, <&cpu3 5 9>;
 			};
 		};
 	};
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#6 lore raw

PATCH 3/10 ARM64: dts: fsl: Add all CPUs in cooling maps

In reply to Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  6 ++--
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  6 ++--
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 17 ++++++-----
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 28 ++++++-------------
 4 files changed, 24 insertions(+), 33 deletions(-)
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +4 -2
index 3fed504b5381..c7224c5bb6cc 100644
@@ -171,8 +171,10 @@
 				map0 {
 					trip = <&cpu_alert>;
 					cooling-device =
-						<&cpu0 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +4 -2
index 51cbd50012d6..8c94d8279b5e 100644
@@ -140,8 +140,10 @@
 				map0 {
 					trip = <&cpu_alert>;
 					cooling-device =
-						<&cpu0 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +8 -9
index a07f612ab56b..7faee0d270d2 100644
@@ -152,15 +152,14 @@
 				map0 {
 					trip = <&cpu_alert>;
 					cooling-device =
-						<&cpu0 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
-				};
-
-				map1 {
-					trip = <&cpu_alert>;
-					cooling-device =
-						<&cpu4 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +8 -20
index d188774a36e8..f11187f7465c 100644
@@ -101,26 +101,14 @@
 				map0 {
 					trip = <&cpu_alert>;
 					cooling-device =
-						<&cpu0 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
-				};
-				map1 {
-					trip = <&cpu_alert>;
-					cooling-device =
-						<&cpu2 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
-				};
-				map2 {
-					trip = <&cpu_alert>;
-					cooling-device =
-						<&cpu4 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
-				};
-				map3 {
-					trip = <&cpu_alert>;
-					cooling-device =
-						<&cpu6 THERMAL_NO_LIMIT
-						THERMAL_NO_LIMIT>;
+						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#8 lore raw

PATCH 4/10 arm64: dts: hi3660: Add missing cooling device properties for CPUs

In reply to Viresh Kumar

The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm64/boot/dts/hisilicon/hi3660.dtsi +6 -0
index f432b0a88c65..d943a96eedee 100644
@@ -79,6 +79,7 @@
 			capacity-dmips-mhz = <592>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu at 2 {

@@ -91,6 +92,7 @@
 			capacity-dmips-mhz = <592>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu at 3 {

@@ -103,6 +105,7 @@
 			capacity-dmips-mhz = <592>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu4: cpu at 100 {

@@ -129,6 +132,7 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu6: cpu at 102 {

@@ -141,6 +145,7 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu7: cpu at 103 {

@@ -153,6 +158,7 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
 		};
 
 		idle-states {
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#10 lore raw

PATCH 5/10 ARM64: dts: hisilicon: Add all CPUs in cooling maps

In reply to Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++++++++--
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi |  9 ++++++++-
 2 files changed, 16 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/hisilicon/hi3660.dtsi +8 -2
index d943a96eedee..20ae40df61d5 100644
@@ -1118,12 +1118,18 @@
 					map0 {
 						trip = <&target>;
 						contribution = <1024>;
-						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 					};
 					map1 {
 						trip = <&target>;
 						contribution = <512>;
-						cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 					};
 				};
 			};
arch/arm64/boot/dts/hisilicon/hi6220.dtsi +8 -1
index 97d5bf2c6ec5..aec9e371c2a7 100644
@@ -893,7 +893,14 @@
 				cooling-maps {
 					map0 {
 						trip = <&target>;
-						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 					};
 				};
 			};
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#12 lore raw

PATCH 6/10 ARM64: dts: mediatek: Add all CPUs in cooling maps

In reply to Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 9 ++++++---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++++--
 2 files changed, 10 insertions(+), 5 deletions(-)
arch/arm64/boot/dts/mediatek/mt7622.dtsi +6 -3
index fe0c875f1d95..53e707df98d9 100644
@@ -170,17 +170,20 @@
 			cooling-maps {
 				map0 {
 					trip = <&cpu_passive>;
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 
 				map1 {
 					trip = <&cpu_active>;
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 
 				map2 {
 					trip = <&cpu_hot>;
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
arch/arm64/boot/dts/mediatek/mt8173.dtsi +4 -2
index abd2f15a544b..e578f7d18038 100644
@@ -275,12 +275,14 @@
 			cooling-maps {
 				map at 0 {
 					trip = <&target>;
-					cooling-device = <&cpu0 0 0>;
+					cooling-device = <&cpu0 0 0>,
+							 <&cpu1 0 0>;
 					contribution = <3072>;
 				};
 				map at 1 {
 					trip = <&target>;
-					cooling-device = <&cpu2 0 0>;
+					cooling-device = <&cpu2 0 0>,
+							 <&cpu3 0 0>;
 					contribution = <1024>;
 				};
 			};
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#13 lore raw

PATCH 7/10 ARM64: dts: msm8916: Add all CPUs in cooling maps

In reply to Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/qcom/msm8916.dtsi +8 -2
index d302d8d639a1..482e275f0a03 100644
@@ -202,7 +202,10 @@
 			cooling-maps {
 				map0 {
 					trip = <&cpu_alert0>;
-					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};

@@ -229,7 +232,10 @@
 			cooling-maps {
 				map0 {
 					trip = <&cpu_alert1>;
-					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#14 lore raw

PATCH 8/10 ARM64: dts: renesas: Add all CPUs in cooling maps

In reply to Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 ++++++++++++---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi |  6 +++---
 2 files changed, 15 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +12 -3
index a79c8d369e0b..3a662df32143 100644
@@ -2878,7 +2878,10 @@
 			cooling-maps {
 				map0 {
 					trip = <&sensor1_passive>;
-					cooling-device = <&a57_0 4 4>;
+					cooling-device = <&a57_0 4 4>,
+							 <&a57_1 4 4>,
+							 <&a57_2 4 4>,
+							 <&a57_3 4 4>;
 				};
 			};
 		};

@@ -2904,7 +2907,10 @@
 			cooling-maps {
 				map0 {
 					trip = <&sensor2_passive>;
-					cooling-device = <&a57_0 4 4>;
+					cooling-device = <&a57_0 4 4>,
+							 <&a57_1 4 4>,
+							 <&a57_2 4 4>,
+							 <&a57_3 4 4>;
 				};
 			};
 		};

@@ -2930,7 +2936,10 @@
 			cooling-maps {
 				map0 {
 					trip = <&sensor3_passive>;
-					cooling-device = <&a57_0 4 4>;
+					cooling-device = <&a57_0 4 4>,
+							 <&a57_1 4 4>,
+							 <&a57_2 4 4>,
+							 <&a57_3 4 4>;
 				};
 			};
 		};
arch/arm64/boot/dts/renesas/r8a7796.dtsi +3 -3
index 1ec6aaa520c1..dd95e937f87a 100644
@@ -2526,7 +2526,7 @@
 			cooling-maps {
 				map0 {
 					trip = <&sensor1_passive>;
-					cooling-device = <&a57_0 5 5>;
+					cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
 				};
 			};
 		};

@@ -2552,7 +2552,7 @@
 			cooling-maps {
 				map0 {
 					trip = <&sensor2_passive>;
-					cooling-device = <&a57_0 5 5>;
+					cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
 				};
 			};
 		};

@@ -2578,7 +2578,7 @@
 			cooling-maps {
 				map0 {
 					trip = <&sensor3_passive>;
-					cooling-device = <&a57_0 5 5>;
+					cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
 				};
 			};
 		};
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#16 lore raw

PATCH 9/10 ARM64: dts: rockchip: Add all CPUs in cooling maps

In reply to Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3328.dtsi          |  5 ++++-
 arch/arm64/boot/dts/rockchip/rk3368.dtsi          | 15 ++++++++++++---
 arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts |  8 ++++++--
 arch/arm64/boot/dts/rockchip/rk3399.dtsi          | 12 +++++++++---
 4 files changed, 31 insertions(+), 9 deletions(-)
arch/arm64/boot/dts/rockchip/rk3328.dtsi +4 -1
index e1a33dd981e0..ecd7f19c3542 100644
@@ -479,7 +479,10 @@
 			cooling-maps {
 				map0 {
 					trip = <&target>;
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 					contribution = <4096>;
 				};
 			};
arch/arm64/boot/dts/rockchip/rk3368.dtsi +12 -3
index 9c24de1ba43c..7014d10b954c 100644
@@ -426,12 +426,18 @@
 				map0 {
 					trip = <&cpu_alert0>;
 					cooling-device =
-					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 				map1 {
 					trip = <&cpu_alert1>;
 					cooling-device =
-					<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};

@@ -459,7 +465,10 @@
 				map0 {
 					trip = <&gpu_alert0>;
 					cooling-device =
-					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +6 -2
index 2cc7c47d6a85..81e73103fa78 100644
@@ -118,13 +118,17 @@
 			map0 {
 				trip = <&ppvar_bigcpu_alert>;
 				cooling-device =
-					<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				contribution = <4096>;
 			};
 			map1 {
 				trip = <&ppvar_bigcpu_alert>;
 				cooling-device =
-					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				contribution = <1024>;
 			};
 		};
arch/arm64/boot/dts/rockchip/rk3399.dtsi +9 -3
index 99e7f65c1779..d4ebffc28953 100644
@@ -770,13 +770,18 @@
 				map0 {
 					trip = <&cpu_alert0>;
 					cooling-device =
-						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 				map1 {
 					trip = <&cpu_alert1>;
 					cooling-device =
 						<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};

@@ -804,7 +809,8 @@
 				map0 {
 					trip = <&gpu_alert0>;
 					cooling-device =
-						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
Signature · 1 line
2.19.1.568.g152ad8e3369a
author
#18 lore raw

PATCH 10/10 ARM64: dts: uniphier: Add all CPUs in cooling maps

In reply to Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +4 -7
index d7e2d8969601..4a0c46cb11cd 100644
@@ -206,13 +206,10 @@
 			cooling-maps {
 				map0 {
 					trip = <&cpu_alert>;
-					cooling-device = <&cpu0
-					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-				map1 {
-					trip = <&cpu_alert>;
-					cooling-device = <&cpu2
-					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
Signature · 1 line
2.19.1.568.g152ad8e3369a
Acked-by on v1 1/10
#2 lore raw

Re: [PATCH 01/10] ARM64: dts: amlogic: Add all CPUs in cooling maps

In reply to Viresh Kumar
Quoted 43 lines · Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 .../dts/amlogic/meson-gxm-khadas-vim2.dts     | 22 ++++++++-----------
 1 file changed, 9 insertions(+), 13 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +2 -13
index 313f88f8759e..cfc92d06a28f 100644
@@ -132,19 +132,15 @@
 
 				map1 {
 					trip = <&cpu_alert1>;
-					cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>;
-				};
-
-				map2 {
-					trip = <&cpu_alert1>;
-					cooling-device =
-						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-
-				map3 {
-					trip = <&cpu_alert1>;
-					cooling-device =
-						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+					cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
+							 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,

arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts line 146

Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +7 -0
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 				};
 			};
 		};
Acked-by Neil Armstrong <[email protected]>
maintainer Applied
#5 lore raw

Re: [PATCH 02/10] ARM64: dts: exynos: Add all CPUs in cooling maps

In reply to Viresh Kumar
Quoted 11 lines · Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Quoted 6 lines

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>
---
 .../arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 36 ++++++++++++-------

Thanks, applied.

Best regards,
Krzysztof

Applied
#15 lore raw

Re: [PATCH 08/10] ARM64: dts: renesas: Add all CPUs in cooling maps

In reply to Viresh Kumar
Quoted 8 lines · Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Quoted 7 lines

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>

Thanks, applied for v4.21.

maintainer
#17 lore raw

Re: [PATCH 09/10] ARM64: dts: rockchip: Add all CPUs in cooling maps

In reply to Viresh Kumar

Am Freitag, 16. November 2018, 11:04:32 CET schrieb Viresh Kumar:

Quoted 8 lines

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Quoted 7 lines

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>

looks like I forgot to respond ... applied like 7 days ago and already part of my pull-request for 4.21

Thanks
Heiko

Applied
#19 lore raw

Re: [PATCH 10/10] ARM64: dts: uniphier: Add all CPUs in cooling maps

In reply to Viresh Kumar
Quoted 9 lines · Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Quoted 7 lines

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>

Applied to linux-uniphier.
Thanks.

Quoted 29 lines
---
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +4 -8
index d7e2d8969601..4a0c46cb11cd 100644
@@ -206,13 +206,10 @@
                        cooling-maps {
                                map0 {
                                        trip = <&cpu_alert>;
-                                       cooling-device = <&cpu0
-                                           THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-                               };
-                               map1 {
-                                       trip = <&cpu_alert>;
-                                       cooling-device = <&cpu2
-                                           THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                                };
                        };
                };
--

2.19.1.568.g152ad8e3369a

Signature · 2 lines
Best Regards
Masahiro Yamada
Applied
#7 lore raw

Re: [PATCH 03/10] ARM64: dts: fsl: Add all CPUs in cooling maps

In reply to Viresh Kumar
Quoted 8 lines · Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Quoted 7 lines

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>

Applied, thanks.

maintainer
#3 lore raw

Re: [PATCH 01/10] ARM64: dts: amlogic: Add all CPUs in cooling maps

In reply to Viresh Kumar
Quoted 8 lines · Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Quoted 7 lines

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>

Queued for v4.21,

Thanks!

Kevin

maintainer Applied
#9 lore raw

Re: [PATCH 04/10] arm64: dts: hi3660: Add missing cooling device properties for CPUs

In reply to Viresh Kumar

Hi Viresh,

Quoted 11 lines · Viresh Kumar

The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Signed-off-by Viresh Kumar <[email protected]>

Applied to the hisilicon soc dt tree.
Thanks!

Best Regards,
Wei

Quoted 57 lines
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm64/boot/dts/hisilicon/hi3660.dtsi +6 -0
index f432b0a88c65..d943a96eedee 100644
@@ -79,6 +79,7 @@
 			capacity-dmips-mhz = <592>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu@2 {

@@ -91,6 +92,7 @@
 			capacity-dmips-mhz = <592>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@3 {

@@ -103,6 +105,7 @@
 			capacity-dmips-mhz = <592>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu4: cpu@100 {

@@ -129,6 +132,7 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu6: cpu@102 {

@@ -141,6 +145,7 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu7: cpu@103 {

@@ -153,6 +158,7 @@
 			capacity-dmips-mhz = <1024>;
 			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
 		};
 
 		idle-states {
maintainer Applied
#11 lore raw

Re: [PATCH 05/10] ARM64: dts: hisilicon: Add all CPUs in cooling maps

In reply to Viresh Kumar

Hi Viresh,

Quoted 8 lines · Viresh Kumar

Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.

Quoted 7 lines

Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip points.

Signed-off-by Viresh Kumar <[email protected]>

Applied to the hisilicon soc dt tree.
Thanks!

Best Regards,
Wei

Quoted 51 lines
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 10 ++++++++--
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi |  9 ++++++++-
 2 files changed, 16 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/hisilicon/hi3660.dtsi +8 -2
index d943a96eedee..20ae40df61d5 100644
@@ -1118,12 +1118,18 @@
 					map0 {
 						trip = <&target>;
 						contribution = <1024>;
-						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 					};
 					map1 {
 						trip = <&target>;
 						contribution = <512>;
-						cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 					};
 				};
 			};
arch/arm64/boot/dts/hisilicon/hi6220.dtsi +8 -1
index 97d5bf2c6ec5..aec9e371c2a7 100644
@@ -893,7 +893,14 @@
 				cooling-maps {
 					map0 {
 						trip = <&target>;
-						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 					};
 				};
 			};