drm/i915/icl: dsi enabling

PATCH In review Jani Nikula 4 participants 47 messages Nov 29, 2018 – Dec 7, 2018

Subsystems (2)

DRM drivers Intel i915

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Jani Nikula

author

2018-11-29 14:12 UTC #0 lore raw

v11 cover drm/i915/icl: dsi enabling

v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.

It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.

The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].

BR,
Jani.

[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3] http://patchwork.freedesktop.org/patch/msgid/[email protected]
[4] http://patchwork.freedesktop.org/patch/msgid/[email protected]
[5] https://cgit.freedesktop.org/~jani/drm/

Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports

Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox

Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI

Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI

 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)

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2.11.0

_______________________________________________
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Jani Nikula

author

2018-11-29 14:12 UTC #1 lore raw

PATCH v11 1/23 drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks

Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions a bit by moving the pll to port mapping and unmapping functions to the ddi encoder hooks. This allows removal of a bunch of boilerplate code from the functions.

Additionally, the ICL DSI encoder needs to do the clock gating and ungating slightly differently, and this allows its own handling in a clean fashion.

Cc Madhav Chauhan <[email protected]>

Cc Paulo Zanoni <[email protected]>

Cc Ville Syrjälä <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_ddi.c     | 84 +++++++++++++++---------------------
 drivers/gpu/drm/i915/intel_display.c |  6 ---
 drivers/gpu/drm/i915/intel_drv.h     |  6 ---
 3 files changed, 34 insertions(+), 62 deletions(-)

drivers/gpu/drm/i915/intel_ddi.c +34 ~~-50~~

index ad11540ac436..7bad6c857b81 100644
@@ -2785,69 +2785,45 @@ uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
-void icl_map_plls_to_ports(struct drm_crtc *crtc,
-			   struct intel_crtc_state *crtc_state,
-			   struct drm_atomic_state *old_state)
+static void icl_map_plls_to_ports(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	struct drm_connector_state *conn_state;
-	struct drm_connector *conn;
-	int i;
-
-	for_each_new_connector_in_state(old_state, conn, conn_state, i) {
-		struct intel_encoder *encoder =
-			to_intel_encoder(conn_state->best_encoder);
-		enum port port;
-		uint32_t val;
-
-		if (conn_state->crtc != crtc)
-			continue;
-
-		port = encoder->port;
-		mutex_lock(&dev_priv->dpll_lock);
+	enum port port = encoder->port;
+	u32 val;
 
-		val = I915_READ(DPCLKA_CFGCR0_ICL);
-		WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+	mutex_lock(&dev_priv->dpll_lock);
 
-		if (intel_port_is_combophy(dev_priv, port)) {
-			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
-			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
-			POSTING_READ(DPCLKA_CFGCR0_ICL);
-		}
+	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
 
-		val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	if (intel_port_is_combophy(dev_priv, port)) {
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
-
-		mutex_unlock(&dev_priv->dpll_lock);
+		POSTING_READ(DPCLKA_CFGCR0_ICL);
 	}
+
+	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+	mutex_unlock(&dev_priv->dpll_lock);
 }
 
-void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
-			     struct intel_crtc_state *crtc_state,
-			     struct drm_atomic_state *old_state)
+static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	struct drm_connector_state *old_conn_state;
-	struct drm_connector *conn;
-	int i;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+	u32 val;
 
-	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
-		struct intel_encoder *encoder =
-			to_intel_encoder(old_conn_state->best_encoder);
-		enum port port;
+	mutex_lock(&dev_priv->dpll_lock);
 
-		if (old_conn_state->crtc != crtc)
-			continue;
+	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
-		port = encoder->port;
-		mutex_lock(&dev_priv->dpll_lock);
-		I915_WRITE(DPCLKA_CFGCR0_ICL,
-			   I915_READ(DPCLKA_CFGCR0_ICL) |
-			   icl_dpclka_cfgcr0_clk_off(dev_priv, port));
-		mutex_unlock(&dev_priv->dpll_lock);
-	}
+	mutex_unlock(&dev_priv->dpll_lock);
 }
 
 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)

@@ -3208,6 +3184,9 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
 
 	WARN_ON(crtc_state->has_pch_encoder);
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_map_plls_to_ports(encoder, crtc_state);
+
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

@@ -3306,6 +3285,8 @@ static void intel_ddi_post_disable(struct intel_encoder *encoder,
 				   const struct intel_crtc_state *old_crtc_state,
 				   const struct drm_connector_state *old_conn_state)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
 	/*
 	 * When called from DP MST code:
 	 * - old_conn_state will be NULL

@@ -3325,6 +3306,9 @@ static void intel_ddi_post_disable(struct intel_encoder *encoder,
 	else
 		intel_ddi_post_disable_dp(encoder,
 					  old_crtc_state, old_conn_state);
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_unmap_plls_to_ports(encoder);
 }
 
 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_display.c +0 -6

index d07fa4456150..559db98b5a4a 100644
@@ -5704,9 +5704,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (pipe_config->shared_dpll)
 		intel_enable_shared_dpll(pipe_config);
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		icl_map_plls_to_ports(crtc, pipe_config, old_state);
-
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
 	if (intel_crtc_has_dp_encoder(pipe_config))

@@ -5908,9 +5905,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 
 	intel_encoders_post_disable(crtc, old_crtc_state, old_state);
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
-
 	intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
 }

drivers/gpu/drm/i915/intel_drv.h +0 -6

index 40edb21087a7..9018be2171ee 100644
@@ -1522,12 +1522,6 @@ u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
 				 u8 voltage_swing);
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 				     bool enable);
-void icl_map_plls_to_ports(struct drm_crtc *crtc,
-			   struct intel_crtc_state *crtc_state,
-			   struct drm_atomic_state *old_state);
-void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
-			     struct intel_crtc_state *crtc_state,
-			     struct drm_atomic_state *old_state);
 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
 
 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-11-29 14:12 UTC #3 lore raw

PATCH v11 2/23 drm/i915/icl: Sanitize DDI port clock gating for DSI ports

In reply to Jani Nikula

From: Imre Deak <[email protected]>

The requirement for the DDI port clock gating for a port in DSI mode is the opposite wrt. the case when the port is in DDI mode: the clock should be gated when the port is active and ungated when the port is inactive. Note that we cannot simply keep the DDI clock gated when the port will be only used in DSI mode: it must be gated/ungated at a specific spot in the DSI enable/disable sequence.

Ensure the above for all ports of a DSI encoder, also adding a sanity check that we haven't registered another encoder using the same port (VBT should never allow this to happen).

Cc Madhav Chauhan <[email protected]>

Cc Vandita Kulkarni <[email protected]>

Cc Jani Nikula <[email protected]>

Cc Ville Syrjälä <[email protected]>

Cc Clint Taylor <[email protected]>

Reviewed-by Jani Nikula <[email protected]>

Signed-off-by Imre Deak <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_ddi.c | 65 +++++++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_dsi.h |  5 ++++
 2 files changed, 53 insertions(+), 17 deletions(-)

drivers/gpu/drm/i915/intel_ddi.c +48 ~~-17~~

index 7bad6c857b81..b5fdf9a15338 100644
@@ -28,6 +28,7 @@
 #include <drm/drm_scdc_helper.h>
 #include "i915_drv.h"
 #include "intel_drv.h"
+#include "intel_dsi.h"
 
 struct ddi_buf_trans {
 	u32 trans1;	/* balance leg enable, de-emph level */

@@ -2830,8 +2831,9 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	u32 val;
-	enum port port = encoder->port;
-	bool clk_enabled;
+	enum port port;
+	u32 port_mask;
+	bool ddi_clk_needed;
 
 	/*
 	 * In case of DP MST, we sanitize the primary encoder only, not the

@@ -2840,9 +2842,6 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 	if (encoder->type == INTEL_OUTPUT_DP_MST)
 		return;
 
-	val = I915_READ(DPCLKA_CFGCR0_ICL);
-	clk_enabled = !(val & icl_dpclka_cfgcr0_clk_off(dev_priv, port));
-
 	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
 		u8 pipe_mask;
 		bool is_mst;

@@ -2856,20 +2855,52 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 			return;
 	}
 
-	if (clk_enabled == !!encoder->base.crtc)
-		return;
+	port_mask = BIT(encoder->port);
+	ddi_clk_needed = encoder->base.crtc;
 
-	/*
-	 * Punt on the case now where clock is disabled, but the encoder is
-	 * enabled, something else is really broken then.
-	 */
-	if (WARN_ON(!clk_enabled))
-		return;
+	if (encoder->type == INTEL_OUTPUT_DSI) {
+		struct intel_encoder *other_encoder;
 
-	DRM_NOTE("Port %c is disabled but it has a mapped PLL, unmap it\n",
-		 port_name(port));
-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
-	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+		port_mask = intel_dsi_encoder_ports(encoder);
+		/*
+		 * Sanity check that we haven't incorrectly registered another
+		 * encoder using any of the ports of this DSI encoder.
+		 */
+		for_each_intel_encoder(&dev_priv->drm, other_encoder) {
+			if (other_encoder == encoder)
+				continue;
+
+			if (WARN_ON(port_mask & BIT(other_encoder->port)))
+				return;
+		}
+		/*
+		 * DSI ports should have their DDI clock ungated when disabled
+		 * and gated when enabled.
+		 */
+		ddi_clk_needed = !encoder->base.crtc;
+	}
+
+	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	for_each_port_masked(port, port_mask) {
+		bool ddi_clk_ungated = !(val &
+					 icl_dpclka_cfgcr0_clk_off(dev_priv,
+								   port));
+
+		if (ddi_clk_needed == ddi_clk_ungated)
+			continue;
+
+		/*
+		 * Punt on the case now where clock is gated, but it would
+		 * be needed by the port. Something else is really broken then.
+		 */
+		if (WARN_ON(ddi_clk_needed))
+			continue;
+
+		DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+			 port_name(port));
+		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+	}
 }
 
 static void intel_ddi_clk_select(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_dsi.h +5 -0

index ee93137f4433..d968f1f13e09 100644
@@ -146,6 +146,11 @@ static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
 	return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
 }
 
+static inline u16 intel_dsi_encoder_ports(struct intel_encoder *encoder)
+{
+	return enc_to_intel_dsi(&encoder->base)->ports;
+}
+
 /* intel_dsi.c */
 int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
 int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-11-29 14:12 UTC #4 lore raw

PATCH v11 3/23 drm/i915/icl: Calculate DPLL params for DSI

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

This patch calculates various DPLL dividers and
parameters for DSI encoder and adjust AFE clock
for DSI. For DSI, 8x clock is AFE clock.

v2: Extend haswell_crtc_compute_clock() for Gen11 DSI

v3: Rebase

v4: use port clock instead of bitrate.

v5: Reabse and remove divide by 5

v6 by Jani:
- Fix indent (Madhav)
- Fix dpll state calc for EDP and DP MST

Co-developed-by Vandita Kulkarni <[email protected]>

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Vandita Kulkarni <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_display.c  | 4 +++-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 3 ++-
 2 files changed, 5 insertions(+), 2 deletions(-)

drivers/gpu/drm/i915/intel_display.c +3 -1

index 559db98b5a4a..1e4261f524f4 100644
@@ -9309,10 +9309,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_atomic_state *state =
 		to_intel_atomic_state(crtc_state->base.state);
 
-	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
+	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
+	    IS_ICELAKE(dev_priv)) {
 		struct intel_encoder *encoder =
 			intel_get_crtc_new_encoder(state, crtc_state);

drivers/gpu/drm/i915/intel_dpll_mgr.c +2 -1

index 901e15063b24..d513ca875c67 100644
@@ -2523,7 +2523,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
 
 	if (intel_port_is_tc(dev_priv, encoder->port))
 		ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
-	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
+		 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 		ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
 	else
 		ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-11-29 14:12 UTC #5 lore raw

PATCH v11 4/23 drm/i915/icl: Allocate DSI encoder/connector

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

This patch allocates memory for DSI encoder and connector which will be used for various DSI encoder/connector operations and attaching the same to DRM subsystem. This patch also extracts DSI modes info from VBT and save the desired mode info to connector.

v2 by Jani:
- Drop GEN11 prefix from encoder name
- Drop extra parenthesis
- Drop extra local variable
- Squash encoder power domain here

v3 by Jani:
- Squash connector and connector helper functions here
- Move intel_dsi_vbt_init call here

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 117 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 109 insertions(+), 8 deletions(-)

drivers/gpu/drm/i915/icl_dsi.c +109 -8

index 01f422df8c23..a40083a7eb6a 100644
@@ -26,6 +26,7 @@
  */
 
 #include <drm/drm_mipi_dsi.h>
+#include <drm/drm_atomic_helper.h>
 #include "intel_dsi.h"
 
 static inline int header_credits_available(struct drm_i915_private *dev_priv,

@@ -799,10 +800,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 	wait_for_cmds_dispatched_to_panel(encoder);
 }
 
-static void __attribute__((unused))
-gen11_dsi_pre_enable(struct intel_encoder *encoder,
-		     const struct intel_crtc_state *pipe_config,
-		     const struct drm_connector_state *conn_state)
+static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *pipe_config,
+				 const struct drm_connector_state *conn_state)
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

@@ -945,10 +945,9 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
 	}
 }
 
-static void __attribute__((unused)) gen11_dsi_disable(
-			struct intel_encoder *encoder,
-			const struct intel_crtc_state *old_crtc_state,
-			const struct drm_connector_state *old_conn_state)
+static void gen11_dsi_disable(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *old_crtc_state,
+			      const struct drm_connector_state *old_conn_state)
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

@@ -972,10 +971,112 @@ static void __attribute__((unused)) gen11_dsi_disable(
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
+{
+	intel_encoder_destroy(encoder);
+}
+
+static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
+	.destroy = gen11_dsi_encoder_destroy,
+};
+
+static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
+	.late_register = intel_connector_register,
+	.early_unregister = intel_connector_unregister,
+	.destroy = intel_connector_destroy,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.atomic_get_property = intel_digital_connector_atomic_get_property,
+	.atomic_set_property = intel_digital_connector_atomic_set_property,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
+};
+
+static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
+	.get_modes = intel_dsi_get_modes,
+	.mode_valid = intel_dsi_mode_valid,
+	.atomic_check = intel_digital_connector_atomic_check,
+};
+
 void icl_dsi_init(struct drm_i915_private *dev_priv)
 {
+	struct drm_device *dev = &dev_priv->drm;
+	struct intel_dsi *intel_dsi;
+	struct intel_encoder *encoder;
+	struct intel_connector *intel_connector;
+	struct drm_connector *connector;
+	struct drm_display_mode *scan, *fixed_mode = NULL;
 	enum port port;
 
 	if (!intel_bios_is_dsi_present(dev_priv, &port))
 		return;
+
+	intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
+	if (!intel_dsi)
+		return;
+
+	intel_connector = intel_connector_alloc();
+	if (!intel_connector) {
+		kfree(intel_dsi);
+		return;
+	}
+
+	encoder = &intel_dsi->base;
+	intel_dsi->attached_connector = intel_connector;
+	connector = &intel_connector->base;
+
+	/* register DSI encoder with DRM subsystem */
+	drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
+			 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
+
+	encoder->pre_enable = gen11_dsi_pre_enable;
+	encoder->disable = gen11_dsi_disable;
+	encoder->port = port;
+	encoder->type = INTEL_OUTPUT_DSI;
+	encoder->cloneable = 0;
+	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
+	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+
+	/* register DSI connector with DRM subsystem */
+	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
+			   DRM_MODE_CONNECTOR_DSI);
+	drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
+	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
+	connector->interlace_allowed = false;
+	connector->doublescan_allowed = false;
+
+	/* attach connector to encoder */
+	intel_connector_attach_encoder(intel_connector, encoder);
+
+	/* fill mode info from VBT */
+	mutex_lock(&dev->mode_config.mutex);
+	intel_dsi_vbt_get_modes(intel_dsi);
+	list_for_each_entry(scan, &connector->probed_modes, head) {
+		if (scan->type & DRM_MODE_TYPE_PREFERRED) {
+			fixed_mode = drm_mode_duplicate(dev, scan);
+			break;
+		}
+	}
+	mutex_unlock(&dev->mode_config.mutex);
+
+	if (!fixed_mode) {
+		DRM_ERROR("DSI fixed mode info missing\n");
+		goto err;
+	}
+
+	connector->display_info.width_mm = fixed_mode->width_mm;
+	connector->display_info.height_mm = fixed_mode->height_mm;
+	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
+	intel_panel_setup_backlight(connector, INVALID_PIPE);
+
+	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
+		DRM_DEBUG_KMS("no device found\n");
+		goto err;
+	}
+
+	return;
+
+err:
+	drm_encoder_cleanup(&encoder->base);
+	kfree(intel_dsi);
+	kfree(intel_connector);
 }

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-11-29 14:12 UTC #6 lore raw

PATCH v11 5/23 drm/i915/icl: Use the same pll functions for dsi

In reply to Jani Nikula

From: Vandita Kulkarni <[email protected]>

The same pll manager functions can be used to enable dpll for mipi. Hence enabling the IO power and esc clock as part of pre pll enable call.

v2 by Jani:
- fix function parameter indent (Madhav)

Signed-off-by Vandita Kulkarni <[email protected]>

Reviewed-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

drivers/gpu/drm/i915/icl_dsi.c +11 -5

index a40083a7eb6a..9d6cbe35259a 100644
@@ -800,17 +800,22 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 	wait_for_cmds_dispatched_to_panel(encoder);
 }
 
-static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
-				 const struct intel_crtc_state *pipe_config,
-				 const struct drm_connector_state *conn_state)
+static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *pipe_config,
+				     const struct drm_connector_state *conn_state)
 {
-	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-
 	/* step2: enable IO power */
 	gen11_dsi_enable_io_power(encoder);
 
 	/* step3: enable DSI PLL */
 	gen11_dsi_program_esc_clk_div(encoder);
+}
+
+static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *pipe_config,
+				 const struct drm_connector_state *conn_state)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
 	/* step4: enable DSI port and DPHY */
 	gen11_dsi_enable_port_and_phy(encoder, pipe_config);

@@ -1028,6 +1033,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
 			 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
 
+	encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
 	encoder->pre_enable = gen11_dsi_pre_enable;
 	encoder->disable = gen11_dsi_disable;
 	encoder->port = port;

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-11-29 14:12 UTC #7 lore raw

PATCH v11 6/23 drm/i915/icl: Fill DSI ports info

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

This patch fills backlight, CABC and general port info for Gen11 DSI.

Signed-off-by Madhav Chauhan <[email protected]>

Reviewed-by Jani Nikula <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
 1 file changed, 8 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +8 -0

index 9d6cbe35259a..dc3fcc67814b 100644
@@ -1074,6 +1074,14 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 	intel_panel_setup_backlight(connector, INVALID_PIPE);
 
+	if (dev_priv->vbt.dsi.config->dual_link)
+		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
+	else
+		intel_dsi->ports = BIT(port);
+
+	intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
+	intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+
 	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
 		DRM_DEBUG_KMS("no device found\n");
 		goto err;

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
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Jani Nikula

author

2018-11-29 14:12 UTC #8 lore raw

PATCH v11 7/23 drm/i915/icl: Allocate DSI hosts and imlement host transfer

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

Allocate DSI host structure for each DSI port available on gen11 and register them with DSI fwk of DRM. Some of the DSI host operations are also registered as part of this.

Retrieves DSI pkt (from DSI msg) to be sent over DSI link using DRM DSI exported functions. A wrapper function is also added as "DSI host transfer" for sending DSI data/cmd. Add DSI packet payload to command payload queue using credit based mechanism for *long* packets.

v2 by Jani:
- indentation
- Use the new credit available helper
- Use int for free_credits
- Add intel_dsi local variable for better code flow
- Use the new credit available helper
- Use int for free_credits, i, and j

v3 by Jani:
- Squash DSI host allocation and transfer patches together

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 147 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +147 -0

index dc3fcc67814b..43a4d19e36d8 100644
@@ -108,6 +108,90 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
 	}
 }
 
+static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
+			       u32 len)
+{
+	struct intel_dsi *intel_dsi = host->intel_dsi;
+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+	enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+	int free_credits;
+	int i, j;
+
+	for (i = 0; i < len; i += 4) {
+		u32 tmp = 0;
+
+		free_credits = payload_credits_available(dev_priv, dsi_trans);
+		if (free_credits < 1) {
+			DRM_ERROR("Payload credit not available\n");
+			return false;
+		}
+
+		for (j = 0; j < min_t(u32, len - i, 4); j++)
+			tmp |= *data++ << 8 * j;
+
+		I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
+	}
+
+	return true;
+}
+
+static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
+			    struct mipi_dsi_packet pkt, bool enable_lpdt)
+{
+	struct intel_dsi *intel_dsi = host->intel_dsi;
+	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+	enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+	u32 tmp;
+	int free_credits;
+
+	/* check if header credit available */
+	free_credits = header_credits_available(dev_priv, dsi_trans);
+	if (free_credits < 1) {
+		DRM_ERROR("send pkt header failed, not enough hdr credits\n");
+		return -1;
+	}
+
+	tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
+
+	if (pkt.payload)
+		tmp |= PAYLOAD_PRESENT;
+	else
+		tmp &= ~PAYLOAD_PRESENT;
+
+	tmp &= ~VBLANK_FENCE;
+
+	if (enable_lpdt)
+		tmp |= LP_DATA_TRANSFER;
+
+	tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
+	tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
+	tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
+	tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
+	tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
+	I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
+
+	return 0;
+}
+
+static int dsi_send_pkt_payld(struct intel_dsi_host *host,
+			      struct mipi_dsi_packet pkt)
+{
+	/* payload queue can accept *256 bytes*, check limit */
+	if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
+		DRM_ERROR("payload size exceeds max queue limit\n");
+		return -1;
+	}
+
+	/* load data into command payload queue */
+	if (!add_payld_to_queue(host, pkt.payload,
+				pkt.payload_length)) {
+		DRM_ERROR("adding payload to queue failed\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

@@ -1002,6 +1086,58 @@ static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs
 	.atomic_check = intel_digital_connector_atomic_check,
 };
 
+static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
+				 struct mipi_dsi_device *dsi)
+{
+	return 0;
+}
+
+static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
+				 struct mipi_dsi_device *dsi)
+{
+	return 0;
+}
+
+static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
+				       const struct mipi_dsi_msg *msg)
+{
+	struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
+	struct mipi_dsi_packet dsi_pkt;
+	ssize_t ret;
+	bool enable_lpdt = false;
+
+	ret = mipi_dsi_create_packet(&dsi_pkt, msg);
+	if (ret < 0)
+		return ret;
+
+	if (msg->flags & MIPI_DSI_MSG_USE_LPM)
+		enable_lpdt = true;
+
+	/* send packet header */
+	ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
+	if (ret < 0)
+		return ret;
+
+	/* only long packet contains payload */
+	if (mipi_dsi_packet_format_is_long(msg->type)) {
+		ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
+		if (ret < 0)
+			return ret;
+	}
+
+	//TODO: add payload receive code if needed
+
+	ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
+
+	return ret;
+}
+
+static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
+	.attach = gen11_dsi_host_attach,
+	.detach = gen11_dsi_host_detach,
+	.transfer = gen11_dsi_host_transfer,
+};
+
 void icl_dsi_init(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = &dev_priv->drm;

@@ -1074,6 +1210,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
 	intel_panel_setup_backlight(connector, INVALID_PIPE);
 
+
 	if (dev_priv->vbt.dsi.config->dual_link)
 		intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
 	else

@@ -1082,6 +1219,16 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
 	intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
 
+	for_each_dsi_port(port, intel_dsi->ports) {
+		struct intel_dsi_host *host;
+
+		host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
+		if (!host)
+			goto err;
+
+		intel_dsi->dsi_hosts[port] = host;
+	}
+
 	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
 		DRM_DEBUG_KMS("no device found\n");
 		goto err;

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-11-29 14:12 UTC #9 lore raw

PATCH v11 8/23 drm/i915/icl: Add get config functionality for DSI

In reply to Jani Nikula

From: Vandita Kulkarni <[email protected]>

This patch implements the functionality for getting PIPE configuration to which DSI encoder is connected. Use the same method to get port clock like other DDI encoders. Used during the atomic modeset.

v2 by Jani:
- Squash Madhav's and Vandita's get config bits together
- Move cnl_calc_wrpll_link() to intel_drv.h
- Drop extra temp variables
- Use enc_to_intel_dsi() instead of open coding

Co-developed-by Madhav Chauhan <[email protected]>

Signed-off-by Vandita Kulkarni <[email protected]>

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c   | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 3 files changed, 19 insertions(+), 2 deletions(-)

drivers/gpu/drm/i915/icl_dsi.c +15 -0

index 43a4d19e36d8..fba68e1e1bd4 100644
@@ -1060,6 +1060,20 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static void gen11_dsi_get_config(struct intel_encoder *encoder,
+				 struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 pll_id;
+
+	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
+	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
+	pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
+}
+
 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
 	intel_encoder_destroy(encoder);

@@ -1173,6 +1187,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->pre_enable = gen11_dsi_pre_enable;
 	encoder->disable = gen11_dsi_disable;
 	encoder->port = port;
+	encoder->get_config = gen11_dsi_get_config;
 	encoder->type = INTEL_OUTPUT_DSI;
 	encoder->cloneable = 0;
 	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);

drivers/gpu/drm/i915/intel_ddi.c +2 -2

index b5fdf9a15338..64680c3c5d3d 100644
@@ -1364,8 +1364,8 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 	return dco_freq / (p0 * p1 * p2 * 5);
 }
 
-static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
-			       enum intel_dpll_id pll_id)
+int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
+			enum intel_dpll_id pll_id)
 {
 	uint32_t cfgcr0, cfgcr1;
 	uint32_t p0, p1, p2, dco_freq, ref_clock;

drivers/gpu/drm/i915/intel_drv.h +2 -0

index 9018be2171ee..0005b261824e 100644
@@ -1523,6 +1523,8 @@ u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
 				     bool enable);
 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
+int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
+			enum intel_dpll_id pll_id);
 
 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
 				   int color_plane, unsigned int height);

Signature · 6 lines

2.11.0

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-11-29 14:12 UTC #10 lore raw

PATCH v11 9/23 drm/i915/icl: Get HW state for DSI encoder

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

This patch read out the current hw state for DSI and return true if encoder is active.

v2 by Jani:
- Squash connector get hw state hook here
- Squash encode get hw state fix here

v3 by Jani:
- Add encoder->get_power_domains() (Imre)

v4 by Jani:
- Make encoder->get_power_domains() sensible... (Imre)

v5 by Jani:
- Power domains are bit positions, not bits (Stan, Imre)

Cc Imre Deak <[email protected]>

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 59 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +59 -0

index fba68e1e1bd4..12e907b00bb9 100644
@@ -1074,6 +1074,62 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 }
 
+static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder,
+				       struct intel_crtc_state *crtc_state)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u64 domains = 0;
+	enum port port;
+
+	for_each_dsi_port(port, intel_dsi->ports)
+		if (port == PORT_A)
+			domains |= BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO);
+		else
+			domains |= BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO);
+
+	return domains;
+}
+
+static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
+				   enum pipe *pipe)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+	enum transcoder dsi_trans;
+	bool ret = false;
+
+	if (!intel_display_power_get_if_enabled(dev_priv,
+						encoder->power_domain))
+		return false;
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi_trans = dsi_port_to_transcoder(port);
+		tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+		case TRANS_DDI_EDP_INPUT_A_ON:
+			*pipe = PIPE_A;
+			break;
+		case TRANS_DDI_EDP_INPUT_B_ONOFF:
+			*pipe = PIPE_B;
+			break;
+		case TRANS_DDI_EDP_INPUT_C_ONOFF:
+			*pipe = PIPE_C;
+			break;
+		default:
+			DRM_ERROR("Invalid PIPE input\n");
+			goto out;
+		}
+
+		tmp = I915_READ(PIPECONF(dsi_trans));
+		ret = tmp & PIPECONF_ENABLE;
+	}
+out:
+	intel_display_power_put(dev_priv, encoder->power_domain);
+	return ret;
+}
+
 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
 	intel_encoder_destroy(encoder);

@@ -1188,10 +1244,12 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->disable = gen11_dsi_disable;
 	encoder->port = port;
 	encoder->get_config = gen11_dsi_get_config;
+	encoder->get_hw_state = gen11_dsi_get_hw_state;
 	encoder->type = INTEL_OUTPUT_DSI;
 	encoder->cloneable = 0;
 	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
 	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+	encoder->get_power_domains = gen11_dsi_get_power_domains;
 
 	/* register DSI connector with DRM subsystem */
 	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,

@@ -1200,6 +1258,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 	connector->interlace_allowed = false;
 	connector->doublescan_allowed = false;
+	intel_connector->get_hw_state = intel_connector_get_hw_state;
 
 	/* attach connector to encoder */
 	intel_connector_attach_encoder(intel_connector, encoder);

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2.11.0

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Jani Nikula

author

2018-11-29 14:12 UTC #11 lore raw

PATCH v11 10/23 drm/i915/icl: Add DSI encoder compute config hook

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

This patch implements compute config for Gen11 DSI encoder which is required at the time of modeset.

For DSI 8X clock is AFE clock which is 5 times port clock.

v2 by Jani:
- drop the enable nop hook
- fixed_mode is always true
- HAS_GMCH_DISPLAY() is always false

v3 by Jani:
- set encoder->compute_config dropped during rebase

v4 by Jani:
- squash Vandita's port clock patch
- remove todo comment

Co-developed-by Vandita Kulkarni <[email protected]>

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Vandita Kulkarni <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +31 -0

index 12e907b00bb9..f935008ff960 100644
@@ -1074,6 +1074,36 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 }
 
+static bool gen11_dsi_compute_config(struct intel_encoder *encoder,
+				     struct intel_crtc_state *pipe_config,
+				     struct drm_connector_state *conn_state)
+{
+	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+						   base);
+	struct intel_connector *intel_connector = intel_dsi->attached_connector;
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+	const struct drm_display_mode *fixed_mode =
+					intel_connector->panel.fixed_mode;
+	struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+
+	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
+	intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
+
+	adjusted_mode->flags = 0;
+
+	/* Dual link goes to trancoder DSI'0' */
+	if (intel_dsi->ports == BIT(PORT_B))
+		pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
+	else
+		pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+
+	pipe_config->clock_set = true;
+	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
+
+	return true;
+}
+
 static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder,
 				       struct intel_crtc_state *crtc_state)
 {

@@ -1244,6 +1274,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->disable = gen11_dsi_disable;
 	encoder->port = port;
 	encoder->get_config = gen11_dsi_get_config;
+	encoder->compute_config = gen11_dsi_compute_config;
 	encoder->get_hw_state = gen11_dsi_get_hw_state;
 	encoder->type = INTEL_OUTPUT_DSI;
 	encoder->cloneable = 0;

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2.11.0

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Jani Nikula

author

2018-11-29 14:12 UTC #12 lore raw

PATCH v11 11/23 drm/i915/icl: Configure DSI Dual link mode

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

This patch configures DSI video mode dual link by
programming DSS_CTL registers.

v2: Use new bitfield definitions from Anusha's patch
Correct register to be programmed and use max depth buffer value (James)

v3 by Jani:
- checkpatch fixes

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 42 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/icl_dsi.c +41 -1

index f935008ff960..2b576a70222f 100644
@@ -257,6 +257,45 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 	}
 }
 
+static void configure_dual_link_mode(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 dss_ctl1;
+
+	dss_ctl1 = I915_READ(DSS_CTL1);
+	dss_ctl1 |= SPLITTER_ENABLE;
+	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
+	dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
+
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+		const struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+		u32 dss_ctl2;
+		u16 hactive = adjusted_mode->crtc_hdisplay;
+		u16 dl_buffer_depth;
+
+		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
+		dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
+
+		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
+			DRM_ERROR("DL buffer depth exceed max value\n");
+
+		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
+		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+		dss_ctl2 = I915_READ(DSS_CTL2);
+		dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
+		dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+		I915_WRITE(DSS_CTL2, dss_ctl2);
+	} else {
+		/* Interleave */
+		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
+	}
+
+	I915_WRITE(DSS_CTL1, dss_ctl1);
+}
+
 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

@@ -591,7 +630,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
 		}
 
-		//TODO: configure DSS_CTL1
+		/* configure stream splitting */
+		configure_dual_link_mode(encoder, pipe_config);
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {

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Jani Nikula

author

2018-11-29 14:13 UTC #13 lore raw

PATCH v11 12/23 drm/i915/icl: Consider DSI for getting transcoder state

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

For Gen11 DSI, we use similar registers like for eDP to find if DSI encoder is connected or not to a pipe. This patch refactors existing hsw_get_transcoder_state() to handle this.

v2 by Jani:
- Add WARN_ON(dsi && edp) (Ville)

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

drivers/gpu/drm/i915/intel_display.c +24 -7

index 1e4261f524f4..dfce3e675e6f 100644
@@ -9453,6 +9453,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum intel_display_power_domain power_domain;
 	u32 tmp;
+	bool is_dsi = false;
+	bool is_edp = false;
 
 	/*
 	 * The pipe->transcoder mapping is fixed with the exception of the eDP

@@ -9465,26 +9467,41 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
 	 * consistency and less surprising code; it's in always on power).
 	 */
 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
-	if (tmp & TRANS_DDI_FUNC_ENABLE) {
-		enum pipe trans_edp_pipe;
+	if (tmp & TRANS_DDI_FUNC_ENABLE)
+		is_edp = true;
+
+	if (IS_ICELAKE(dev_priv)) {
+		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_DSI_0));
+		if (tmp & TRANS_DDI_FUNC_ENABLE)
+			is_dsi = true;
+	}
+
+	WARN_ON(is_edp && is_dsi);
+
+	if (is_edp || is_dsi) {
+		enum pipe trans_pipe;
 		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 		default:
 			WARN(1, "unknown pipe linked to edp transcoder\n");
 			/* fall through */
 		case TRANS_DDI_EDP_INPUT_A_ONOFF:
 		case TRANS_DDI_EDP_INPUT_A_ON:
-			trans_edp_pipe = PIPE_A;
+			trans_pipe = PIPE_A;
 			break;
 		case TRANS_DDI_EDP_INPUT_B_ONOFF:
-			trans_edp_pipe = PIPE_B;
+			trans_pipe = PIPE_B;
 			break;
 		case TRANS_DDI_EDP_INPUT_C_ONOFF:
-			trans_edp_pipe = PIPE_C;
+			trans_pipe = PIPE_C;
 			break;
 		}
 
-		if (trans_edp_pipe == crtc->pipe)
-			pipe_config->cpu_transcoder = TRANSCODER_EDP;
+		if (trans_pipe == crtc->pipe) {
+			if (is_edp)
+				pipe_config->cpu_transcoder = TRANSCODER_EDP;
+			else if (is_dsi)
+				pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+		}
 	}
 
 	power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);

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Jani Nikula

author

2018-11-29 14:13 UTC #14 lore raw

PATCH v11 13/23 drm/i915/icl: Get pipe timings for DSI

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

Transcoder timings for Gen11 DSI encoder
is available at pipe level unlike in older platform where port specific registers need to be accessed.

v2 by Jani:
- get timings for (!dsi || icl) instead of (dsi && icl).

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/intel_display.c +2 -1

index dfce3e675e6f..ec12c0d8df05 100644
@@ -9636,7 +9636,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	if (!active)
 		goto out;
 
-	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
+	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
+	    IS_ICELAKE(dev_priv)) {
 		haswell_get_ddi_port_state(crtc, pipe_config);
 		intel_get_pipe_timings(crtc, pipe_config);
 	}

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2.11.0

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Jani Nikula

author

2018-11-29 14:13 UTC #15 lore raw

PATCH v11 14/23 drm/i915/icl: Define missing bitfield for shortplug reg

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

This patch define missing bitfield for shortplug ctl ddi register which will be used for ICL DSI GPIO programming.

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 1 file changed, 1 insertion(+)

drivers/gpu/drm/i915/i915_reg.h +1 -0

index 47baf2fe8f71..b5bd84b71814 100644
@@ -7750,6 +7750,7 @@ enum {
 #define   ICP_DDIB_HPD_LONG_DETECT		(2 << 4)
 #define   ICP_DDIB_HPD_SHORT_LONG_DETECT	(3 << 4)
 #define   ICP_DDIA_HPD_ENABLE			(1 << 3)
+#define   ICP_DDIA_HPD_OP_DRIVE_1		(1 << 2)
 #define   ICP_DDIA_HPD_STATUS_MASK		(3 << 0)
 #define   ICP_DDIA_HPD_NO_DETECT		(0 << 0)
 #define   ICP_DDIA_HPD_SHORT_DETECT		(1 << 0)

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Jani Nikula

author

2018-11-29 14:13 UTC #16 lore raw

PATCH v11 15/23 drm/i915/icl: Define Panel power ctrl register

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

There are two panel power sequencers. Each register has two addressable instances. This patch defines both the instances of Panel power control register

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/gpu/drm/i915/i915_reg.h +11 -0

index b5bd84b71814..bbbbc20f292c 100644
@@ -4617,6 +4617,17 @@ enum {
 #define _PP_STATUS			0x61200
 #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
 #define   PP_ON				(1 << 31)
+
+#define _PP_CONTROL_1			0xc7204
+#define _PP_CONTROL_2			0xc7304
+#define ICP_PP_CONTROL(x)		_MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+					      _PP_CONTROL_2)
+#define  POWER_CYCLE_DELAY_MASK	(0x1f << 4)
+#define  POWER_CYCLE_DELAY_SHIFT	4
+#define  VDD_OVERRIDE_FORCE		(1 << 3)
+#define  BACKLIGHT_ENABLE		(1 << 2)
+#define  PWR_DOWN_ON_RESET		(1 << 1)
+#define  PWR_STATE_TARGET		(1 << 0)
 /*
  * Indicates that all dependencies of the panel are on:
  *

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Jani Nikula

author

2018-11-29 14:13 UTC #17 lore raw

PATCH v11 16/23 drm/i915/icl: Define display GPIO pins for DSI

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

Display Pins are the only GPIOs that need to be used by driver for DSI panels. So driver should now have its own implementation to toggle these pins based on GPIO info received from VBT sequences.

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

drivers/gpu/drm/i915/intel_dsi_vbt.c +12 -0

index a72de81f4832..b41ca6436401 100644
@@ -103,6 +103,18 @@ static struct gpio_map vlv_gpio_table[] = {
 #define CHV_GPIO_PAD_CFG1(f, i)		(0x4400 + (f) * 0x400 + (i) * 8 + 4)
 #define  CHV_GPIO_CFGLOCK		(1 << 31)
 
+/* ICL DSI Display GPIO Pins */
+#define  ICL_GPIO_DDSP_HPD_A		0
+#define  ICL_GPIO_L_VDDEN_1		1
+#define  ICL_GPIO_L_BKLTEN_1		2
+#define  ICL_GPIO_DDPA_CTRLCLK_1	3
+#define  ICL_GPIO_DDPA_CTRLDATA_1	4
+#define  ICL_GPIO_DDSP_HPD_B		5
+#define  ICL_GPIO_L_VDDEN_2		6
+#define  ICL_GPIO_L_BKLTEN_2		7
+#define  ICL_GPIO_DDPA_CTRLCLK_2	8
+#define  ICL_GPIO_DDPA_CTRLDATA_2	9
+
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 {
 	return port ? PORT_C : PORT_A;

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Jani Nikula

author

2018-11-29 14:13 UTC #18 lore raw

PATCH v11 17/23 drm/i915/icl: add dummy DSI GPIO element execution function

In reply to Jani Nikula

Add dummy debug logging GPIO element execution function for ICL.

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/intel_dsi_vbt.c +9 -1

index b41ca6436401..a1a8b3790e61 100644
@@ -336,6 +336,12 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
 	gpiod_set_value(gpio_desc, value);
 }
 
+static void icl_exec_gpio(struct drm_i915_private *dev_priv,
+			  u8 gpio_source, u8 gpio_index, bool value)
+{
+	DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;

@@ -359,7 +365,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	/* pull up/down */
 	value = *data++ & 1;
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+	else if (IS_VALLEYVIEW(dev_priv))
 		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
 	else if (IS_CHERRYVIEW(dev_priv))
 		chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);

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2.11.0

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Jani Nikula

author

2018-11-29 14:13 UTC #20 lore raw

PATCH v11 18/23 drm/i915/icl: Gate clocks for DSI

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

As per BSPEC, depending on the DSI transcoder being used, DDI clock for the associated port should be gated. This patch does the same.

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Vandita Kulkarni <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +20 -0

index 2b576a70222f..e42a99fda191 100644
@@ -536,6 +536,23 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	}
 }
 
+static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	mutex_lock(&dev_priv->dpll_lock);
+	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+	}
+
+	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
+	mutex_unlock(&dev_priv->dpll_lock);
+}
+
 static void
 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *pipe_config)

@@ -883,6 +900,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 
 	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
 	gen11_dsi_configure_transcoder(encoder, pipe_config);
+
+	/* Step 4l: Gate DDI clocks */
+	gen11_dsi_gate_clocks(encoder);
 }
 
 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)

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2.11.0

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Jani Nikula

author

2018-11-29 14:13 UTC #21 lore raw

PATCH v11 19/23 drm/i915/icl: Ungate DSI clocks

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

Ungate the clocks on the selected port.

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Vandita Kulkarni <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +19 -0

index e42a99fda191..e3aa9d3d2291 100644
@@ -553,6 +553,23 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpll_lock);
 }
 
+static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u32 tmp;
+	enum port port;
+
+	mutex_lock(&dev_priv->dpll_lock);
+	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+	}
+
+	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
+	mutex_unlock(&dev_priv->dpll_lock);
+}
+
 static void
 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *pipe_config)

@@ -1061,6 +1078,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
 	u32 tmp;
 	enum port port;
 
+	gen11_dsi_ungate_clocks(encoder);
 	for_each_dsi_port(port, intel_dsi->ports) {
 		tmp = I915_READ(DDI_BUF_CTL(port));
 		tmp &= ~DDI_BUF_CTL_ENABLE;

@@ -1072,6 +1090,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
 			DRM_ERROR("DDI port:%c buffer not idle\n",
 				  port_name(port));
 	}
+	gen11_dsi_ungate_clocks(encoder);
 }
 
 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)

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Jani Nikula

author

2018-11-29 14:13 UTC #22 lore raw

PATCH v11 20/23 drm/i915/icl: add pll mapping for DSI

In reply to Jani Nikula

Add encoder specific pll mapping for DSI. The differences with the DDI version are big enough to warrant a separate function.

Cc Madhav Chauhan <[email protected]>

Cc Vandita Kulkarni <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +24 -0

index e3aa9d3d2291..1907640a2e6a 100644
@@ -570,6 +570,27 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpll_lock);
 }
 
+static void gen11_dsi_map_pll(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port;
+	u32 val;
+
+	mutex_lock(&dev_priv->dpll_lock);
+
+	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+	}
+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+	mutex_unlock(&dev_priv->dpll_lock);
+}
+
 static void
 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *pipe_config)

@@ -978,6 +999,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
+	/* step3b */
+	gen11_dsi_map_pll(encoder, pipe_config);
+
 	/* step4: enable DSI port and DPHY */
 	gen11_dsi_enable_port_and_phy(encoder, pipe_config);

Signature · 6 lines

2.11.0

_______________________________________________
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Jani Nikula

author

2018-11-29 14:13 UTC #25 lore raw

PATCH v11 21/23 HACK: drm/i915/icl: Add changes to program DSI panel GPIOs

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

For ICELAKE DSI, Display Pins are the only GPIOs that need to be programmed. So DSI driver should have its own implementation to toggle these pins based on GPIO info coming from VBT sequences instead of using platform specific GPIO driver.

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 38 +++++++++++++++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/intel_dsi_vbt.c +37 -1

index a1a8b3790e61..e6686dbdf462 100644
@@ -339,7 +339,43 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
 static void icl_exec_gpio(struct drm_i915_private *dev_priv,
 			  u8 gpio_source, u8 gpio_index, bool value)
 {
-	DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
+	u32 val;
+
+	switch (gpio_index) {
+	case ICL_GPIO_DDSP_HPD_A:
+		val = I915_READ(SHOTPLUG_CTL_DDI);
+		val &= ~ICP_DDIA_HPD_ENABLE;
+		I915_WRITE(SHOTPLUG_CTL_DDI, val);
+		val = I915_READ(SHOTPLUG_CTL_DDI);
+
+		if (value)
+			val |= ICP_DDIA_HPD_OP_DRIVE_1;
+		else
+			val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
+
+		I915_WRITE(SHOTPLUG_CTL_DDI, val);
+		break;
+	case ICL_GPIO_L_VDDEN_1:
+		val = I915_READ(ICP_PP_CONTROL(1));
+		if (value)
+			val |= PWR_STATE_TARGET;
+		else
+			val &= ~PWR_STATE_TARGET;
+		I915_WRITE(ICP_PP_CONTROL(1), val);
+		break;
+	case ICL_GPIO_L_BKLTEN_1:
+		val = I915_READ(ICP_PP_CONTROL(1));
+		if (value)
+			val |= BACKLIGHT_ENABLE;
+		else
+			val &= ~BACKLIGHT_ENABLE;
+		I915_WRITE(ICP_PP_CONTROL(1), val);
+		break;
+	default:
+		/* TODO: Add support for remaining GPIOs */
+		DRM_ERROR("Invalid GPIO no from VBT\n");
+		break;
+	}
 }
 
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)

Signature · 6 lines

2.11.0

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Jani Nikula

author

2018-11-29 14:13 UTC #26 lore raw

PATCH v11 22/23 HACK: drm/i915/icl: Configure backlight functions for DSI

In reply to Jani Nikula

From: Madhav Chauhan <[email protected]>

Gen11 DSI doesn't use DCS commands based functionality for enabling/disabling backlight but uses PWM based functions similar to eDP.

Note by Jani: This should be decided by VBT, not hard coded. DCS brightness control is still a thing.

Signed-off-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_panel.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/intel_panel.c +2 -1

index e6cd7b55c018..b6df63aa11e3 100644
@@ -1835,7 +1835,8 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
 	    intel_dp_aux_init_backlight_funcs(connector) == 0)
 		return;
 
-	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
+	if (IS_GEN9_LP(dev_priv) &&
+	    connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
 	    intel_dsi_dcs_init_backlight_funcs(connector) == 0)
 		return;

Signature · 6 lines

2.11.0

_______________________________________________
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Jani Nikula

author

2018-11-29 14:13 UTC #27 lore raw

PATCH v11 23/23 HACK: drm/i915/bios: ignore VBT not overflowing the mailbox

In reply to Jani Nikula

Some machines seem to have a broken opregion where the VBT overflows the mailbox. Ignore this until properly fixed.

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/intel_bios.c | 1 -
 1 file changed, 1 deletion(-)

drivers/gpu/drm/i915/intel_bios.c +0 -1

index 0694aa8bb9bc..39e502ea557c 100644
@@ -1706,7 +1706,6 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size)
 	bdb = get_bdb_header(vbt);
 	if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
 		DRM_DEBUG_DRIVER("BDB incomplete\n");
-		return false;
 	}
 
 	return vbt;

Signature · 6 lines

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Patchwork

2018-11-29 14:50 UTC #29 lore raw

✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling (rev6)

In reply to Jani Nikula

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev6)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a65617b53ade drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
37ef11ea7aa7 drm/i915/icl: Sanitize DDI port clock gating for DSI ports
0f5edfc63f35 drm/i915/icl: Calculate DPLL params for DSI
-:22: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#22: 
Co-developed-by: Vandita Kulkarni <[email protected]>

total: 0 errors, 1 warnings, 0 checks, 22 lines checked 6dc7fe9047df drm/i915/icl: Allocate DSI encoder/connector -:137: CHECK:CAMELCASE: Avoid CamelCase: <SubPixelHorizontalRGB> #137: FILE: drivers/gpu/drm/i915/icl_dsi.c:1043:
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB;

total: 0 errors, 0 warnings, 1 checks, 145 lines checked 1556283cacab drm/i915/icl: Use the same pll functions for dsi 4dac6888a145 drm/i915/icl: Fill DSI ports info
7fad6a3ad9da drm/i915/icl: Allocate DSI hosts and imlement host transfer -:187: CHECK:LINE_SPACING: Please don't use multiple blank lines #187: FILE: drivers/gpu/drm/i915/icl_dsi.c:1213:

total: 0 errors, 0 warnings, 1 checks, 171 lines checked 82bf01085a14 drm/i915/icl: Add get config functionality for DSI -:16: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#16:

Co-developed-by Madhav Chauhan <[email protected]>

total: 0 errors, 1 warnings, 0 checks, 45 lines checked aa8fb2448b1f drm/i915/icl: Get HW state for DSI encoder 63e5965d02c1 drm/i915/icl: Add DSI encoder compute config hook -:23: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#23:

Co-developed-by Vandita Kulkarni <[email protected]>

total: 0 errors, 1 warnings, 0 checks, 43 lines checked 7db8401305da drm/i915/icl: Configure DSI Dual link mode 1bd7b569b632 drm/i915/icl: Consider DSI for getting transcoder state b3273c98d705 drm/i915/icl: Get pipe timings for DSI f80c2ca9d8c4 drm/i915/icl: Define missing bitfield for shortplug reg 3c816c13f322 drm/i915/icl: Define Panel power ctrl register 570c6994a5d9 drm/i915/icl: Define display GPIO pins for DSI 5a1f35547955 drm/i915/icl: add dummy DSI GPIO element execution function 583b019c2b85 drm/i915/icl: Gate clocks for DSI
9ae624b30832 drm/i915/icl: Ungate DSI clocks
9ec5126e3d2a drm/i915/icl: add pll mapping for DSI e11d2a74b0e8 HACK: drm/i915/icl: Add changes to program DSI panel GPIOs baf028ec4d0d HACK: drm/i915/icl: Configure backlight functions for DSI d5ba18915e1b HACK: drm/i915/bios: ignore VBT not overflowing the mailbox

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Patchwork

2018-11-29 14:57 UTC #30 lore raw

✗ Fi.CI.SPARSE: warning for drm/i915/icl: dsi enabling (rev6)

In reply to Jani Nikula

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev6)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
Okay!

Commit: drm/i915/icl: Sanitize DDI port clock gating for DSI ports Okay!

Commit: drm/i915/icl: Calculate DPLL params for DSI Okay!

Commit: drm/i915/icl: Allocate DSI encoder/connector +./include/linux/slab.h:332:43: warning: dubious: x & !y

Commit: drm/i915/icl: Use the same pll functions for dsi Okay!

Commit: drm/i915/icl: Fill DSI ports info
Okay!

Commit: drm/i915/icl: Allocate DSI hosts and imlement host transfer +drivers/gpu/drm/i915/icl_dsi.c:129:33: warning: expression using sizeof(void)

Commit: drm/i915/icl: Add get config functionality for DSI Okay!

Commit: drm/i915/icl: Get HW state for DSI encoder Okay!

Commit: drm/i915/icl: Add DSI encoder compute config hook Okay!

Commit: drm/i915/icl: Configure DSI Dual link mode Okay!

Commit: drm/i915/icl: Consider DSI for getting transcoder state Okay!

Commit: drm/i915/icl: Get pipe timings for DSI
Okay!

Commit: drm/i915/icl: Define missing bitfield for shortplug reg Okay!

Commit: drm/i915/icl: Define Panel power ctrl register Okay!

Commit: drm/i915/icl: Define display GPIO pins for DSI Okay!

Commit: drm/i915/icl: add dummy DSI GPIO element execution function Okay!

Commit: drm/i915/icl: Gate clocks for DSI
Okay!

Commit: drm/i915/icl: Ungate DSI clocks
Okay!

Commit: drm/i915/icl: add pll mapping for DSI
Okay!

Commit: HACK: drm/i915/icl: Add changes to program DSI panel GPIOs Okay!

Commit: HACK: drm/i915/icl: Configure backlight functions for DSI Okay!

Commit: HACK: drm/i915/bios: ignore VBT not overflowing the mailbox Okay!

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Patchwork

2018-11-29 15:16 UTC #31 lore raw

✓ Fi.CI.BAT: success for drm/i915/icl: dsi enabling (rev6)

In reply to Jani Nikula

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev6)
URL : https://patchwork.freedesktop.org/series/51011/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5222 -> Patchwork_10956
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/6/mbox/

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_10956:

### IGT changes ###

#### Possible regressions ####

* igt@kms_busy@basic-flip-b:
- {fi-icl-u3}: PASS -> DMESG-WARN

* {igt@runner@aborted}:
- {fi-icl-u3}: NOTRUN -> FAIL

Known issues
------------

Here are the changes found in Patchwork_10956 that come from known issues:

### IGT changes ###

#### Issues hit ####

* {igt@runner@aborted}:
- {fi-icl-y}: NOTRUN -> FAIL [fdo#108070]

#### Possible fixes ####

* igt@gem_mmap_gtt@basic:
- fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133

Participating hosts (49 -> 43)
------------------------------

Additional (1): fi-icl-y
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510

Build changes
-------------

* Linux: CI_DRM_5222 -> Patchwork_10956

CI_DRM_5222: a6f85043a0ca86eb0072e69bf92b77f7d9d6d5d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10956: d5ba18915e1b1b609b8c361634dbec396627126d @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

d5ba18915e1b HACK: drm/i915/bios: ignore VBT not overflowing the mailbox baf028ec4d0d HACK: drm/i915/icl: Configure backlight functions for DSI e11d2a74b0e8 HACK: drm/i915/icl: Add changes to program DSI panel GPIOs 9ec5126e3d2a drm/i915/icl: add pll mapping for DSI
9ae624b30832 drm/i915/icl: Ungate DSI clocks
583b019c2b85 drm/i915/icl: Gate clocks for DSI
5a1f35547955 drm/i915/icl: add dummy DSI GPIO element execution function 570c6994a5d9 drm/i915/icl: Define display GPIO pins for DSI 3c816c13f322 drm/i915/icl: Define Panel power ctrl register f80c2ca9d8c4 drm/i915/icl: Define missing bitfield for shortplug reg b3273c98d705 drm/i915/icl: Get pipe timings for DSI
1bd7b569b632 drm/i915/icl: Consider DSI for getting transcoder state 7db8401305da drm/i915/icl: Configure DSI Dual link mode
63e5965d02c1 drm/i915/icl: Add DSI encoder compute config hook aa8fb2448b1f drm/i915/icl: Get HW state for DSI encoder
82bf01085a14 drm/i915/icl: Add get config functionality for DSI 7fad6a3ad9da drm/i915/icl: Allocate DSI hosts and imlement host transfer 4dac6888a145 drm/i915/icl: Fill DSI ports info
1556283cacab drm/i915/icl: Use the same pll functions for dsi 6dc7fe9047df drm/i915/icl: Allocate DSI encoder/connector 0f5edfc63f35 drm/i915/icl: Calculate DPLL params for DSI
37ef11ea7aa7 drm/i915/icl: Sanitize DDI port clock gating for DSI ports a65617b53ade drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10956/
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Patchwork

2018-11-30 03:05 UTC #32 lore raw

✓ Fi.CI.IGT: success for drm/i915/icl: dsi enabling (rev6)

In reply to Jani Nikula

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev6)
URL : https://patchwork.freedesktop.org/series/51011/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5222_full -> Patchwork_10956_full
====================================================

Summary
-------

**WARNING**

Minor unknown changes coming with Patchwork_10956_full need to be verified manually.

If you think the reported changes have nothing to do with the changes introduced in Patchwork_10956_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI.

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_10956_full:

### IGT changes ###

#### Possible regressions ####

* igt@kms_vblank@pipe-c-wait-forked:
- {shard-iclb}: PASS -> DMESG-WARN +30

* {igt@runner@aborted}:
- {shard-iclb}: NOTRUN -> ( 33 FAIL ) [fdo#105702]

#### Warnings ####

* igt@kms_ccs@pipe-b-crc-primary-rotation-180:
- {shard-iclb}: FAIL [fdo#107725] -> DMESG-FAIL

* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP -> PASS

Known issues
------------

Here are the changes found in Patchwork_10956_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl: NOTRUN -> FAIL [fdo#103158]

* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108039]

* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2

* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-skl: PASS -> DMESG-WARN [fdo#107956]

* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-apl: PASS -> DMESG-WARN [fdo#107956]

* igt@kms_color@pipe-a-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]

* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +2

* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107882]

* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: PASS -> FAIL [fdo#100368]

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +1

* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682]

* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]

* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1

* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +4

* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1

* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-skl: NOTRUN -> FAIL [fdo#103166] / [fdo#107815]

* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]

* igt@perf@polling:
- shard-hsw: PASS -> FAIL [fdo#102252]

* igt@pm_backlight@fade_with_suspend:
- shard-skl: NOTRUN -> FAIL [fdo#107847]

* igt@pm_rpm@gem-evict-pwrite:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]

* igt@syncobj_wait@multi-wait-for-submit-unsubmitted-signaled:
- shard-snb: PASS -> INCOMPLETE [fdo#105411] / [fdo#107469]

#### Possible fixes ####

* igt@drm_import_export@import-close-race-flink:
- shard-skl: TIMEOUT [fdo#108667] -> PASS

* igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-skl: FAIL [fdo#107725] -> PASS

* igt@kms_color@pipe-b-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS

* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS +1

* igt@kms_cursor_crc@cursor-128x42-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1

* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-glk: FAIL [fdo#103232] -> PASS

* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-xtiled:
- shard-skl: FAIL [fdo#107791] -> PASS

* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-apl: FAIL [fdo#103167] -> PASS +2

* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-glk: FAIL [fdo#103167] -> PASS

* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS

* igt@pm_rpm@legacy-planes:
- shard-skl: INCOMPLETE [fdo#105959] / [fdo#107807] -> PASS

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (7 -> 7)
------------------------------

No changes in participating hosts

Build changes
-------------

* Linux: CI_DRM_5222 -> Patchwork_10956

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10956/shards.html
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Madhav Chauhan

Reviewed-by on v11 1/23

2018-11-30 13:39 UTC #2 lore raw

Re: [PATCH v11 01/23] drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks

In reply to Jani Nikula

Quoted 8 lines · Jani Nikula

Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions a bit by moving the pll to port mapping and unmapping functions to the ddi encoder hooks. This allows removal of a bunch of boilerplate code from the functions.
Additionally, the ICL DSI encoder needs to do the clock gating and ungating slightly differently, and this allows its own handling in a clean fashion.

Looks good to me,

Reviewed-by Madhav Chauhan <[email protected]>

Regards,
Madhav

Quoted 171 lines

Cc Madhav Chauhan <[email protected]>

Cc Paulo Zanoni <[email protected]>

Cc Ville Syrjälä <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
  drivers/gpu/drm/i915/intel_ddi.c     | 84 +++++++++++++++---------------------
  drivers/gpu/drm/i915/intel_display.c |  6 ---
  drivers/gpu/drm/i915/intel_drv.h     |  6 ---
  3 files changed, 34 insertions(+), 62 deletions(-)

drivers/gpu/drm/i915/intel_ddi.c +34 ~~-50~~

index ad11540ac436..7bad6c857b81 100644
@@ -2785,69 +2785,45 @@ uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
  	return 0;
  }
 
-void icl_map_plls_to_ports(struct drm_crtc *crtc,
-			   struct intel_crtc_state *crtc_state,
-			   struct drm_atomic_state *old_state)
+static void icl_map_plls_to_ports(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *crtc_state)
  {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	struct drm_connector_state *conn_state;
-	struct drm_connector *conn;
-	int i;
-
-	for_each_new_connector_in_state(old_state, conn, conn_state, i) {
-		struct intel_encoder *encoder =
-			to_intel_encoder(conn_state->best_encoder);
-		enum port port;
-		uint32_t val;
-
-		if (conn_state->crtc != crtc)
-			continue;
-
-		port = encoder->port;
-		mutex_lock(&dev_priv->dpll_lock);
+	enum port port = encoder->port;
+	u32 val;
 
-		val = I915_READ(DPCLKA_CFGCR0_ICL);
-		WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+	mutex_lock(&dev_priv->dpll_lock);
 
-		if (intel_port_is_combophy(dev_priv, port)) {
-			val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-			val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
-			I915_WRITE(DPCLKA_CFGCR0_ICL, val);
-			POSTING_READ(DPCLKA_CFGCR0_ICL);
-		}
+	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
 
-		val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	if (intel_port_is_combophy(dev_priv, port)) {
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
  		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
-
-		mutex_unlock(&dev_priv->dpll_lock);
+		POSTING_READ(DPCLKA_CFGCR0_ICL);
  	}
+
+	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+	mutex_unlock(&dev_priv->dpll_lock);
  }
 
-void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
-			     struct intel_crtc_state *crtc_state,
-			     struct drm_atomic_state *old_state)
+static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
  {
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	struct drm_connector_state *old_conn_state;
-	struct drm_connector *conn;
-	int i;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+	u32 val;
 
-	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
-		struct intel_encoder *encoder =
-			to_intel_encoder(old_conn_state->best_encoder);
-		enum port port;
+	mutex_lock(&dev_priv->dpll_lock);
 
-		if (old_conn_state->crtc != crtc)
-			continue;
+	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
-		port = encoder->port;
-		mutex_lock(&dev_priv->dpll_lock);
-		I915_WRITE(DPCLKA_CFGCR0_ICL,
-			   I915_READ(DPCLKA_CFGCR0_ICL) |
-			   icl_dpclka_cfgcr0_clk_off(dev_priv, port));
-		mutex_unlock(&dev_priv->dpll_lock);
-	}
+	mutex_unlock(&dev_priv->dpll_lock);
  }
 
  void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)

@@ -3208,6 +3184,9 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
 
  	WARN_ON(crtc_state->has_pch_encoder);
 
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_map_plls_to_ports(encoder, crtc_state);
+
  	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 
  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

@@ -3306,6 +3285,8 @@ static void intel_ddi_post_disable(struct intel_encoder *encoder,
  				   const struct intel_crtc_state *old_crtc_state,
  				   const struct drm_connector_state *old_conn_state)
  {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
  	/*
  	 * When called from DP MST code:
  	 * - old_conn_state will be NULL

@@ -3325,6 +3306,9 @@ static void intel_ddi_post_disable(struct intel_encoder *encoder,
  	else
  		intel_ddi_post_disable_dp(encoder,
  					  old_crtc_state, old_conn_state);
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_unmap_plls_to_ports(encoder);
  }
 
  void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_display.c +0 -6

index d07fa4456150..559db98b5a4a 100644
@@ -5704,9 +5704,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
  	if (pipe_config->shared_dpll)
  		intel_enable_shared_dpll(pipe_config);
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		icl_map_plls_to_ports(crtc, pipe_config, old_state);
-
  	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
  	if (intel_crtc_has_dp_encoder(pipe_config))

@@ -5908,9 +5905,6 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 
  	intel_encoders_post_disable(crtc, old_crtc_state, old_state);
 
-	if (INTEL_GEN(dev_priv) >= 11)
-		icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state);
-
  	intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
  }

drivers/gpu/drm/i915/intel_drv.h +0 -0

index 40edb21087a7..9018be2171ee 100644
@@ -1522,12 +1522,6 @@ u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
  				 u8 voltage_swing);
  int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,

drivers/gpu/drm/i915/intel_drv.h u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, · line 1527

Quoted 10 lines

drivers/gpu/drm/i915/intel_drv.h +0 -6

  				     bool enable);
-void icl_map_plls_to_ports(struct drm_crtc *crtc,
-			   struct intel_crtc_state *crtc_state,
-			   struct drm_atomic_state *old_state);
-void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
-			     struct intel_crtc_state *crtc_state,
-			     struct drm_atomic_state *old_state);
  void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
 
  unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,

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Madhav Chauhan

Reviewed-by on v11 17/23

2018-11-30 13:44 UTC #19 lore raw

Re: [PATCH v11 17/23] drm/i915/icl: add dummy DSI GPIO element execution function

In reply to Jani Nikula

Quoted 1 line · Jani Nikula

Add dummy debug logging GPIO element execution function for ICL.

Looks fine to me.

Reviewed-by Madhav Chauhan <[email protected]>

Regards,
Madhav

Quoted 24 lines

Signed-off-by Jani Nikula <[email protected]>

---
  drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +++++++++-
  1 file changed, 9 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/intel_dsi_vbt.c +6 -0

index b41ca6436401..a1a8b3790e61 100644
@@ -336,6 +336,12 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
  	gpiod_set_value(gpio_desc, value);
  }
 
+static void icl_exec_gpio(struct drm_i915_private *dev_priv,
+			  u8 gpio_source, u8 gpio_index, bool value)
+{
+	DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
+}
+
  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
  {
  	struct drm_device *dev = intel_dsi->base.base.dev;

drivers/gpu/drm/i915/intel_dsi_vbt.c static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) · line 373

Quoted 10 lines

drivers/gpu/drm/i915/intel_dsi_vbt.c +3 -1

@@ -359,7 +365,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
  	/* pull up/down */
  	value = *data++ & 1;
 
-	if (IS_VALLEYVIEW(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+	else if (IS_VALLEYVIEW(dev_priv))
  		vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
  	else if (IS_CHERRYVIEW(dev_priv))
  		chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);

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Madhav Chauhan

Reviewed-by on v11 20/23

2018-11-30 14:08 UTC #23 lore raw

Re: [PATCH v11 20/23] drm/i915/icl: add pll mapping for DSI

In reply to Jani Nikula

Quoted 25 lines · Jani Nikula

Add encoder specific pll mapping for DSI. The differences with the DDI version are big enough to warrant a separate function.

Cc Madhav Chauhan <[email protected]>

Cc Vandita Kulkarni <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
  drivers/gpu/drm/i915/icl_dsi.c | 24 ++++++++++++++++++++++++
  1 file changed, 24 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +7 -0

index e3aa9d3d2291..1907640a2e6a 100644
@@ -570,6 +570,27 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
  	mutex_unlock(&dev_priv->dpll_lock);
  }
 
+static void gen11_dsi_map_pll(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port;

drivers/gpu/drm/i915/icl_dsi.c static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) · line 589

Quoted 10 lines

drivers/gpu/drm/i915/icl_dsi.c +10 -0

+	u32 val;
+
+	mutex_lock(&dev_priv->dpll_lock);
+
+	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+	}
+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);

We need to read back DPCLKA_CFGCR0_ICL to ensure write completed before next step as per BSPEC. With this fix,

Reviewed-by Madhav Chauhan <[email protected]>

Regards,
Madhav

drivers/gpu/drm/i915/icl_dsi.c static void gen11_dsi_pre_enable(struct intel_encoder *encoder, · line 1003

Quoted 13 lines

drivers/gpu/drm/i915/icl_dsi.c +6 -0

+
+	mutex_unlock(&dev_priv->dpll_lock);
+}
+
  static void
  gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
  			       const struct intel_crtc_state *pipe_config)

@@ -978,6 +999,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
  {
  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
+	/* step3b */
+	gen11_dsi_map_pll(encoder, pipe_config);

/* step4: enable DSI port and DPHY */

drivers/gpu/drm/i915/icl_dsi.c static void gen11_dsi_pre_enable(struct intel_encoder *encoder, · line 1007

Quoted 2 lines

drivers/gpu/drm/i915/icl_dsi.c +0 -0
  	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
 

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Madhav Chauhan

Acked-by on v11 23/23

2018-11-30 14:10 UTC #28 lore raw

Re: [PATCH v11 23/23] HACK: drm/i915/bios: ignore VBT not overflowing the mailbox

In reply to Jani Nikula

Quoted 2 lines · Jani Nikula

Some machines seem to have a broken opregion where the VBT overflows the mailbox. Ignore this until properly fixed.

Right, otherwise DSI modeset doesn't progress further.

Acked-by Madhav Chauhan <[email protected]>

Regards,
Madhav

Quoted 11 lines

Signed-off-by Jani Nikula <[email protected]>
---
  drivers/gpu/drm/i915/intel_bios.c | 1 -
  1 file changed, 1 deletion(-)
drivers/gpu/drm/i915/intel_bios.c +0 -0
index 0694aa8bb9bc..39e502ea557c 100644

drivers/gpu/drm/i915/intel_bios.c bool intel_bios_is_valid_vbt(const void *buf, size_t size) · line 1711

Quoted 7 lines

drivers/gpu/drm/i915/intel_bios.c +0 -1

@@ -1706,7 +1706,6 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size)
  	bdb = get_bdb_header(vbt);
  	if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
  		DRM_DEBUG_DRIVER("BDB incomplete\n");
-		return false;
  	}
 
  	return vbt;

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Jani Nikula

author

2018-12-03 09:43 UTC #24 lore raw

PATCH v11 20/23 drm/i915/icl: add pll mapping for DSI

In reply to Jani Nikula

Add encoder specific pll mapping for DSI. The differences with the DDI version are big enough to warrant a separate function.

v2: add posting read (Madhav)

Cc Madhav Chauhan <[email protected]>

Cc Vandita Kulkarni <[email protected]>

Reviewed-by Madhav Chauhan <[email protected]>

Signed-off-by Jani Nikula <[email protected]>

---
 drivers/gpu/drm/i915/icl_dsi.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

drivers/gpu/drm/i915/icl_dsi.c +25 -0

index e3aa9d3d2291..4dd793b78996 100644
@@ -570,6 +570,28 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpll_lock);
 }
 
+static void gen11_dsi_map_pll(struct intel_encoder *encoder,
+			      const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum port port;
+	u32 val;
+
+	mutex_lock(&dev_priv->dpll_lock);
+
+	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	for_each_dsi_port(port, intel_dsi->ports) {
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+	}
+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+	POSTING_READ(DPCLKA_CFGCR0_ICL);
+
+	mutex_unlock(&dev_priv->dpll_lock);
+}
+
 static void
 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *pipe_config)

@@ -978,6 +1000,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
+	/* step3b */
+	gen11_dsi_map_pll(encoder, pipe_config);
+
 	/* step4: enable DSI port and DPHY */
 	gen11_dsi_enable_port_and_phy(encoder, pipe_config);

Signature · 6 lines

2.11.0

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Patchwork

2018-12-03 11:16 UTC #33 lore raw

✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling (rev7)

In reply to Jani Nikula

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
96d02a19d096 drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
a3c740ce09ea drm/i915/icl: Sanitize DDI port clock gating for DSI ports
87b45256f131 drm/i915/icl: Calculate DPLL params for DSI
-:22: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#22: 
Co-developed-by: Vandita Kulkarni <[email protected]>

total: 0 errors, 1 warnings, 0 checks, 22 lines checked fbb01f92a65c drm/i915/icl: Allocate DSI encoder/connector -:137: CHECK:CAMELCASE: Avoid CamelCase: <SubPixelHorizontalRGB> #137: FILE: drivers/gpu/drm/i915/icl_dsi.c:1043:
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB;

total: 0 errors, 0 warnings, 1 checks, 145 lines checked 028d3c2eb0e4 drm/i915/icl: Use the same pll functions for dsi 50773017b12a drm/i915/icl: Fill DSI ports info
62513a8970ed drm/i915/icl: Allocate DSI hosts and imlement host transfer -:187: CHECK:LINE_SPACING: Please don't use multiple blank lines #187: FILE: drivers/gpu/drm/i915/icl_dsi.c:1213:

total: 0 errors, 0 warnings, 1 checks, 171 lines checked 33521ef27138 drm/i915/icl: Add get config functionality for DSI -:16: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#16:

Co-developed-by Madhav Chauhan <[email protected]>

total: 0 errors, 1 warnings, 0 checks, 45 lines checked 3f22982ec59a drm/i915/icl: Get HW state for DSI encoder 7d6ef2834195 drm/i915/icl: Add DSI encoder compute config hook -:23: WARNING:BAD_SIGN_OFF: Non-standard signature: Co-developed-by:
#23:

Co-developed-by Vandita Kulkarni <[email protected]>

total: 0 errors, 1 warnings, 0 checks, 43 lines checked 532aa53e71c8 drm/i915/icl: Configure DSI Dual link mode 978f80d3edf2 drm/i915/icl: Consider DSI for getting transcoder state 8463e98e1a20 drm/i915/icl: Get pipe timings for DSI 24945f1aac4a drm/i915/icl: Define missing bitfield for shortplug reg 1027ae61ad4a drm/i915/icl: Define Panel power ctrl register 70438b447157 drm/i915/icl: Define display GPIO pins for DSI b2fffaad2d0f drm/i915/icl: add dummy DSI GPIO element execution function c3483c42f102 drm/i915/icl: Gate clocks for DSI
8f5d87749941 drm/i915/icl: Ungate DSI clocks
079bbc7aeea6 drm/i915/icl: add pll mapping for DSI 061f3e41e0c7 HACK: drm/i915/icl: Add changes to program DSI panel GPIOs 48813c1d2c3a HACK: drm/i915/icl: Configure backlight functions for DSI 0de32c2896a1 HACK: drm/i915/bios: ignore VBT not overflowing the mailbox

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Patchwork

2018-12-03 11:23 UTC #34 lore raw

✗ Fi.CI.SPARSE: warning for drm/i915/icl: dsi enabling (rev7)

In reply to Jani Nikula

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
Okay!

Commit: drm/i915/icl: Sanitize DDI port clock gating for DSI ports Okay!

Commit: drm/i915/icl: Calculate DPLL params for DSI Okay!

Commit: drm/i915/icl: Allocate DSI encoder/connector +./include/linux/slab.h:332:43: warning: dubious: x & !y

Commit: drm/i915/icl: Use the same pll functions for dsi Okay!

Commit: drm/i915/icl: Fill DSI ports info
Okay!

Commit: drm/i915/icl: Allocate DSI hosts and imlement host transfer +drivers/gpu/drm/i915/icl_dsi.c:129:33: warning: expression using sizeof(void)

Commit: drm/i915/icl: Add get config functionality for DSI Okay!

Commit: drm/i915/icl: Get HW state for DSI encoder Okay!

Commit: drm/i915/icl: Add DSI encoder compute config hook Okay!

Commit: drm/i915/icl: Configure DSI Dual link mode Okay!

Commit: drm/i915/icl: Consider DSI for getting transcoder state Okay!

Commit: drm/i915/icl: Get pipe timings for DSI
Okay!

Commit: drm/i915/icl: Define missing bitfield for shortplug reg Okay!

Commit: drm/i915/icl: Define Panel power ctrl register Okay!

Commit: drm/i915/icl: Define display GPIO pins for DSI Okay!

Commit: drm/i915/icl: add dummy DSI GPIO element execution function Okay!

Commit: drm/i915/icl: Gate clocks for DSI
Okay!

Commit: drm/i915/icl: Ungate DSI clocks
Okay!

Commit: drm/i915/icl: add pll mapping for DSI
Okay!

Commit: HACK: drm/i915/icl: Add changes to program DSI panel GPIOs Okay!

Commit: HACK: drm/i915/icl: Configure backlight functions for DSI Okay!

Commit: HACK: drm/i915/bios: ignore VBT not overflowing the mailbox Okay!

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Patchwork

2018-12-03 11:40 UTC #35 lore raw

✓ Fi.CI.BAT: success for drm/i915/icl: dsi enabling (rev7)

In reply to Jani Nikula

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5239 -> Patchwork_10995
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/7/mbox/

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_10995:

### IGT changes ###

#### Possible regressions ####

* igt@kms_flip@basic-flip-vs-dpms:
- {fi-icl-u3}: PASS -> DMESG-WARN

* {igt@runner@aborted}:
- {fi-icl-u3}: NOTRUN -> FAIL

Known issues
------------

Here are the changes found in Patchwork_10995 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m: PASS -> FAIL [fdo#108880]

* igt@i915_selftest@live_coherency:
- fi-gdg-551: PASS -> DMESG-FAIL [fdo#107164]

* {igt@runner@aborted}:
- {fi-icl-y}: NOTRUN -> FAIL [fdo#108070]

#### Possible fixes ####

* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#108622] -> PASS

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107164]: https://bugs.freedesktop.org/show_bug.cgi?id=107164
[fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880

Participating hosts (47 -> 42)
------------------------------

Additional (1): fi-icl-y
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510

Build changes
-------------

* Linux: CI_DRM_5239 -> Patchwork_10995

CI_DRM_5239: 6b82ae50cbf9b70fb3884937a221f69261c4c41c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10995: 0de32c2896a1ff7e0d9f7663bf3c52dff55cf8f4 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

0de32c2896a1 HACK: drm/i915/bios: ignore VBT not overflowing the mailbox 48813c1d2c3a HACK: drm/i915/icl: Configure backlight functions for DSI 061f3e41e0c7 HACK: drm/i915/icl: Add changes to program DSI panel GPIOs 079bbc7aeea6 drm/i915/icl: add pll mapping for DSI
8f5d87749941 drm/i915/icl: Ungate DSI clocks
c3483c42f102 drm/i915/icl: Gate clocks for DSI
b2fffaad2d0f drm/i915/icl: add dummy DSI GPIO element execution function 70438b447157 drm/i915/icl: Define display GPIO pins for DSI 1027ae61ad4a drm/i915/icl: Define Panel power ctrl register 24945f1aac4a drm/i915/icl: Define missing bitfield for shortplug reg 8463e98e1a20 drm/i915/icl: Get pipe timings for DSI
978f80d3edf2 drm/i915/icl: Consider DSI for getting transcoder state 532aa53e71c8 drm/i915/icl: Configure DSI Dual link mode
7d6ef2834195 drm/i915/icl: Add DSI encoder compute config hook 3f22982ec59a drm/i915/icl: Get HW state for DSI encoder
33521ef27138 drm/i915/icl: Add get config functionality for DSI 62513a8970ed drm/i915/icl: Allocate DSI hosts and imlement host transfer 50773017b12a drm/i915/icl: Fill DSI ports info
028d3c2eb0e4 drm/i915/icl: Use the same pll functions for dsi fbb01f92a65c drm/i915/icl: Allocate DSI encoder/connector 87b45256f131 drm/i915/icl: Calculate DPLL params for DSI
a3c740ce09ea drm/i915/icl: Sanitize DDI port clock gating for DSI ports 96d02a19d096 drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10995/
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-12-03 14:08 UTC #36 lore raw

In reply to Jani Nikula

Quoted 8 lines · Jani Nikula

v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].

Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.

Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!

BR,
Jani.

Quoted 55 lines

BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3] http://patchwork.freedesktop.org/patch/msgid/[email protected]
[4] http://patchwork.freedesktop.org/patch/msgid/[email protected]
[5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)

Signature · 5 lines

Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patchwork

2018-12-03 14:09 UTC #46 lore raw

✓ Fi.CI.IGT: success for drm/i915/icl: dsi enabling (rev7)

In reply to Jani Nikula

== Series Details ==

Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5239_full -> Patchwork_10995_full
====================================================

Summary
-------

**WARNING**

Minor unknown changes coming with Patchwork_10995_full need to be verified manually.

If you think the reported changes have nothing to do with the changes introduced in Patchwork_10995_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI.

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_10995_full:

### IGT changes ###

#### Possible regressions ####

* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- {shard-iclb}: PASS -> DMESG-WARN +28

* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- {shard-iclb}: NOTRUN -> DMESG-WARN

* {igt@runner@aborted}:
- {shard-iclb}: NOTRUN -> ( 35 FAIL ) [fdo#105702]

#### Warnings ####

* igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- {shard-iclb}: FAIL [fdo#107725] -> DMESG-FAIL

* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- {shard-iclb}: FAIL [fdo#103166] -> DMESG-WARN

* igt@kms_vblank@pipe-a-wait-busy:
- shard-snb: SKIP -> PASS +1

Known issues
------------

Here are the changes found in Patchwork_10995_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_eio@reset-stress:
- shard-glk: PASS -> FAIL [fdo#107799]

* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl: PASS -> TIMEOUT [fdo#108039]

* igt@gem_userptr_blits@readonly-unsync:
- shard-skl: PASS -> TIMEOUT [fdo#108887]
- shard-kbl: PASS -> TIMEOUT [fdo#108887]

* igt@gem_userptr_blits@stress-mm-invalidate-close-overlap:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]

* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-snb: PASS -> DMESG-WARN [fdo#107956]

* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]

* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]

* igt@kms_color@pipe-a-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]

* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103232]

* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-glk: PASS -> FAIL [fdo#103232]

* igt@kms_fbcon_fbt@psr:
- shard-skl: NOTRUN -> FAIL [fdo#107882]

* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-hsw: PASS -> FAIL [fdo#102887]

* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: PASS -> FAIL [fdo#105363]

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: PASS -> FAIL [fdo#103167] +1

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-glk: PASS -> FAIL [fdo#103167] +2

* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#106978]

* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815] / [fdo#108145]

* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]

* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166]

* igt@kms_properties@connector-properties-atomic:
- shard-skl: NOTRUN -> FAIL [fdo#108642]

* igt@pm_backlight@basic-brightness:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724]

#### Possible fixes ####

* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-glk: DMESG-WARN [fdo#107956] -> PASS

* igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-skl: FAIL [fdo#103232] -> PASS

* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-glk: FAIL [fdo#103232] -> PASS

* igt@kms_cursor_crc@cursor-64x64-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +2

* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: FAIL [fdo#105767] -> PASS

* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: FAIL [fdo#103184] -> PASS

* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS

* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: FAIL [fdo#103166] -> PASS +2

* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS

* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS +1

* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS

* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-hsw: FAIL [fdo#104894] -> PASS

* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-apl: DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +7

* igt@pm_rpm@gem-pread:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS

#### Warnings ####

* igt@kms_plane@pixel-format-pipe-b-planes:
- {shard-iclb}: FAIL [fdo#103166] -> DMESG-FAIL [fdo#103166]

* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: DMESG-FAIL [fdo#103558] / [fdo#105602] / [fdo#108145] -> FAIL [fdo#108145] +1

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (7 -> 7)
------------------------------

No changes in participating hosts

Build changes
-------------

* Linux: CI_DRM_5239 -> Patchwork_10995

== Logs ==

Chauhan, Madhav

2018-12-04 07:40 UTC #37 lore raw

In reply to Jani Nikula

Quoted 17 lines

-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 6 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.

Quoted 8 lines

Quoted 2 lines
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!

Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)

Regards,
Madhav

Quoted 67 lines

BR,
Jani.
Quoted 10 lines
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1-
jan
Quoted 2 lines
[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-1-
im
Quoted 30 lines
[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Quoted 6 lines
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
Quoted 9 lines
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)

Quoted 2 lines

--
Jani Nikula, Intel Open Source Graphics Center

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Lisovskiy, Stanislav

2018-12-04 16:26 UTC #38 lore raw

Hi,

Currently ICL DSI panel seems to work fine, however I still face mainly two issues, which probably need to be addressed:

1) There is still pipe_config mismatch assertion:

[   13.119965] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   13.119989] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   13.120015] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   13.120038] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   13.120061] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   13.120083] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   13.120113] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   13.120139] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   13.120169] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   13.120188] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   13.120207] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   13.120225] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)

Also whenever I run some suspend test case(for example I use igt@kms_vblank@pipe-a-ts-continuation-suspend I start to get it everytime machine wakes up, DSI panel get blank and doesn't recover from that.

2) During reboot, there are sometimes flood of "The master control interrupt lied (DE PIPE)!" messages visible. Looks like GEN8_DE_PIPE_IIR(pipe) which reads as 0 toggles this. Looks like also if I add a few retries it reads correctly.

Could this be also because I'm still using old BIOS, which I've got initially from Vandita?

Best Regards,

Lisovskiy Stanislav

Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo

________________________________________
From: Chauhan, Madhav
Sent: Tuesday, December 04, 2018 9:40 AM
To: Nikula, Jani; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Lisovskiy, Stanislav; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling

Quoted 17 lines

-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 6 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.

Quoted 8 lines

Quoted 2 lines
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!

Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)

Regards,
Madhav

Quoted 67 lines

BR,
Jani.
Quoted 10 lines
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1-
jan
Quoted 2 lines
[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-1-
im
Quoted 30 lines
[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Quoted 6 lines
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
Quoted 9 lines
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)

Quoted 2 lines

--
Jani Nikula, Intel Open Source Graphics Center

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-12-04 17:13 UTC #39 lore raw

Quoted 4 lines · Stanislav

Hi,
Currently ICL DSI panel seems to work fine, however I still face mainly two issues, which probably need to be addressed:

Please try with current drm-tip with

commit 0716931a82b4d0e211d2ef66616ad7130107e455

Author: Jani Nikula <[email protected]>
Date:   Tue Dec 4 12:19:26 2018 +0200

drm/i915/icl: fix transcoder state readout

plus the hack patches from the end of the series. It's possible only the VBT one is required.

BR,
Jani.

Quoted 140 lines

1) There is still pipe_config mismatch assertion:
[   13.119965] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   13.119989] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   13.120015] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   13.120038] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   13.120061] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   13.120083] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   13.120113] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   13.120139] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   13.120169] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   13.120188] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   13.120207] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   13.120225] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Also whenever I run some suspend test case(for example I use igt@kms_vblank@pipe-a-ts-continuation-suspend I start to get it everytime machine wakes up, DSI panel get blank and doesn't recover from that.
2) During reboot, there are sometimes flood of "The master control interrupt lied (DE PIPE)!" messages visible. Looks like GEN8_DE_PIPE_IIR(pipe) which reads as 0 toggles this. Looks like also if I add a few retries it reads correctly.
Could this be also because I'm still using old BIOS, which I've got initially from Vandita?
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Chauhan, Madhav
Sent: Tuesday, December 04, 2018 9:40 AM
To: Nikula, Jani; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Lisovskiy, Stanislav; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 17 lines
-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 6 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.
Quoted 8 lines
Quoted 2 lines
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!
Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)
Regards,
Madhav
Quoted 69 lines
BR,
Jani.
Quoted 10 lines
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1-
jan
Quoted 2 lines
[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-1-
im
Quoted 30 lines
[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Quoted 6 lines
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
Quoted 9 lines
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center

Signature · 5 lines

Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Lisovskiy, Stanislav

2018-12-05 07:49 UTC #40 lore raw

Hi Jani,

I've tried previously with branch icl-dsi-2018-12-03 for your github repo. I think it has everything except this 4.12.2018 "fix transcoder state readout" commit.

I will apply it and try with that now, thanks.

Best Regards,

Lisovskiy Stanislav

Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo

________________________________________
From: Nikula, Jani
Sent: Tuesday, December 04, 2018 7:13 PM
To: Lisovskiy, Stanislav; Chauhan, Madhav; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling

Quoted 4 lines · Stanislav

Hi,
Currently ICL DSI panel seems to work fine, however I still face mainly two issues, which probably need to be addressed:

Please try with current drm-tip with

commit 0716931a82b4d0e211d2ef66616ad7130107e455

Author: Jani Nikula <[email protected]>
Date:   Tue Dec 4 12:19:26 2018 +0200

drm/i915/icl: fix transcoder state readout

plus the hack patches from the end of the series. It's possible only the VBT one is required.

BR,
Jani.

Quoted 61 lines

1) There is still pipe_config mismatch assertion:
[   13.119965] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   13.119989] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   13.120015] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   13.120038] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   13.120061] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   13.120083] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   13.120113] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   13.120139] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   13.120169] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   13.120188] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   13.120207] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   13.120225] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Also whenever I run some suspend test case(for example I use igt@kms_vblank@pipe-a-ts-continuation-suspend I start to get it everytime machine wakes up, DSI panel get blank and doesn't recover from that.
2) During reboot, there are sometimes flood of "The master control interrupt lied (DE PIPE)!" messages visible. Looks like GEN8_DE_PIPE_IIR(pipe) which reads as 0 toggles this. Looks like also if I add a few retries it reads correctly.
Could this be also because I'm still using old BIOS, which I've got initially from Vandita?
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Chauhan, Madhav
Sent: Tuesday, December 04, 2018 9:40 AM
To: Nikula, Jani; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Lisovskiy, Stanislav; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 23 lines
-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 8 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.

Quoted 79 lines

Quoted 2 lines
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!
Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)
Regards,
Madhav
Quoted 69 lines
BR,
Jani.
Quoted 10 lines
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1-
jan
Quoted 2 lines
[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-1-
im
Quoted 30 lines
[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Quoted 6 lines
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
Quoted 9 lines
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center

--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Lisovskiy, Stanislav

2018-12-05 08:25 UTC #41 lore raw

I still see this pipe config mismatch(with icl-dsi-2018-12-03(4.20.0-rc5) + "fix transcoder state readout" commit applied):

[   12.773332] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   12.773425] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   12.773510] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   12.773588] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   12.773663] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   12.773735] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   12.773813] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   12.773897] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   12.773976] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   12.774039] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   12.774099] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   12.774157] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)

To me it looks different from https://bugs.freedesktop.org/show_bug.cgi?id=108928 bug.

Also there are still "The master control interrupt lied (DE PIPE)!" messages( Pipe IIR register is read as 0, while
master_ctl has a correspondent flag set) - however with this one I can at least cope by adding a few retries in the interrupt handler as a workaround. Then the flooding stops. Not sure if this is a proper fix though.

I also run kms_draw_crc test with this board(investigating https://bugs.freedesktop.org/show_bug.cgi?id=103184),
and sometimes half of the tests fail with the crc mismatch, I think this is kind of different thing.

Best Regards,

Lisovskiy Stanislav

Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo

________________________________________
From: Intel-gfx [[email protected]] on behalf of Lisovskiy, Stanislav [[email protected]]
Sent: Wednesday, December 05, 2018 9:49 AM
To: Nikula, Jani; Chauhan, Madhav; [email protected]
Subject: Re: [Intel-gfx] [PATCH v11 00/23] drm/i915/icl: dsi enabling

Hi Jani,

I've tried previously with branch icl-dsi-2018-12-03 for your github repo. I think it has everything except this 4.12.2018 "fix transcoder state readout" commit.

I will apply it and try with that now, thanks.

Best Regards,

Lisovskiy Stanislav

Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo

Quoted 4 lines · Stanislav

Hi,
Currently ICL DSI panel seems to work fine, however I still face mainly two issues, which probably need to be addressed:

Please try with current drm-tip with

commit 0716931a82b4d0e211d2ef66616ad7130107e455

Author: Jani Nikula <[email protected]>
Date:   Tue Dec 4 12:19:26 2018 +0200

drm/i915/icl: fix transcoder state readout

plus the hack patches from the end of the series. It's possible only the VBT one is required.

BR,
Jani.

Quoted 61 lines

1) There is still pipe_config mismatch assertion:
[   13.119965] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   13.119989] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   13.120015] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   13.120038] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   13.120061] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   13.120083] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   13.120113] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   13.120139] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   13.120169] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   13.120188] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   13.120207] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   13.120225] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Also whenever I run some suspend test case(for example I use igt@kms_vblank@pipe-a-ts-continuation-suspend I start to get it everytime machine wakes up, DSI panel get blank and doesn't recover from that.
2) During reboot, there are sometimes flood of "The master control interrupt lied (DE PIPE)!" messages visible. Looks like GEN8_DE_PIPE_IIR(pipe) which reads as 0 toggles this. Looks like also if I add a few retries it reads correctly.
Could this be also because I'm still using old BIOS, which I've got initially from Vandita?
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Chauhan, Madhav
Sent: Tuesday, December 04, 2018 9:40 AM
To: Nikula, Jani; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Lisovskiy, Stanislav; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 23 lines
-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 8 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.

Quoted 79 lines

Quoted 2 lines
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!
Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)
Regards,
Madhav
Quoted 69 lines
BR,
Jani.
Quoted 10 lines
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1-
jan
Quoted 2 lines
[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-1-
im
Quoted 30 lines
[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Quoted 6 lines
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
Quoted 9 lines
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center

--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Jani Nikula

author

2018-12-05 08:34 UTC #42 lore raw

Quoted 15 lines · Stanislav

I still see this pipe config mismatch(with icl-dsi-2018-12-03(4.20.0-rc5) + "fix transcoder state readout" commit applied):

[   12.773332] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   12.773425] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   12.773510] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   12.773588] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   12.773663] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   12.773735] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   12.773813] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   12.773897] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   12.773976] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   12.774039] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   12.774099] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   12.774157] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)

Quoted 1 line

To me it looks different from https://bugs.freedesktop.org/show_bug.cgi?id=108928 bug.

Okay, please file a new bug with the full dmesg. The above is not enough.

BR,
Jani.

Quoted 208 lines

Also there are still "The master control interrupt lied (DE PIPE)!" messages( Pipe IIR register is read as 0, while
master_ctl has a correspondent flag set) - however with this one I can at least cope by adding a few retries in the interrupt handler as a workaround. Then the flooding stops. Not sure if this is a proper fix though.
I also run kms_draw_crc test with this board(investigating https://bugs.freedesktop.org/show_bug.cgi?id=103184),
and sometimes half of the tests fail with the crc mismatch, I think this is kind of different thing.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Intel-gfx [[email protected]] on behalf of Lisovskiy, Stanislav [[email protected]]
Sent: Wednesday, December 05, 2018 9:49 AM
To: Nikula, Jani; Chauhan, Madhav; [email protected]
Subject: Re: [Intel-gfx] [PATCH v11 00/23] drm/i915/icl: dsi enabling
Hi Jani,
I've tried previously with branch icl-dsi-2018-12-03 for your github repo. I think it has everything except this 4.12.2018 "fix transcoder state readout" commit.
I will apply it and try with that now, thanks.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Nikula, Jani
Sent: Tuesday, December 04, 2018 7:13 PM
To: Lisovskiy, Stanislav; Chauhan, Madhav; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 4 lines · Stanislav
Hi,
Currently ICL DSI panel seems to work fine, however I still face mainly two issues, which probably need to be addressed:
Please try with current drm-tip with
commit 0716931a82b4d0e211d2ef66616ad7130107e455
Author: Jani Nikula <[email protected]>
Date:   Tue Dec 4 12:19:26 2018 +0200
drm/i915/icl: fix transcoder state readout
plus the hack patches from the end of the series. It's possible only the VBT one is required.
BR,
Jani.
Quoted 61 lines
1) There is still pipe_config mismatch assertion:
[   13.119965] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   13.119989] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   13.120015] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   13.120038] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   13.120061] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   13.120083] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   13.120113] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   13.120139] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   13.120169] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   13.120188] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   13.120207] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   13.120225] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Also whenever I run some suspend test case(for example I use igt@kms_vblank@pipe-a-ts-continuation-suspend I start to get it everytime machine wakes up, DSI panel get blank and doesn't recover from that.
2) During reboot, there are sometimes flood of "The master control interrupt lied (DE PIPE)!" messages visible. Looks like GEN8_DE_PIPE_IIR(pipe) which reads as 0 toggles this. Looks like also if I add a few retries it reads correctly.
Could this be also because I'm still using old BIOS, which I've got initially from Vandita?
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Chauhan, Madhav
Sent: Tuesday, December 04, 2018 9:40 AM
To: Nikula, Jani; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Lisovskiy, Stanislav; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 23 lines
-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 8 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.
Quoted 79 lines
Quoted 2 lines
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!
Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)
Regards,
Madhav
Quoted 69 lines
BR,
Jani.
Quoted 10 lines
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1-
jan
Quoted 2 lines
[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-1-
im
Quoted 30 lines
[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Quoted 6 lines
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
Quoted 9 lines
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Signature · 5 lines

Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Lisovskiy, Stanislav

2018-12-05 08:48 UTC #43 lore raw

Ok, I didn't file a bug yet, because I still have suspicion that this could be a bios thing.

Vandita, Madhav, did you happen to see same issue?

Best Regards,

Lisovskiy Stanislav

Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo

________________________________________
From: Nikula, Jani
Sent: Wednesday, December 05, 2018 10:35 AM
To: Lisovskiy, Stanislav; Chauhan, Madhav; [email protected]
Cc: Peres, Martin; Saarinen, Jani
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling

Quoted 15 lines · Stanislav

I still see this pipe config mismatch(with icl-dsi-2018-12-03(4.20.0-rc5) + "fix transcoder state readout" commit applied):

[   12.773332] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   12.773425] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   12.773510] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   12.773588] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   12.773663] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   12.773735] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   12.773813] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   12.773897] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   12.773976] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   12.774039] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   12.774099] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   12.774157] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)

Quoted 1 line

To me it looks different from https://bugs.freedesktop.org/show_bug.cgi?id=108928 bug.

Okay, please file a new bug with the full dmesg. The above is not enough.

BR,
Jani.

Quoted 201 lines

Also there are still "The master control interrupt lied (DE PIPE)!" messages( Pipe IIR register is read as 0, while
master_ctl has a correspondent flag set) - however with this one I can at least cope by adding a few retries in the interrupt handler as a workaround. Then the flooding stops. Not sure if this is a proper fix though.
I also run kms_draw_crc test with this board(investigating https://bugs.freedesktop.org/show_bug.cgi?id=103184),
and sometimes half of the tests fail with the crc mismatch, I think this is kind of different thing.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Intel-gfx [[email protected]] on behalf of Lisovskiy, Stanislav [[email protected]]
Sent: Wednesday, December 05, 2018 9:49 AM
To: Nikula, Jani; Chauhan, Madhav; [email protected]
Subject: Re: [Intel-gfx] [PATCH v11 00/23] drm/i915/icl: dsi enabling
Hi Jani,
I've tried previously with branch icl-dsi-2018-12-03 for your github repo. I think it has everything except this 4.12.2018 "fix transcoder state readout" commit.
I will apply it and try with that now, thanks.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Nikula, Jani
Sent: Tuesday, December 04, 2018 7:13 PM
To: Lisovskiy, Stanislav; Chauhan, Madhav; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 4 lines · Stanislav
Hi,
Currently ICL DSI panel seems to work fine, however I still face mainly two issues, which probably need to be addressed:
Please try with current drm-tip with
commit 0716931a82b4d0e211d2ef66616ad7130107e455
Author: Jani Nikula <[email protected]>
Date:   Tue Dec 4 12:19:26 2018 +0200
drm/i915/icl: fix transcoder state readout
plus the hack patches from the end of the series. It's possible only the VBT one is required.
BR,
Jani.
Quoted 61 lines
1) There is still pipe_config mismatch assertion:
[   13.119965] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   13.119989] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   13.120015] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   13.120038] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   13.120061] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   13.120083] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   13.120113] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   13.120139] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   13.120169] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   13.120188] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   13.120207] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   13.120225] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Also whenever I run some suspend test case(for example I use igt@kms_vblank@pipe-a-ts-continuation-suspend I start to get it everytime machine wakes up, DSI panel get blank and doesn't recover from that.
2) During reboot, there are sometimes flood of "The master control interrupt lied (DE PIPE)!" messages visible. Looks like GEN8_DE_PIPE_IIR(pipe) which reads as 0 toggles this. Looks like also if I add a few retries it reads correctly.
Could this be also because I'm still using old BIOS, which I've got initially from Vandita?
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Chauhan, Madhav
Sent: Tuesday, December 04, 2018 9:40 AM
To: Nikula, Jani; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Lisovskiy, Stanislav; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 23 lines
-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 8 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.
Quoted 79 lines
Quoted 2 lines
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!
Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)
Regards,
Madhav
Quoted 69 lines
BR,
Jani.
Quoted 10 lines
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1-
jan
Quoted 2 lines
[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-1-
im
Quoted 30 lines
[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Quoted 6 lines
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
Quoted 9 lines
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center

Quoted 7 lines

--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Chauhan, Madhav

2018-12-05 08:55 UTC #44 lore raw

However I have not seen fdo bug mentioned below, but root cause for these pipe config error messages are due to the fact that for dual link we are programming half the timings but while comparing We use undivided values.

Moreover some timings are not even gets programmed for DSI like HBLANK/VBLANK etc. So while dumping pipe_config errors we need to consider dual link scenario for DSI.

Regards,
Madhav

Quoted 309 lines

-----Original Message-----
From: Lisovskiy, Stanislav
Sent: Wednesday, December 5, 2018 2:18 PM
To: Nikula, Jani <[email protected]>; Chauhan, Madhav <[email protected]>; [email protected]
Cc: Peres, Martin <[email protected]>; Saarinen, Jani <[email protected]>; Kulkarni, Vandita <[email protected]>
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Ok, I didn't file a bug yet, because I still have suspicion that this could be a bios thing.
Vandita, Madhav, did you happen to see same issue?
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Nikula, Jani
Sent: Wednesday, December 05, 2018 10:35 AM
To: Lisovskiy, Stanislav; Chauhan, Madhav; [email protected]
Cc: Peres, Martin; Saarinen, Jani
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 1 line · Stanislav
I still see this pipe config mismatch(with icl-dsi-2018-12-03(4.20.0-rc5) + "fix
transcoder state readout" commit applied):
Quoted 2 lines
[   12.773332] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
Quoted 1 line
[   12.773425] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_htotal (expected 1586, found 793)
Quoted 1 line
[   12.773510] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
Quoted 1 line
[   12.773588] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
Quoted 1 line
[   12.773663] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
Quoted 1 line
[   12.773735] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
Quoted 1 line
[   12.773813] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
Quoted 1 line
[   12.773897] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
Quoted 1 line
[   12.773976] [drm:pipe_config_err [i915]] *ERROR* mismatch in
output_format (expected 0, found 1)
Quoted 1 line
[   12.774039] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate
(expected 245700, found 122850)
Quoted 1 line
[   12.774099] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp
(expected 24, found 0)
Quoted 1 line
[   12.774157] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Quoted 2 lines
To me it looks different from
https://bugs.freedesktop.org/show_bug.cgi?id=108928 bug.
Okay, please file a new bug with the full dmesg. The above is not enough.
BR,
Jani.
Quoted 3 lines
Also there are still "The master control interrupt lied (DE PIPE)!" messages( Pipe IIR register is read as 0, while master_ctl has a
correspondent flag set) - however with this one I can at least cope by adding a few retries in the interrupt handler as a workaround. Then the flooding stops. Not sure if this is a proper fix though.
Quoted 4 lines
I also run kms_draw_crc test with this board(investigating
https://bugs.freedesktop.org/show_bug.cgi?id=103184),
and sometimes half of the tests fail with the crc mismatch, I think this is
kind of different thing.
Quoted 16 lines
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Intel-gfx [[email protected]] on behalf of Lisovskiy, Stanislav [[email protected]]
Sent: Wednesday, December 05, 2018 9:49 AM
To: Nikula, Jani; Chauhan, Madhav; [email protected]
Subject: Re: [Intel-gfx] [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 4 lines
Hi Jani,
I've tried previously with branch icl-dsi-2018-12-03 for your github repo. I think it has everything except this 4.12.2018 "fix transcoder state
readout" commit.
Quoted 19 lines
I will apply it and try with that now, thanks.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Nikula, Jani
Sent: Tuesday, December 04, 2018 7:13 PM
To: Lisovskiy, Stanislav; Chauhan, Madhav; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
On Tue, 04 Dec 2018, "Lisovskiy, Stanislav" <[email protected]>
Quoted 11 lines · wrote:
Quoted 4 lines
Hi,
Currently ICL DSI panel seems to work fine, however I still face mainly two issues, which probably need to be addressed:
Please try with current drm-tip with
commit 0716931a82b4d0e211d2ef66616ad7130107e455
Author: Jani Nikula <[email protected]>
Date:   Tue Dec 4 12:19:26 2018 +0200
Quoted 12 lines
drm/i915/icl: fix transcoder state readout
plus the hack patches from the end of the series. It's possible only the VBT one is required.
BR,
Jani.
Quoted 4 lines
1) There is still pipe_config mismatch assertion:
[   13.119965] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
Quoted 1 line
Quoted 1 line
[   13.119989] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_htotal (expected 1586, found 793)
Quoted 1 line
Quoted 1 line
[   13.120015] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
Quoted 1 line
Quoted 1 line
[   13.120038] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
Quoted 1 line
Quoted 1 line
[   13.120061] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
Quoted 1 line
Quoted 1 line
[   13.120083] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
Quoted 1 line
Quoted 1 line
[   13.120113] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
Quoted 1 line
Quoted 1 line
[   13.120139] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
Quoted 1 line
Quoted 1 line
[   13.120169] [drm:pipe_config_err [i915]] *ERROR* mismatch in
output_format (expected 0, found 1)
Quoted 1 line
Quoted 1 line
[   13.120188] [drm:pipe_config_err [i915]] *ERROR* mismatch in
pixel_rate (expected 245700, found 122850)
Quoted 1 line
Quoted 1 line
[   13.120207] [drm:pipe_config_err [i915]] *ERROR* mismatch in
pipe_bpp (expected 24, found 0)
Quoted 1 line
Quoted 1 line
[   13.120225] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Quoted 4 lines
Quoted 4 lines
Also whenever I run some suspend test case(for example I use igt@kms_vblank@pipe-a-ts-continuation-suspend
I start to get it everytime machine wakes up, DSI panel get blank and
doesn't recover from that.
Quoted 2 lines
Quoted 2 lines
2) During reboot, there are sometimes flood of "The master control
interrupt lied (DE PIPE)!" messages visible.
Quoted 4 lines
Quoted 4 lines
Looks like GEN8_DE_PIPE_IIR(pipe) which reads as 0 toggles this. Looks like also if I add a few retries it reads correctly.
Could this be also because I'm still using old BIOS, which I've got initially
from Vandita?
Quoted 56 lines
Quoted 56 lines
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Chauhan, Madhav
Sent: Tuesday, December 04, 2018 9:40 AM
To: Nikula, Jani; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Lisovskiy, Stanislav; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 17 lines
-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 6 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.
Quoted 8 lines
Quoted 2 lines
The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!
Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)
Regards,
Madhav
Quoted 8 lines
BR,
Jani.
Quoted 2 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
Quoted 1 line
-
jan
Quoted 2 lines
[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-
Quoted 10 lines
Quoted 10 lines
Quoted 10 lines
Quoted 1 line
1-
im
Quoted 8 lines
[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder
hooks
Quoted 43 lines
Quoted 39 lines
Quoted 39 lines
Quoted 22 lines
drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
Quoted 6 lines
Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
Quoted 9 lines
 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)
Quoted 3 lines
Quoted 2 lines
--
Jani Nikula, Intel Open Source Graphics Center
Quoted 7 lines
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Quoted 2 lines

--
Jani Nikula, Intel Open Source Graphics Center

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Lisovskiy, Stanislav

2018-12-07 09:05 UTC #45 lore raw

Hi,

I decided to create a simple patch, which fixes those warns:

[   12.773332] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
[   12.773425] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 1586, found 793)
[   12.773510] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
[   12.773588] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
[   12.773663] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
[   12.773735] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
[   12.773813] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
[   12.773897] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
[   12.773976] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   12.774039] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate (expected 245700, found 122850)
[   12.774099] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp (expected 24, found 0)
[   12.774157] [drm:pipe_config_err [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 245700, found 122850)

The patch itself is here:

https://patchwork.freedesktop.org/series/53727/

After that it complains only at output_format and scaler_id mismatch(which I currently don't know how to fix):

[   13.476929] [drm:pipe_config_err [i915]] *ERROR* mismatch in output_format (expected 0, found 1)
[   13.476994] [drm:pipe_config_err [i915]] *ERROR* mismatch in scaler_state.scaler_id (expected 0, found -1)

Best Regards,

Lisovskiy Stanislav

Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo

________________________________________
From: Chauhan, Madhav
Sent: Wednesday, December 05, 2018 10:54 AM
To: Lisovskiy, Stanislav; Nikula, Jani; [email protected]
Cc: Peres, Martin; Saarinen, Jani; Kulkarni, Vandita
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling

Moreover some timings are not even gets programmed for DSI like HBLANK/VBLANK etc. So while dumping pipe_config errors we need to consider dual link scenario for DSI.

Regards,
Madhav

Quoted 309 lines

-----Original Message-----
From: Lisovskiy, Stanislav
Sent: Wednesday, December 5, 2018 2:18 PM
To: Nikula, Jani <[email protected]>; Chauhan, Madhav <[email protected]>; [email protected]
Cc: Peres, Martin <[email protected]>; Saarinen, Jani <[email protected]>; Kulkarni, Vandita <[email protected]>
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Ok, I didn't file a bug yet, because I still have suspicion that this could be a bios thing.
Vandita, Madhav, did you happen to see same issue?
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Nikula, Jani
Sent: Wednesday, December 05, 2018 10:35 AM
To: Lisovskiy, Stanislav; Chauhan, Madhav; [email protected]
Cc: Peres, Martin; Saarinen, Jani
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 1 line · Stanislav
I still see this pipe config mismatch(with icl-dsi-2018-12-03(4.20.0-rc5) + "fix
transcoder state readout" commit applied):
Quoted 2 lines
[   12.773332] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
Quoted 1 line
[   12.773425] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_htotal (expected 1586, found 793)
Quoted 1 line
[   12.773510] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
Quoted 1 line
[   12.773588] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
Quoted 1 line
[   12.773663] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
Quoted 1 line
[   12.773735] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
Quoted 1 line
[   12.773813] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
Quoted 1 line
[   12.773897] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
Quoted 1 line
[   12.773976] [drm:pipe_config_err [i915]] *ERROR* mismatch in
output_format (expected 0, found 1)
Quoted 1 line
[   12.774039] [drm:pipe_config_err [i915]] *ERROR* mismatch in pixel_rate
(expected 245700, found 122850)
Quoted 1 line
[   12.774099] [drm:pipe_config_err [i915]] *ERROR* mismatch in pipe_bpp
(expected 24, found 0)
Quoted 1 line
[   12.774157] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Quoted 2 lines
To me it looks different from
https://bugs.freedesktop.org/show_bug.cgi?id=108928 bug.
Okay, please file a new bug with the full dmesg. The above is not enough.
BR,
Jani.
Quoted 3 lines
Also there are still "The master control interrupt lied (DE PIPE)!" messages( Pipe IIR register is read as 0, while master_ctl has a
correspondent flag set) - however with this one I can at least cope by adding a few retries in the interrupt handler as a workaround. Then the flooding stops. Not sure if this is a proper fix though.
Quoted 4 lines
I also run kms_draw_crc test with this board(investigating
https://bugs.freedesktop.org/show_bug.cgi?id=103184),
and sometimes half of the tests fail with the crc mismatch, I think this is
kind of different thing.
Quoted 16 lines
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Intel-gfx [[email protected]] on behalf of Lisovskiy, Stanislav [[email protected]]
Sent: Wednesday, December 05, 2018 9:49 AM
To: Nikula, Jani; Chauhan, Madhav; [email protected]
Subject: Re: [Intel-gfx] [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 4 lines
Hi Jani,
I've tried previously with branch icl-dsi-2018-12-03 for your github repo. I think it has everything except this 4.12.2018 "fix transcoder state
readout" commit.
Quoted 19 lines
I will apply it and try with that now, thanks.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Nikula, Jani
Sent: Tuesday, December 04, 2018 7:13 PM
To: Lisovskiy, Stanislav; Chauhan, Madhav; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
On Tue, 04 Dec 2018, "Lisovskiy, Stanislav" <[email protected]>
Quoted 11 lines · wrote:
Quoted 4 lines
Hi,
Currently ICL DSI panel seems to work fine, however I still face mainly two issues, which probably need to be addressed:
Please try with current drm-tip with
commit 0716931a82b4d0e211d2ef66616ad7130107e455
Author: Jani Nikula <[email protected]>
Date:   Tue Dec 4 12:19:26 2018 +0200
Quoted 12 lines
drm/i915/icl: fix transcoder state readout
plus the hack patches from the end of the series. It's possible only the VBT one is required.
BR,
Jani.
Quoted 4 lines
1) There is still pipe_config mismatch assertion:
[   13.119965] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hdisplay (expected 1440, found 720)
Quoted 1 line
Quoted 1 line
[   13.119989] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_htotal (expected 1586, found 793)
Quoted 1 line
Quoted 1 line
[   13.120015] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hblank_start (expected 1440, found 1)
Quoted 1 line
Quoted 1 line
[   13.120038] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hblank_end (expected 1586, found 1)
Quoted 1 line
Quoted 1 line
[   13.120061] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hsync_start (expected 1540, found 770)
Quoted 1 line
Quoted 1 line
[   13.120083] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_hsync_end (expected 1550, found 775)
Quoted 1 line
Quoted 1 line
[   13.120113] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_vblank_start (expected 2560, found 1)
Quoted 1 line
Quoted 1 line
[   13.120139] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_vblank_end (expected 2582, found 1)
Quoted 1 line
Quoted 1 line
[   13.120169] [drm:pipe_config_err [i915]] *ERROR* mismatch in
output_format (expected 0, found 1)
Quoted 1 line
Quoted 1 line
[   13.120188] [drm:pipe_config_err [i915]] *ERROR* mismatch in
pixel_rate (expected 245700, found 122850)
Quoted 1 line
Quoted 1 line
[   13.120207] [drm:pipe_config_err [i915]] *ERROR* mismatch in
pipe_bpp (expected 24, found 0)
Quoted 1 line
Quoted 1 line
[   13.120225] [drm:pipe_config_err [i915]] *ERROR* mismatch in
base.adjusted_mode.crtc_clock (expected 245700, found 122850)
Quoted 4 lines
Quoted 4 lines
Also whenever I run some suspend test case(for example I use igt@kms_vblank@pipe-a-ts-continuation-suspend
I start to get it everytime machine wakes up, DSI panel get blank and
doesn't recover from that.
Quoted 2 lines
Quoted 2 lines
2) During reboot, there are sometimes flood of "The master control
interrupt lied (DE PIPE)!" messages visible.
Quoted 4 lines
Quoted 4 lines
Looks like GEN8_DE_PIPE_IIR(pipe) which reads as 0 toggles this. Looks like also if I add a few retries it reads correctly.
Could this be also because I'm still using old BIOS, which I've got initially
from Vandita?
Quoted 56 lines
Quoted 56 lines
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Chauhan, Madhav
Sent: Tuesday, December 04, 2018 9:40 AM
To: Nikula, Jani; [email protected]
Cc: [email protected]; Kulkarni, Vandita; Lisovskiy, Stanislav; Deak, Imre
Subject: RE: [PATCH v11 00/23] drm/i915/icl: dsi enabling
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-----Original Message-----
From: Nikula, Jani
Sent: Monday, December 3, 2018 7:39 PM
To: [email protected]
Cc: [email protected]; Chauhan, Madhav <[email protected]>; Kulkarni, Vandita <[email protected]>; Lisovskiy, Stanislav <[email protected]>; Deak, Imre <[email protected]>
Subject: Re: [PATCH v11 00/23] drm/i915/icl: dsi enabling
Quoted 6 lines · Jani Nikula
v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL mapping and gating patches [3] from me and [4] from Imre.
It made sense to squash some patches in [1] and [2] together, I've tried to set authorship and co-developed-by tags fairly.
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The series is also available in icl-dsi-2018-11-29 branch of my fdo git repo [5].
Pushed the series to dinq except for the three HACK patches at the end. They'll still need to be addressed one way or another.
Thanks everyone for your contributions in writing the patches, reviewing, testing, etc. It's been a long ride!
Thanks a lot to you as well Jani N for your continuous support during design/development/review/merge Of this new/big feature :)
Regards,
Madhav
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BR,
Jani.
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BR,
Jani.
[1] https://patchwork.freedesktop.org/series/51011/
[2] https://patchwork.freedesktop.org/series/51373/
[3]
http://patchwork.freedesktop.org/patch/msgid/20181129115715.9152-1
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-
jan
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[email protected] [4]
http://patchwork.freedesktop.org/patch/msgid/20181127163606.28841-
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1-
im
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[email protected] [5] https://cgit.freedesktop.org/~jani/drm/
Imre Deak (1):
drm/i915/icl: Sanitize DDI port clock gating for DSI ports
Jani Nikula (4):
drm/i915/icl: push pll to port mapping/unmapping to ddi encoder
hooks
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drm/i915/icl: add dummy DSI GPIO element execution function drm/i915/icl: add pll mapping for DSI
HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
Madhav Chauhan (16):
drm/i915/icl: Calculate DPLL params for DSI drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info
drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder compute config hook drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI drm/i915/icl: Gate clocks for DSI
drm/i915/icl: Ungate DSI clocks
HACK: drm/i915/icl: Add changes to program DSI panel GPIOs
HACK: drm/i915/icl: Configure backlight functions for DSI
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Vandita Kulkarni (2):
drm/i915/icl: Use the same pll functions for dsi drm/i915/icl: Add get config functionality for DSI
 drivers/gpu/drm/i915/i915_reg.h       |  12 +
 drivers/gpu/drm/i915/icl_dsi.c        | 492
+++++++++++++++++++++++++++++++++-
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 drivers/gpu/drm/i915/intel_bios.c     |   1 -
 drivers/gpu/drm/i915/intel_ddi.c      | 153 ++++++-----
 drivers/gpu/drm/i915/intel_display.c  |  44 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/intel_drv.h      |   8 +-
 drivers/gpu/drm/i915/intel_dsi.h      |   5 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c  |  58 +++-
 drivers/gpu/drm/i915/intel_panel.c    |   3 +-
 10 files changed, 674 insertions(+), 105 deletions(-)
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--
Jani Nikula, Intel Open Source Graphics Center
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--
Jani Nikula, Intel Open Source Graphics Center
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--
Jani Nikula, Intel Open Source Graphics Center

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