gem_ctx_isolation.c - Gen11 enabling for context isolation test

PATCH In review Dale B Stimson 3 participants 8 messages Mar 5, 2019

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Dale B Stimson

author

2019-03-05 01:03 UTC #0 lore raw

v4 cover gem_ctx_isolation.c - Gen11 enabling for context isolation test

V4:

I have tested these changes on both SKL and ICL with no regressions detected.

I will note that both SKL and ICL seem to currently have (at least for my environment) suspend/resume issues which occur with or without these changes (and also for gem_exec_suspend). Therefore, the S3/S4 tests were not done.

Testing on ICL shows that Gen11 requires BB_OFFSET .ignore_bits = 0x7 instead of 0x4. I presume that the preferred way to do this is to change the existing table entry for BB_OFFSET instead of splitting it into separate entries for GEN8-10 and GEN11.

For those registers that are force_nonpriv for some Gen levels and not for others, I have chosen to show the two states as separate table entries to make this clear. In particular, this applies as shown below. Any objections to doing it that way?

+       { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
+       { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
+       { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true },
+
        /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
-       { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
+       { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
        { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },

- { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },

Dale B Stimson (1):
gem_ctx_isolation.c - Gen11 enabling for context isolation test

 tests/i915/gem_ctx_isolation.c | 47 +++++++++++++++++++++++++---------
 1 file changed, 35 insertions(+), 12 deletions(-)

Signature · 6 lines

2.21.0

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Dale B Stimson

author

2019-03-05 01:03 UTC #1 lore raw

PATCH v4 1/1 gem_ctx_isolation.c - Gen11 enabling for context isolation test

This patch is a change to igt file tests/i915/gem_ctx_isolation.c to add and enable Gen11 support.

This patch accounts for whitelisted registers appropriately for the different Gen levels.

This patch accounts for the changed MMIO offsets of Gen11.

This patch redefines MAX_REG from 0x40000 to 0x200000 due to the larger total register space for Gen11 mmio offsets.

A current Gen11 SKU has two video engines (with indexes 0 and 2, for VCS0 and VCS2), with VCS1 not being used.

Current kernel and igt limitations only allow for VCS0 and VCS1. Those limitations are in the process of being removed. See for example the RFC/PATCH series on igt-dev from Andy Shyti:
[igt-dev] [RFC PATCH v9 0/5] new engine discovery interface
which depends on in-process kernel "media scalability" patches.

Lacking the above infrastructure at the moment:

The array of registers to be tested includes VCS2 and VCS3 registers. They are present as a provision for the future, but they will not actually be tested as those engines are not yet known to the underlying infrastructure.

When run on Gen11 this patch skips the sub-tests for the non-existent VCS1 with these warnings:
Test requirement not met in function gem_require_engine, file ../lib/igt_gt.h:114:
Test requirement: gem_has_engine(gem_fd, class, instance)

Signed-off-by Dale B Stimson <[email protected]>

---
 tests/i915/gem_ctx_isolation.c | 47 +++++++++++++++++++++++++---------
 1 file changed, 35 insertions(+), 12 deletions(-)

tests/i915/gem_ctx_isolation.c +35 ~~-12~~

index e50cc9a7..f1000458 100644
@@ -24,7 +24,7 @@
 #include "igt.h"
 #include "igt_dummyload.h"
 
-#define MAX_REG 0x40000
+#define MAX_REG 0x200000
 #define NUM_REGS (MAX_REG / sizeof(uint32_t))
 
 #define PAGE_ALIGN(x) ALIGN(x, 4096)

@@ -41,6 +41,8 @@ enum {
 	BCS0 = ENGINE(I915_ENGINE_CLASS_COPY, 0),
 	VCS0 = ENGINE(I915_ENGINE_CLASS_VIDEO, 0),
 	VCS1 = ENGINE(I915_ENGINE_CLASS_VIDEO, 1),
+	VCS2 = ENGINE(I915_ENGINE_CLASS_VIDEO, 2),
+	VCS3 = ENGINE(I915_ENGINE_CLASS_VIDEO, 3),
 	VECS0 = ENGINE(I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
 };

@@ -52,10 +54,12 @@ enum {
 #define GEN7 (ALL << 7)
 #define GEN8 (ALL << 8)
 #define GEN9 (ALL << 9)
+#define GEN10 (ALL << 10)
+#define GEN11 (ALL << 11)
 
 #define NOCTX 0
 
-#define LAST_KNOWN_GEN 10
+#define LAST_KNOWN_GEN 11
 
 static const struct named_register {
 	const char *name;

@@ -103,7 +107,7 @@ static const struct named_register {
 	{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
 	{ "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
 	{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
-	{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
+	{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },
 	{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
 	{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
 	{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },

@@ -132,30 +136,49 @@ static const struct named_register {
 	{ "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
 	{ "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
 
+	{ "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
+	{ "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
+	{ "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true },
+
 	/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
-	{ "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
+	{ "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
 	{ "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
-	{ "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+	{ "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },
 	{ "L3SQREG4", NOCTX /* GEN9:skl,kbl */, RCS0, 0xb118, .write_mask = ~0x1ffff0 },
+	{ "HALF_SLICE_CHICKEN7", GEN_RANGE(11, 11), RCS0, 0xe194, .masked = true },
+	{ "SAMPLER_MODE", GEN_RANGE(11, 11), RCS0, 0xe18c, .masked = true },
 
 	{ "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
 	{ "BCS_SWCTRL", GEN8, BCS0, 0x22200, .write_mask = 0x3, .masked = true },
 
-	{ "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
 	{ "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
-
-	{ "VCS1_GPR", GEN9, VCS1, 0x1c600, 32 },
 	{ "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
 
-	{ "VECS_GPR", GEN9, VECS0, 0x1a600, 32 },
+	{ "VCS0_GPR", GEN_RANGE(9, 10), VCS0, 0x12600, 32 },
+	{ "VCS1_GPR", GEN_RANGE(9, 10), VCS1, 0x1c600, 32 },
+	{ "VECS_GPR", GEN_RANGE(9, 10), VECS0, 0x1a600, 32 },
+
+	{ "VCS0_GPR", GEN11, VCS0, 0x1c0600, 32 },
+	{ "VCS1_GPR", GEN11, VCS1, 0x1c4600, 32 },
+	{ "VCS2_GPR", GEN11, VCS2, 0x1d0600, 32 },
+	{ "VCS3_GPR", GEN11, VCS3, 0x1d4600, 32 },
+	{ "VECS_GPR", GEN11, VECS0, 0x1c8600, 32 },
 
 	{}
 }, ignore_registers[] = {
 	{ "RCS timestamp", GEN6, ~0u, 0x2358 },
-	{ "VCS0 timestamp", GEN7, ~0u, 0x12358 },
-	{ "VCS1 timestamp", GEN7, ~0u, 0x1c358 },
 	{ "BCS timestamp", GEN7, ~0u, 0x22358 },
-	{ "VECS timestamp", GEN8, ~0u, 0x1a358 },
+
+	{ "VCS0 timestamp", GEN_RANGE(7, 10), ~0u, 0x12358 },
+	{ "VCS1 timestamp", GEN_RANGE(7, 10), ~0u, 0x1c358 },
+	{ "VECS timestamp", GEN_RANGE(8, 10), ~0u, 0x1a358 },
+
+	{ "VCS0 timestamp", GEN11, ~0u, 0x1c0358 },
+	{ "VCS1 timestamp", GEN11, ~0u, 0x1c4358 },
+	{ "VCS2 timestamp", GEN11, ~0u, 0x1d0358 },
+	{ "VCS3 timestamp", GEN11, ~0u, 0x1d4358 },
+	{ "VECS timestamp", GEN11, ~0u, 0x1c8358 },
+
 	{}
 };

Signature · 6 lines

2.21.0

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Chris Wilson

2019-03-05 19:00 UTC #2 lore raw

Quoting Dale B Stimson (2019-03-05 01:03:08)

tests/i915/gem_ctx_isolation.c static const struct named_register { · line 140

Quoted 6 lines

tests/i915/gem_ctx_isolation.c +2 -0

@@ -132,30 +136,49 @@ static const struct named_register {
        { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
        { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
 
+       { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
+       { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },

CS_CHICKEN1 is still privileged? At least I'm push a patch to add it to the whitelist for gen11.
-Chris
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Dale B Stimson

author

2019-03-05 20:46 UTC #3 lore raw

CS_CHICKEN1 is not privileged anymore (as of Gen11), as evidenced by its absence from the kernel whitelist for Gen11 combined with the successful execution on ICL of the tests added by your recent patch "i915/gem_ctx_isolation: Sanitycheck nonpriv access".

-Dale

Quoted 11 lines · Chris Wilson

Quoting Dale B Stimson (2019-03-05 01:03:08)
tests/i915/gem_ctx_isolation.c static const struct named_register { · line 140
Quoted 6 lines
tests/i915/gem_ctx_isolation.c +2 -0
@@ -132,30 +136,49 @@ static const struct named_register {
        { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
        { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
 
+       { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
+       { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
CS_CHICKEN1 is still privileged? At least I'm push a patch to add it to the whitelist for gen11.
-Chris

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Chris Wilson

Reviewed-by

2019-03-05 20:56 UTC #4 lore raw

Quoting Dale B Stimson (2019-03-05 20:46:51)

Quoted 4 lines

CS_CHICKEN1 is not privileged anymore (as of Gen11), as evidenced by its absence from the kernel whitelist for Gen11 combined with the successful execution on ICL of the tests added by your recent patch "i915/gem_ctx_isolation: Sanitycheck nonpriv access".

Everything seems in order :)

Reviewed-by Chris Wilson <[email protected]>

-Chris
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Patchwork

2019-03-05 02:13 UTC #5 lore raw

[igt-dev] ✓ Fi.CI.BAT: success for gem_ctx_isolation.c - Gen11 enabling for context isolation test (rev5)

In reply to Dale B Stimson

== Series Details ==

Series: gem_ctx_isolation.c - Gen11 enabling for context isolation test (rev5)
URL : https://patchwork.freedesktop.org/series/56016/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5702 -> IGTPW_2552
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://patchwork.freedesktop.org/api/1.0/series/56016/revisions/5/mbox/

Known issues
------------

Here are the changes found in IGTPW_2552 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: PASS -> SKIP [fdo#109271]

* igt@i915_pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]

* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> WARN [fdo#109380]

* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33

* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]

#### Possible fixes ####

* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS

* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: SKIP [fdo#109271] / [fdo#109278] -> PASS +2
- fi-gdg-551: FAIL [fdo#103182] -> PASS

* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (44 -> 41)
------------------------------

Additional (1): fi-icl-y
Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-bdw-samus

Build changes
-------------

* IGT: IGT_4870 -> IGTPW_2552

CI_DRM_5702: 6e90cfc547f7145e1c3c057a8d5f117888e23d91 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2552: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2552/
IGT_4870: ed944b45563c694dc6373bc48dc83b8ba7edb19f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2552/
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Patchwork

2019-03-05 06:35 UTC #6 lore raw

[igt-dev] ✓ Fi.CI.IGT: success for gem_ctx_isolation.c - Gen11 enabling for context isolation test (rev5)

In reply to Dale B Stimson

== Series Details ==

Series: gem_ctx_isolation.c - Gen11 enabling for context isolation test (rev5)
URL : https://patchwork.freedesktop.org/series/56016/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5702_full -> IGTPW_2552_full
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://patchwork.freedesktop.org/api/1.0/series/56016/revisions/5/mbox/

Known issues
------------

Here are the changes found in IGTPW_2552_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_exec_schedule@promotion-bsd2:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +3

* igt@i915_pm_rpm@gem-execbuf-stress-extra-wait:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +34

* igt@kms_atomic_transition@4x-modeset-transitions-nonblocking-fencing:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4

* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]

* igt@kms_busy@extended-modeset-hang-newfb-render-d:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1

* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-kbl: PASS -> DMESG-WARN [fdo#107956] +1
- shard-hsw: PASS -> DMESG-WARN [fdo#107956]

* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: NOTRUN -> DMESG-WARN [fdo#107956]

* igt@kms_color@pipe-a-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]

* igt@kms_color@pipe-b-legacy-gamma:

    - shard-glk:          PASS -> FAIL [fdo#104782]
    - shard-apl:          PASS -> FAIL [fdo#104782]
    - shard-kbl:          PASS -> FAIL [fdo#104782]

* igt@kms_concurrent@pipe-c:
- shard-kbl: PASS -> DMESG-WARN [fdo#105345]

* igt@kms_concurrent@pipe-e:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3

* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232]

* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: PASS -> FAIL [fdo#103232] +5
- shard-kbl: PASS -> FAIL [fdo#103232] +3

* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: PASS -> FAIL [fdo#103232]

* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-glk: PASS -> FAIL [fdo#103167] +1

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-kbl: PASS -> FAIL [fdo#103167] +1

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: PASS -> FAIL [fdo#103167] +3

* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +19

* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +23

* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-apl: PASS -> FAIL [fdo#108948]

* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-glk: PASS -> FAIL [fdo#103166] +5

* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: PASS -> FAIL [fdo#103166] +5
- shard-kbl: PASS -> FAIL [fdo#103166] +1

* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-apl: PASS -> FAIL [fdo#104894]
- shard-kbl: PASS -> FAIL [fdo#104894]

* igt@perf_pmu@semaphore-wait-idle-vcs0:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] +21

#### Possible fixes ####

* igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
- shard-apl: FAIL [fdo#109660] -> PASS

* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
- shard-snb: DMESG-WARN [fdo#107956] -> PASS

* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS

* igt@kms_color@pipe-a-degamma:
- shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS

* igt@kms_color@pipe-c-ctm-max:
- shard-kbl: FAIL [fdo#108147] -> PASS
- shard-apl: FAIL [fdo#108147] -> PASS

* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-kbl: FAIL [fdo#103232] -> PASS +1

* igt@kms_cursor_crc@cursor-64x21-offscreen:
- shard-hsw: INCOMPLETE [fdo#103540] -> PASS

* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1

* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS

* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: FAIL [fdo#105767] -> PASS

* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: FAIL [fdo#104873] -> PASS

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-glk: FAIL [fdo#103167] -> PASS +6
- shard-kbl: FAIL [fdo#103167] -> PASS +1

* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: FAIL [fdo#103166] -> PASS +2
- shard-glk: FAIL [fdo#103166] -> PASS

* igt@kms_setmode@basic:
- shard-kbl: FAIL [fdo#99912] -> PASS

* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: FAIL [fdo#104894] -> PASS
- shard-apl: FAIL [fdo#104894] -> PASS

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (6 -> 5)
------------------------------

Missing (1): shard-skl

Build changes
-------------

* IGT: IGT_4870 -> IGTPW_2552
* Piglit: piglit_4509 -> None

== Logs ==

Chris Wilson

2019-03-05 15:31 UTC #7 lore raw

In reply to Dale B Stimson

Quoting Dale B Stimson (2019-03-05 01:03:06)

Quoted 20 lines

V4:
I have tested these changes on both SKL and ICL with no regressions detected.
I will note that both SKL and ICL seem to currently have (at least for my environment) suspend/resume issues which occur with or without these changes (and also for gem_exec_suspend). Therefore, the S3/S4 tests were not done.
Testing on ICL shows that Gen11 requires BB_OFFSET .ignore_bits = 0x7 instead of 0x4. I presume that the preferred way to do this is to change the existing table entry for BB_OFFSET instead of splitting it into separate entries for GEN8-10 and GEN11.
For those registers that are force_nonpriv for some Gen levels and not for others, I have chosen to show the two states as separate table entries to make this clear. In particular, this applies as shown below. Any objections to doing it that way?

Review

Quoted 10 lines

(quoted diff) +6 -2

+       { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
+       { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
+       { "HDC_CHICKEN1", GEN_RANGE(10, 10), RCS0, 0x7304, .masked = true },
+
        /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
-       { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
+       { "CTX_PREEMPT", NOCTX /* GEN9 */, RCS0, 0x2248 },
        { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580, .masked = true },
-       { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304, .masked = true },
+       { "HDC_CHICKEN1", GEN_RANGE(9, 9), RCS0, 0x7304, .masked = true },

Looks clear enough; a few more gen and we'll have a better picture and maybe a better method for retrieving the register db. -Chris
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