coresight: etm4x: Add support to skip trace unit power up
Subsystems (4)
v3 cover coresight: etm4x: Add support to skip trace unit power up
This series adds support to skip powering up of trace unit on systems with an errata which stops CPU watchdog counter when power up bit is set (TRCPDCR.PU = 1). Setting this bit is not required on Qualcomm Technologies Inc. chipsets where this errata exists since the ETMs are in the same power domain as their respective CPU cores.
Changes since v2:
* Fix checkpatch warning for 80 characters.
Changes since v1:
* Use qcom,skip-power-up for naming as suggested by Mathieu.
* Have check for DT property in initialization as per Mathieu.
* Reword description for property as per Mathieu.
* Split up dt-binding patch as checkpatch complains.
Tingwei Zhang (2):
coresight: etm4x: Add support to skip trace unit power up
dt-bindings: arm: coresight: Add support to skip trace unit power up
.../devicetree/bindings/arm/coresight.txt | 7 +++++ drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ 3 files changed, 27 insertions(+), 10 deletions(-)
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v3 1/2 coresight: etm4x: Add support to skip trace unit power up
From: Tingwei Zhang <[email protected]>
On some Qualcomm Technologies Inc. SoCs like SC7180, there exists a hardware errata where the APSS (Application Processor SubSystem)/CPU watchdog counter is stopped when the trace unit power up ETM register is set (TRCPDCR.PU = 1). Since the ETMs share the same power domain as that of respective CPU cores, they are powered on when the CPU core is powered on. So we can skip powering up of trace unit after checking for this errata via new property called "qcom,skip-power-up".
--- drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ 2 files changed, 20 insertions(+), 10 deletions(-)
drivers/hwtracing/coresight/coresight-etm4x.c +17 -10
@@ -196,12 +196,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)writel_relaxed (config->vmid_mask0, drvdata->base +TRCVMIDCCTLR0 );writel_relaxed (config->vmid_mask1, drvdata->base +TRCVMIDCCTLR1 ); -/* -* Request to keep the trace unit powered and also -* emulation of powerdown -*/ -writel_relaxed (readl_relaxed (drvdata->base +TRCPDCR ) |TRCPDCR_PU , - drvdata->base +TRCPDCR ); +if (!drvdata->skip_power_up) { +/* +* Request to keep the trace unit powered and also +* emulation of powerdown +*/ +writel_relaxed (readl_relaxed (drvdata->base +TRCPDCR ) | +TRCPDCR_PU , drvdata->base +TRCPDCR ); + }/* Enable the trace unit */ writel_relaxed (1 , drvdata->base +TRCPRGCTLR );
@@ -476,10 +478,12 @@ static void etm4_disable_hw(void *info)CS_UNLOCK (drvdata->base); -/* power can be removed from the trace unit now */ - control =readl_relaxed (drvdata->base +TRCPDCR ); - control &= ~TRCPDCR_PU ; -writel_relaxed (control, drvdata->base +TRCPDCR ); +if (!drvdata->skip_power_up) { +/* power can be removed from the trace unit now */ + control =readl_relaxed (drvdata->base +TRCPDCR ); + control &= ~TRCPDCR_PU ; +writel_relaxed (control, drvdata->base +TRCPDCR ); + } control =readl_relaxed (drvdata->base +TRCPRGCTLR );
@@ -1429,6 +1433,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)return -ENOMEM ; } +if (fwnode_property_present (dev_fwnode (dev),"qcom,skip-power-up" )) + drvdata->skip_power_up = true; +/* Validity for the resource is already checked by the AMBA core */ base =devm_ioremap_resource (dev, res);if (IS_ERR (base))
drivers/hwtracing/coresight/coresight-etm4x.h +3 -0
@@ -407,6 +407,8 @@ struct etmv4_save_state {* @config: structure holding configuration parameters. * @save_state: State to be preserved across power loss * @state_needs_restore: True when there is context to restore after PM exit +* @skip_power_up: Indicates if an implementation can skip powering up +* the trace unit. */ struct etmv4_drvdata {void __iomem *base;
@@ -454,6 +456,7 @@ struct etmv4_drvdata {struct etmv4_config config;struct etmv4_save_state *save_state;bool state_needs_restore; +bool skip_power_up; };/* Address comparator access types */
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v3 2/2 dt-bindings: arm: coresight: Add support to skip trace unit power up
In reply to Sai Prakash RanjanFrom: Tingwei Zhang <[email protected]>
Add "qcom,skip-power-up" property to identify systems which can skip powering up of trace unit since they share the same power domain as their CPU core. This is required to identify such systems with hardware errata which stops the CPU watchdog counter when the power up bit is set (TRCPDCR.PU).
--- Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++ 1 file changed, 7 insertions(+)
Documentation/devicetree/bindings/arm/coresight.txt +7 -0
@@ -108,6 +108,13 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. + * qcom,skip-power-up: boolean. Indicates that an implementation can + skip powering up the trace unit. TRCPDCR.PU does not have to be set + on Qualcomm Technologies Inc. systems since ETMs are in the same power + domain as their CPU cores. This property is required to identify such + systems with hardware errata where the CPU watchdog counter is stopped + when TRCPDCR.PU is set. + * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv3 2/2] dt-bindings: arm: coresight: Add support to skip trace unit power up
Quoted 22 lines · Sai Prakash Ranjan
From: Tingwei Zhang <[email protected]>
Add "qcom,skip-power-up" property to identify systems which can skip powering up of trace unit since they share the same power domain as their CPU core. This is required to identify such systems with hardware errata which stops the CPU watchdog counter when the power up bit is set (TRCPDCR.PU).
Signed-off-by Tingwei Zhang <[email protected]>Co-developed-by Sai Prakash Ranjan <[email protected]>Signed-off-by Sai Prakash Ranjan <[email protected]>--- Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++ 1 file changed, 7 insertions(+)Documentation/devicetree/bindings/arm/coresight.txt +0
-0@@ -108,6 +108,13 @@ its hardware characteristcs. * arm,cp14: must be present if the system accesses ETM/PTM management
Documentation/devicetree/bindings/arm/coresight.txt its hardware characteristcs. · line 118
Quoted 10 lines
Documentation/devicetree/bindings/arm/coresight.txt +7
-0registers via co-processor 14. + * qcom,skip-power-up: boolean. Indicates that an implementation can + skip powering up the trace unit. TRCPDCR.PU does not have to be set + on Qualcomm Technologies Inc. systems since ETMs are in the same power + domain as their CPU cores. This property is required to identify such + systems with hardware errata where the CPU watchdog counter is stopped + when TRCPDCR.PU is set. + * Optional property for TMC:
Quoted 5 lines
Documentation/devicetree/bindings/arm/coresight.txt +0
-1* arm,buffer-size: size of contiguous buffer space for TMC ETR --QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCHv3 2/2] dt-bindings: arm: coresight: Add support to skip trace unit power up
In reply to Sai Prakash RanjanQuoted 8 lines · Sai Prakash Ranjan
From: Tingwei Zhang <[email protected]>
Add "qcom,skip-power-up" property to identify systems which can skip powering up of trace unit since they share the same power domain as their CPU core. This is required to identify such systems with hardware errata which stops the CPU watchdog counter when the power up bit is set (TRCPDCR.PU).
Quoted 7 lines
Signed-off-by Tingwei Zhang <[email protected]>Co-developed-by Sai Prakash Ranjan <[email protected]>Signed-off-by Sai Prakash Ranjan <[email protected]>--- Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++ 1 file changed, 7 insertions(+)