Allwinner A100 Initial support
Subsystems (14)
v5 cover Allwinner A100 Initial support
This patch set adds initial support for allwinner a100 soc, which is a 64-bit tablet chip.
v5:
-Drop redundant SOB for thermal series patch
-Trival a100 dtsi fix
v4:
-Drop "dt-bindings: pinctrl: sunxi: make gpio banks supplies required" -Fix dcdc1 regulator name
-Get rid of underscore in dts node name
-Some trivial things in yaml files
v3:
-Add pmu and nmi support
-Add read data mask for calibration
-Code style
-Some trivial things in yaml files
v2:
-Some naming consistency
-Repair email address
-Fix mmc clock
-Don't export system clock
-Fix checkpatch warning
-Drop unneeded pin function, convert to jtag_gpu and i2s_x
Yangtao Li (16):
dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and
R-CCU
clk: sunxi-ng: add support for the Allwinner A100 CCU
dt-bindings: pinctrl: sunxi: Get rid of continual nesting
dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
pinctrl: sunxi: add support for the Allwinner A100 pin controller
dt-bindings: nvmem: SID: add binding for A100's SID controller
dt-bindings: thermal: sun8i: Add binding for A100's THS controller
thermal: sun8i: add TEMP_CALIB_MASK for calibration data in
sun50i_h6_ths_calibrate
thermal: sun8i: Add A100's THS controller support
mfd: axp20x: Allow the AXP803 to be probed by I2C
dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.
arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
arm64: allwinner: A100: add support for Allwinner Perf1 board
.../devicetree/bindings/arm/sunxi.yaml | 5 + .../clock/allwinner,sun4i-a10-ccu.yaml | 7 +- .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 3 + .../allwinner,sun7i-a20-sc-nmi.yaml | 5 +- .../nvmem/allwinner,sun4i-a10-sid.yaml | 19 +- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 139 +- .../thermal/allwinner,sun8i-a83t-ths.yaml | 6 +- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun50i-a100-allwinner-perf1.dts | 180 +++ .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 +++++ drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 214 +++ drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 21 + drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 1276 +++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-a100.h | 56 + drivers/mfd/axp20x-i2c.c | 2 + drivers/pinctrl/sunxi/Kconfig | 10 + drivers/pinctrl/sunxi/Makefile | 2 + drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 ++ drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 +++++++++ drivers/thermal/sun8i_thermal.c | 16 +- include/dt-bindings/clock/sun50i-a100-ccu.h | 116 ++ include/dt-bindings/clock/sun50i-a100-r-ccu.h | 23 + include/dt-bindings/reset/sun50i-a100-ccu.h | 68 + include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 + 26 files changed, 3308 insertions(+), 68 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h
Signature · 1 line
2.24.0
PATCH v5 1/16 dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
From: Yangtao Li <[email protected]>
This patch adds binding to a100's ccu clock and r-ccu clock.
--- .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +6 -1
@@ -36,6 +36,8 @@ properties: - allwinner,sun9i-a80-ccu - allwinner,sun50i-a64-ccu - allwinner,sun50i-a64-r-ccu + - allwinner,sun50i-a100-ccu + - allwinner,sun50i-a100-r-ccu - allwinner,sun50i-h5-ccu - allwinner,sun50i-h6-ccu - allwinner,sun50i-h6-r-ccu
@@ -78,6 +80,7 @@ if: - allwinner,sun8i-a83t-r-ccu - allwinner,sun8i-h3-r-ccu - allwinner,sun50i-a64-r-ccu + - allwinner,sun50i-a100-r-ccu - allwinner,sun50i-h6-r-ccu then:
@@ -94,7 +97,9 @@ else: if: properties: compatible: - const: allwinner,sun50i-h6-ccu + enum: + - allwinner,sun50i-a100-ccu + - allwinner,sun50i-h6-ccu then: properties:
Signature · 1 line
2.24.0
Maxime Ripard
AppliedRe: [PATCH v5 01/16] dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
Quoted 6 lines · Frank Lee
From: Yangtao Li <[email protected]>
This patch adds binding to a100's ccu clock and r-ccu clock.
Signed-off-by Yangtao Li <[email protected]>Reviewed-by Rob Herring <[email protected]>
Applied, thanks!
Maxime
PATCH v5 2/16 clk: sunxi-ng: add support for the Allwinner A100 CCU
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Add support for a100 in the sunxi-ng CCU framework.
--- drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 214 +++ drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 21 + drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 1276 +++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-a100.h | 56 + include/dt-bindings/clock/sun50i-a100-ccu.h | 116 ++ include/dt-bindings/clock/sun50i-a100-r-ccu.h | 23 + include/dt-bindings/reset/sun50i-a100-ccu.h | 68 + include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 + 10 files changed, 1804 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h
drivers/clk/sunxi-ng/Kconfig +10 -0
@@ -17,6 +17,16 @@ config SUN50I_A64_CCU default ARM64 && ARCH_SUNXI depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST +config SUN50I_A100_CCU + bool "Support for the Allwinner A100 CCU" + default ARM64 && ARCH_SUNXI + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST + +config SUN50I_A100_R_CCU + bool "Support for the Allwinner A100 PRCM CCU" + default ARM64 && ARCH_SUNXI + depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST + config SUN50I_H6_CCU bool "Support for the Allwinner H6 CCU" default ARM64 && ARCH_SUNXI
drivers/clk/sunxi-ng/Makefile +2 -0
@@ -23,6 +23,8 @@ obj-y += ccu_mp.o # SoC support obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o +obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o +obj-$(CONFIG_SUN50I_A100_R_CCU) += ccu-sun50i-a100-r.o obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c new file +214 -0
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drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h new file +21 -0
@@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2020 Yangtao Li <[email protected]> +*/ + +#ifndef _CCU_SUN50I_A100_R_H +#define _CCU_SUN50I_A100_R_H + +#include <dt-bindings/clock/sun50i-a100-r-ccu.h> +#include <dt-bindings/reset/sun50i-a100-r-ccu.h> + +#define CLK_R_CPUS 0 +#define CLK_R_AHB 1 + +/* exported except APB1 for R_PIO */ + +#define CLK_R_APB2 3 + +#define CLK_NUMBER (CLK_R_AHB_BUS_RTC + 1) + +#endif /* _CCU_SUN50I_A100_R_H */
drivers/clk/sunxi-ng/ccu-sun50i-a100.c new file +1276 -0
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drivers/clk/sunxi-ng/ccu-sun50i-a100.h new file +56 -0
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include/dt-bindings/clock/sun50i-a100-ccu.h new file +116 -0
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include/dt-bindings/clock/sun50i-a100-r-ccu.h new file +23 -0
@@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2020 Yangtao Li <[email protected]> +*/ + +#ifndef _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ + +#define CLK_R_APB1 2 + +#define CLK_R_APB1_TIMER 4 +#define CLK_R_APB1_TWD 5 +#define CLK_R_APB1_PWM 6 +#define CLK_R_APB1_BUS_PWM 7 +#define CLK_R_APB1_PPU 8 +#define CLK_R_APB2_UART 9 +#define CLK_R_APB2_I2C0 10 +#define CLK_R_APB2_I2C1 11 +#define CLK_R_APB1_IR 12 +#define CLK_R_APB1_BUS_IR 13 +#define CLK_R_AHB_BUS_RTC 14 + +#endif /* _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ */
include/dt-bindings/reset/sun50i-a100-ccu.h new file +68 -0
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include/dt-bindings/reset/sun50i-a100-r-ccu.h new file +18 -0
@@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* +* Copyright (c) 2020 Yangtao Li <[email protected]> +*/ + +#ifndef _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ + +#define RST_R_APB1_TIMER 0 +#define RST_R_APB1_BUS_PWM 1 +#define RST_R_APB1_PPU 2 +#define RST_R_APB2_UART 3 +#define RST_R_APB2_I2C0 4 +#define RST_R_APB2_I2C1 5 +#define RST_R_APB1_BUS_IR 6 +#define RST_R_AHB_BUS_RTC 7 + +#endif /* _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ */
Signature · 1 line
2.24.0
Re: [PATCH v5 02/16] clk: sunxi-ng: add support for the Allwinner A100 CCU
Quoted 17 lines · Frank Lee
From: Yangtao Li <[email protected]>
Add support for a100 in the sunxi-ng CCU framework.
Signed-off-by Yangtao Li <[email protected]>--- drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 214 +++ drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h | 21 + drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 1276 +++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun50i-a100.h | 56 + include/dt-bindings/clock/sun50i-a100-ccu.h | 116 ++ include/dt-bindings/clock/sun50i-a100-r-ccu.h | 23 + include/dt-bindings/reset/sun50i-a100-ccu.h | 68 + include/dt-bindings/reset/sun50i-a100-r-ccu.h | 18 + 10 files changed, 1804 insertions(+)
Quoted 9 lines
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.h create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a100.h create mode 100644 include/dt-bindings/clock/sun50i-a100-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-a100-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a100-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-a100-r-ccu.h
Maxime Ripard
AppliedRe: [PATCH v5 02/16] clk: sunxi-ng: add support for the Allwinner A100 CCU
In reply to Frank LeeQuoted 5 lines · Frank Lee
From: Yangtao Li <[email protected]>
Add support for a100 in the sunxi-ng CCU framework.
Signed-off-by Yangtao Li <[email protected]>
Applied, thanks!
Maxime
PATCH v5 3/16 dt-bindings: pinctrl: sunxi: Get rid of continual nesting
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Rather than a continual nesting of 'else' clauses, just make each 'if' a new entry under 'allOf' and get rid of the else.
--- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 124 ++++++++++-------- 1 file changed, 68 insertions(+), 56 deletions(-)
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +68 -56
@@ -155,62 +155,74 @@ allOf: minItems: 5 maxItems: 5 - else: - if: - properties: - compatible: - enum: - - allwinner,sun6i-a31-pinctrl - - allwinner,sun6i-a31s-pinctrl - - allwinner,sun50i-h6-pinctrl - - then: - properties: - interrupts: - minItems: 4 - maxItems: 4 - - else: - if: - properties: - compatible: - enum: - - allwinner,sun8i-a23-pinctrl - - allwinner,sun8i-a83t-pinctrl - - allwinner,sun50i-a64-pinctrl - - allwinner,sun50i-h5-pinctrl - - allwinner,suniv-f1c100s-pinctrl - - then: - properties: - interrupts: - minItems: 3 - maxItems: 3 - - else: - if: - properties: - compatible: - enum: - - allwinner,sun6i-a31-r-pinctrl - - allwinner,sun8i-a33-pinctrl - - allwinner,sun8i-h3-pinctrl - - allwinner,sun8i-v3-pinctrl - - allwinner,sun8i-v3s-pinctrl - - allwinner,sun9i-a80-r-pinctrl - - allwinner,sun50i-h6-r-pinctrl - - then: - properties: - interrupts: - minItems: 2 - maxItems: 2 - - else: - properties: - interrupts: - minItems: 1 - maxItems: 1 + - if: + properties: + compatible: + enum: + - allwinner,sun6i-a31-pinctrl + - allwinner,sun6i-a31s-pinctrl + - allwinner,sun50i-h6-pinctrl + + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + + - if: + properties: + compatible: + enum: + - allwinner,sun8i-a23-pinctrl + - allwinner,sun8i-a83t-pinctrl + - allwinner,sun50i-a64-pinctrl + - allwinner,sun50i-h5-pinctrl + - allwinner,suniv-f1c100s-pinctrl + + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 + + - if: + properties: + compatible: + enum: + - allwinner,sun6i-a31-r-pinctrl + - allwinner,sun8i-a33-pinctrl + - allwinner,sun8i-h3-pinctrl + - allwinner,sun8i-v3-pinctrl + - allwinner,sun8i-v3s-pinctrl + - allwinner,sun9i-a80-r-pinctrl + - allwinner,sun50i-h6-r-pinctrl + + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + enum: + - allwinner,sun4i-a10-pinctrl + - allwinner,sun5i-a10s-pinctrl + - allwinner,sun5i-a13-pinctrl + - allwinner,sun7i-a20-pinctrl + - allwinner,sun8i-a23-r-pinctrl + - allwinner,sun8i-a83t-r-pinctrl + - allwinner,sun8i-h3-r-pinctrl + - allwinner,sun8i-r40-pinctrl + - allwinner,sun50i-a64-r-pinctrl + - nextthing,gr8-pinctrl + + then: + properties: + interrupts: + minItems: 1 + maxItems: 1 additionalProperties: false
Signature · 1 line
2.24.0
Re: [PATCH v5 03/16] dt-bindings: pinctrl: sunxi: Get rid of continual nesting
Quoted 7 lines · Frank Lee
From: Yangtao Li <[email protected]>
Rather than a continual nesting of 'else' clauses, just make each 'if' a new entry under 'allOf' and get rid of the else.
Signed-off-by Yangtao Li <[email protected]>Reviewed-by Rob Herring <[email protected]>
Thanks!
Maxime
PATCH v5 4/16 dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Add device tree binding Documentation details for A100 pinctrl driver, which has a r pin controller and a pin controller with more irq lines.
--- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +15 -0
@@ -48,6 +48,8 @@ properties: - allwinner,sun9i-a80-r-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-pinctrl + - allwinner,sun50i-a100-r-pinctrl - allwinner,sun50i-h5-pinctrl - allwinner,sun50i-h6-pinctrl - allwinner,sun50i-h6-r-pinctrl
@@ -143,6 +145,18 @@ allOf: # boards are defining it at the moment so it would generate a lot of # warnings. + - if: + properties: + compatible: + enum: + - allwinner,sun50i-a100-pinctrl + + then: + properties: + interrupts: + minItems: 7 + maxItems: 7 + - if: properties: compatible:
@@ -216,6 +230,7 @@ allOf: - allwinner,sun8i-h3-r-pinctrl - allwinner,sun8i-r40-pinctrl - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-r-pinctrl - nextthing,gr8-pinctrl then:
Signature · 1 line
2.24.0
Re: [PATCH v5 04/16] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
Quoted 7 lines · Frank Lee
From: Yangtao Li <[email protected]>
Add device tree binding Documentation details for A100 pinctrl driver, which has a r pin controller and a pin controller with more irq lines.
Signed-off-by Yangtao Li <[email protected]>Reviewed-by Rob Herring <[email protected]>
Thanks!
Maxime
PATCH v5 5/16 pinctrl: sunxi: add support for the Allwinner A100 pin controller
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
This commit introduces support for the pin controller on A100.
--- drivers/pinctrl/sunxi/Kconfig | 10 + drivers/pinctrl/sunxi/Makefile | 2 + drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 +++ drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 ++++++++++++++++++ 4 files changed, 825 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c
drivers/pinctrl/sunxi/Kconfig +10 -0
@@ -94,6 +94,16 @@ config PINCTRL_SUN50I_A64_R default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN50I_A100 + bool "Support for the Allwinner A100 PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + +config PINCTRL_SUN50I_A100_R + bool "Support for the Allwinner A100 R-PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + config PINCTRL_SUN50I_H5 bool "Support for the Allwinner H5 PIO" default ARM64 && ARCH_SUNXI
drivers/pinctrl/sunxi/Makefile +2 -0
@@ -13,6 +13,8 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o +obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o +obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c new file +105 -0
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drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c new file +708 -0
708 lines not on this page · raw message
Signature · 1 line
2.24.0
Re: [PATCH v5 05/16] pinctrl: sunxi: add support for the Allwinner A100 pin controller
Quoted 5 lines · Frank Lee
From: Yangtao Li <[email protected]>
This commit introduces support for the pin controller on A100.
Signed-off-by Yangtao Li <[email protected]>
Thanks!
Maxime
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PATCH v5 6/16 dt-bindings: nvmem: SID: add binding for A100's SID controller
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Add a binding for A100's SID controller.
--- .../nvmem/allwinner,sun4i-a10-sid.yaml | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-)
Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml +11 -8
@@ -15,14 +15,17 @@ allOf: properties: compatible: - enum: - - allwinner,sun4i-a10-sid - - allwinner,sun7i-a20-sid - - allwinner,sun8i-a83t-sid - - allwinner,sun8i-h3-sid - - allwinner,sun50i-a64-sid - - allwinner,sun50i-h5-sid - - allwinner,sun50i-h6-sid + oneOf: + - const: allwinner,sun4i-a10-sid + - const: allwinner,sun7i-a20-sid + - const: allwinner,sun8i-a83t-sid + - const: allwinner,sun8i-h3-sid + - const: allwinner,sun50i-a64-sid + - items: + - const: allwinner,sun50i-a100-sid + - const: allwinner,sun50i-a64-sid + - const: allwinner,sun50i-h5-sid + - const: allwinner,sun50i-h6-sid reg: maxItems: 1
Signature · 1 line
2.24.0
PATCH v5 7/16 dt-bindings: thermal: sun8i: Add binding for A100's THS controller
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Add a binding for A100's ths controller.
--- .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml +5 -1
@@ -17,6 +17,7 @@ properties: - allwinner,sun8i-h3-ths - allwinner,sun8i-r40-ths - allwinner,sun50i-a64-ths + - allwinner,sun50i-a100-ths - allwinner,sun50i-h5-ths - allwinner,sun50i-h6-ths
@@ -61,7 +62,9 @@ allOf: properties: compatible: contains: - const: allwinner,sun50i-h6-ths + enum: + - allwinner,sun50i-a100-ths + - allwinner,sun50i-h6-ths then: properties:
@@ -103,6 +106,7 @@ allOf: - const: allwinner,sun8i-h3-ths - const: allwinner,sun8i-r40-ths - const: allwinner,sun50i-a64-ths + - const: allwinner,sun50i-a100-ths - const: allwinner,sun50i-h5-ths - const: allwinner,sun50i-h6-ths
Signature · 1 line
2.24.0
Re: [PATCH v5 07/16] dt-bindings: thermal: sun8i: Add binding for A100's THS controller
Quoted 6 lines · Frank Lee
From: Yangtao Li <[email protected]>
Add a binding for A100's ths controller.
Signed-off-by Yangtao Li <[email protected]>Reviewed-by Rob Herring <[email protected]>
Thanks!
Maxime
PATCH v5 8/16 thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
For sun50i_h6_ths_calibrate(), the data read from nvmem needs a round of calculation. On the other hand, the newer SOC may store other data in the space other than 12bit sensor data. Add mask operation to read data to avoid conversion error.
--- drivers/thermal/sun8i_thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/thermal/sun8i_thermal.c +1 -1
@@ -244,7 +244,7 @@ static int sun50i_h6_ths_calibrate(struct ths_device *tmdev, ft_temp = (caldata[0 ] &FT_TEMP_MASK ) *100 ;for (i =0 ; i < tmdev->chip->sensor_num; i++) { -int sensor_reg = caldata[i +1 ]; +int sensor_reg = caldata[i +1 ] &TEMP_CALIB_MASK ;int cdata, offset;int sensor_temp = tmdev->chip->calc_temp (tmdev, i, sensor_reg);
Signature · 1 line
2.24.0
Re: [PATCH v5 08/16] thermal: sun8i: add TEMP_CALIB_MASK for calibration data in sun50i_h6_ths_calibrate
Quoted 8 lines · Frank Lee
From: Yangtao Li <[email protected]>
For
sun50i_h6_ths_calibrate(), the data read from nvmem needs a round of calculation. On the other hand, the newer SOC may store other data in the space other than 12bit sensor data. Add mask operation to read data to avoid conversion error.Signed-off-by Yangtao Li <[email protected]>
Maxime
PATCH v5 9/16 thermal: sun8i: Add A100's THS controller support
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
This patch add thermal sensor controller support for A100, which is similar to the previous ones.
--- drivers/thermal/sun8i_thermal.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
drivers/thermal/sun8i_thermal.c +14 -0
@@ -590,6 +590,19 @@ static const struct ths_thermal_chip sun50i_a64_ths = { .calc_temp = sun8i_ths_calc_temp, }; +static const struct ths_thermal_chip sun50i_a100_ths = { + .sensor_num =3 , + .has_bus_clk_reset = true, + .ft_deviation =8000 , + .offset =187744 , + .scale =672 , + .temp_data_base =SUN50I_H6_THS_TEMP_DATA , + .calibrate = sun50i_h6_ths_calibrate, + .init = sun50i_h6_thermal_init, + .irq_ack = sun50i_h6_irq_ack, + .calc_temp = sun8i_ths_calc_temp, +}; +static const struct ths_thermal_chip sun50i_h5_ths = { .sensor_num =2 , .has_mod_clk = true,
@@ -619,6 +632,7 @@ static const struct of_device_id of_ths_match[] = { { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths }, { .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths }, { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths }, + { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths }, { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths }, { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths }, { /* sentinel */ },
Signature · 1 line
2.24.0
Re: [PATCH v5 09/16] thermal: sun8i: Add A100's THS controller support
Quoted 6 lines · Frank Lee
From: Yangtao Li <[email protected]>
This patch add thermal sensor controller support for A100, which is similar to the previous ones.
Signed-off-by Yangtao Li <[email protected]>
Thanks!
Maxime
PATCH v5 10/16 mfd: axp20x: Allow the AXP803 to be probed by I2C
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
The AXP803 can be used both using the RSB proprietary bus, or a more traditional I2C bus.
Let's add that possibility.
--- drivers/mfd/axp20x-i2c.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/mfd/axp20x-i2c.c +2 -0
@@ -63,6 +63,7 @@ static const struct of_device_id axp20x_i2c_of_match[] = { { .compatible = "x-powers,axp209", .data = (void *)AXP209_ID }, { .compatible = "x-powers,axp221", .data = (void *)AXP221_ID }, { .compatible = "x-powers,axp223", .data = (void *)AXP223_ID }, + { .compatible = "x-powers,axp803", .data = (void *)AXP803_ID }, { .compatible = "x-powers,axp806", .data = (void *)AXP806_ID }, { }, };
@@ -74,6 +75,7 @@ static const struct i2c_device_id axp20x_i2c_id[] = { { "axp209", 0 }, { "axp221", 0 }, { "axp223", 0 }, + { "axp803", 0 }, { "axp806", 0 }, { }, };
Signature · 1 line
2.24.0
Re: [PATCH v5 10/16] mfd: axp20x: Allow the AXP803 to be probed by I2C
Quoted 5 lines · Frank Lee
From: Yangtao Li <[email protected]>
The AXP803 can be used both using the RSB proprietary bus, or a more traditional I2C bus.
Quoted 7 lines
Let's add that possibility.
Signed-off-by Yangtao Li <[email protected]>Acked-by Chen-Yu Tsai <[email protected]>--- drivers/mfd/axp20x-i2c.c | 2 ++ 1 file changed, 2 insertions(+)
Why do you keep sending this?
It was applied in v3 [0].
[0] https://lkml.org/lkml/2020/7/16/745
Signature · 4 lines
Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
PATCH v5 11/16 dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
There is no one use "allwinner,sun9i-a80-sc-nmi". The A80 uses "allwinner,sun9i-a80-nmi".
Let's fix it.
--- .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +1 -1
@@ -29,7 +29,7 @@ properties: - items: - const: allwinner,sun8i-a83t-r-intc - const: allwinner,sun6i-a31-r-intc - - const: allwinner,sun9i-a80-sc-nmi + - const: allwinner,sun9i-a80-nmi - items: - const: allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc
Signature · 1 line
2.24.0
Maxime Ripard
AppliedRe: [PATCH v5 11/16] dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
Quoted 9 lines · Frank Lee
From: Yangtao Li <[email protected]>
There is no one use "allwinner,sun9i-a80-sc-nmi". The A80 uses "allwinner,sun9i-a80-nmi".
Let's fix it.
Signed-off-by Yangtao Li <[email protected]>Acked-by Rob Herring <[email protected]>
Applied, thanks!
Maxime
PATCH v5 12/16 dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Add a binding for A100's nmi controller.
--- .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 3 +++ 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +3 -0
@@ -33,6 +33,9 @@ properties: - items: - const: allwinner,sun50i-a64-r-intc - const: allwinner,sun6i-a31-r-intc + - items: + - const: allwinner,sun50i-a100-nmi + - const: allwinner,sun9i-a80-nmi - items: - const: allwinner,sun50i-h6-r-intc - const: allwinner,sun6i-a31-r-intc
Signature · 1 line
2.24.0
Maxime Ripard
AppliedRe: [PATCH v5 12/16] dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
Quoted 6 lines · Frank Lee
From: Yangtao Li <[email protected]>
Add a binding for A100's nmi controller.
Signed-off-by Yangtao Li <[email protected]>Acked-by Rob Herring <[email protected]>
Applied, thanks!
Maxime
PATCH v5 13/16 dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Allwinner A100 have a mv64xxx i2c interface available to be used.
--- Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml | 3 +++ 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +3 -0
@@ -26,6 +26,9 @@ properties: - items: - const: allwinner,sun50i-a64-i2c - const: allwinner,sun6i-a31-i2c + - items: + - const: allwinner,sun50i-a100-i2c + - const: allwinner,sun6i-a31-i2c - items: - const: allwinner,sun50i-h6-i2c - const: allwinner,sun6i-a31-i2c
Signature · 1 line
2.24.0
Re: [PATCH v5 13/16] dt-bindings: i2c: mv64xxx: Add compatible for the A100 i2c node.
Quoted 6 lines · Frank Lee
From: Yangtao Li <[email protected]>
Allwinner A100 have a mv64xxx i2c interface available to be used.
Signed-off-by Yangtao Li <[email protected]>Reviewed-by Rob Herring <[email protected]>
For the record, this got upstream during the 5.9 merge window. I seem to have forgotten to send a mail that this patch got applied. Sorry!
PATCH v5 14/16 arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds the basical DTSI file of it, including the clock, i2c, pins, sid, ths, nmi, and UART support.
--- .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 364 ++++++++++++++++++ 1 file changed, 364 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi new file +364 -0
@@ -0,0 +1,364 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (c) 2020 Yangtao Li <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun50i-a100-ccu.h> +#include <dt-bindings/clock/sun50i-a100-r-ccu.h> +#include <dt-bindings/reset/sun50i-a100-ccu.h> +#include <dt-bindings/reset/sun50i-a100-r-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + dcxo24M: dcxo24M-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "dcxo24M"; + #clock-cells = <0>; + }; + + iosc: internal-osc-clk { + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + #clock-cells = <0>; + }; + + osc32k: osc32k-clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x3fffffff>; + + ccu: clock@3001000 { + compatible = "allwinner,sun50i-a100-ccu"; + reg = <0x03001000 0x1000>; + clocks = <&dcxo24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, <0x03022000 0x2000>, + <0x03024000 0x2000>, <0x03026000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + efuse@3006000 { + compatible = "allwinner,sun50i-a100-sid", + "allwinner,sun50i-a64-sid"; + reg = <0x03006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: calib@14 { + reg = <0x14 8>; + }; + }; + + pio: pinctrl@300b000 { + compatible = "allwinner,sun50i-a100-pinctrl"; + reg = <0x0300b000 0x400>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB9", "PB10"; + function = "uart0"; + }; + }; + + uart0: serial@5000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@5000400 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@5000800 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@5000c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x05000c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@5001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x05001000 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + i2c0: i2c@5002000 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@5002400 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002400 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@5002800 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002800 0x400>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@5002c00 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002c00 0x400>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ths: thermal-sensor@5070400 { + compatible = "allwinner,sun50i-a100-ths"; + reg = <0x05070400 0x100>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + + r_ccu: clock@7010000 { + compatible = "allwinner,sun50i-a100-r-ccu"; + reg = <0x07010000 0x300>; + clocks = <&dcxo24M>, <&osc32k>, <&iosc>, + <&ccu CLK_PLL_PERIPH0>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + r_intc: interrupt-controller@7010320 { + compatible = "allwinner,sun50i-a100-nmi", + "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x07010320 0xc>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun50i-a100-r-pinctrl"; + reg = <0x07022000 0x400>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c0_pins: r-i2c0-pins { + pins = "PL0", "PL1"; + function = "s_i2c0"; + }; + + r_i2c1_pins: r-i2c1-pins { + pins = "PL8", "PL9"; + function = "s_i2c1"; + }; + }; + + r_uart: serial@7080000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07080000 0x400>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_R_APB2_UART>; + resets = <&r_ccu RST_R_APB2_UART>; + status = "disabled"; + }; + + r_i2c0: i2c@7081400 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x07081400 0x400>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB2_I2C0>; + resets = <&r_ccu RST_R_APB2_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_i2c1: i2c@7081800 { + compatible = "allwinner,sun50i-a100-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x07081800 0x400>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB2_I2C1>; + resets = <&r_ccu RST_R_APB2_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + thermal-zones { + cpu-thermal-zone { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + ddr-thermal-zone { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; + + gpu-thermal-zone { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + }; +};
Signature · 1 line
2.24.0
Maxime Ripard
AppliedRe: [PATCH v5 14/16] arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
Quoted 7 lines · Frank Lee
From: Yangtao Li <[email protected]>
Allwinner A100 is a new SoC with Cortex-A53 cores, this commit adds the basical DTSI file of it, including the clock, i2c, pins, sid, ths, nmi, and UART support.
Signed-off-by Yangtao Li <[email protected]>
Applied, thanks!
Maxime
PATCH v5 15/16 dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
Document board compatible names for Allwinner A100 Perf1 Board.
--- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/arm/sunxi.yaml +5 -0
@@ -16,6 +16,11 @@ properties: compatible: oneOf: + - description: Allwinner A100 Perf1 Board + items: + - const: allwinner,a100-perf1 + - const: allwinner,sun50i-a100 + - description: Allwinner A23 Evaluation Board items: - const: allwinner,sun8i-a23-evb
Signature · 1 line
2.24.0
Maxime Ripard
AppliedRe: [PATCH v5 15/16] dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
Quoted 6 lines · Frank Lee
From: Yangtao Li <[email protected]>
Document board compatible names for Allwinner A100 Perf1 Board.
Signed-off-by Yangtao Li <[email protected]>Reviewed-by Rob Herring <[email protected]>
Applied, thanks!
Maxime
PATCH v5 16/16 arm64: allwinner: A100: add support for Allwinner Perf1 board
In reply to Frank LeeFrom: Yangtao Li <[email protected]>
A100 perf1 is an Allwinner A100-based SBC, with the following features:
- 1GiB DDR3 DRAM
- AXP803 PMIC
- 2 USB 2.0 ports
- MicroSD slot and on-board eMMC module
- on-board Nand flash
- ···
Adds initial support for it, including UART and PMU.
--- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun50i-a100-allwinner-perf1.dts | 180 ++++++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
arch/arm64/boot/dts/allwinner/Makefile +1 -0
@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb
arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts new file +180 -0
180 lines not on this page · raw message
Signature · 1 line
2.24.0
Re: [PATCH v5 16/16] arm64: allwinner: A100: add support for Allwinner Perf1 board
Quoted 11 lines · Frank Lee
From: Yangtao Li <[email protected]>
A100 perf1 is an Allwinner A100-based SBC, with the following features:
- 1GiB DDR3 DRAM
- AXP803 PMIC
- 2 USB 2.0 ports
- MicroSD slot and on-board eMMC module
- on-board Nand flash
- ···
Quoted 3 lines
Adds initial support for it, including UART and PMU.
Signed-off-by Yangtao Li <[email protected]>
Applied thanks!
Maxime
Frank Lee
maintainerHI Maxime,
Any comments on thermal and other patches?
I hope these patches can be integrated into the mainline as soon as possible.
Thx,
Yangtao
Frank Lee
maintainerping......
Quoted 1 line · Frank Lee
ping......
"Please don't send content free pings and please allow a reasonable
time for review. People get busy, go on holiday, attend conferences and so on so unless there is some reason for urgency (like critical bug fixes) please allow at least a couple of weeks for review. If there have been review comments then people may be waiting for those to be addressed. Sending content free pings just adds to the mail volume (if they are seen at all) and if something has gone wrong you'll have to resend the patches anyway so [RESEND]ing with any comments addressed is generally a much better approach."
Signature · 4 lines
Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
Quoted 4 lines · Lee Jones
Quoted 1 line · Frank Lee
ping......
Quoted 9 lines
"Please don't send content free pings and please allow a reasonable
time for review. People get busy, go on holiday, attend conferences and so on so unless there is some reason for urgency (like critical bug fixes) please allow at least a couple of weeks for review. If there have been review comments then people may be waiting for those to be addressed. Sending content free pings just adds to the mail volume (if they are seen at all) and if something has gone wrong you'll have to resend the patches anyway so [RESEND]ing with any comments addressed is generally a much better approach."
This is true to some extent, but pinging after a month doesn't seem unreasonable either.
Maxime
Quoted 15 lines · Maxime Ripard
Quoted 4 lines · Lee Jones
Quoted 1 line · Frank Lee
ping......
Quoted 9 lines
"Please don't send content free pings and please allow a reasonable
time for review. People get busy, go on holiday, attend conferences and so on so unless there is some reason for urgency (like critical bug fixes) please allow at least a couple of weeks for review. If there have been review comments then people may be waiting for those to be addressed. Sending content free pings just adds to the mail volume (if they are seen at all) and if something has gone wrong you'll have to resend the patches anyway so [RESEND]ing with any comments addressed is generally a much better approach."
Quoted 2 lines
This is true to some extent, but pinging after a month doesn't seem unreasonable either.
Especially if resending would mean up to 16 patches sent again.
Quoted 15 lines · Maxime Ripard
Quoted 4 lines · Lee Jones
Quoted 1 line · Frank Lee
ping......
Quoted 9 lines
"Please don't send content free pings and please allow a reasonable
time for review. People get busy, go on holiday, attend conferences and so on so unless there is some reason for urgency (like critical bug fixes) please allow at least a couple of weeks for review. If there have been review comments then people may be waiting for those to be addressed. Sending content free pings just adds to the mail volume (if they are seen at all) and if something has gone wrong you'll have to resend the patches anyway so [RESEND]ing with any comments addressed is generally a much better approach."
Quoted 2 lines
This is true to some extent, but pinging after a month doesn't seem unreasonable either.
Pinging is mostly a fruitless exercise.
After a month, many Maintainers would have purged any un-serviced mails anyway. If a patch-set is left hanging, still requiring attention before the next version, submitting a [RESEND] is generally a better option.
Signature · 4 lines
Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
Quoted 2 lines · Frank Lee
This patch set adds initial support for allwinner a100 soc, which is a 64-bit tablet chip.
Shall I commit the pinctrl patches (if Maxime ACKed) separately or not? Once Maxime is happy, I am usually happy too.
Yours,
Linus Walleij
Frank Lee
maintainerHI Linus,
Quoted 8 lines · Linus Walleij
Quoted 2 lines · Frank Lee
This patch set adds initial support for allwinner a100 soc, which is a 64-bit tablet chip.
Shall I commit the pinctrl patches (if Maxime ACKed) separately or not? Once Maxime is happy, I am usually happy too.
Maxime told me he wanted you to commit the pinctrl patches.
Thx,
Yangtao
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Linus
Quoted 7 lines · Linus Walleij
Quoted 2 lines · Frank Lee
This patch set adds initial support for allwinner a100 soc, which is a 64-bit tablet chip.
Shall I commit the pinctrl patches (if Maxime ACKed) separately or not? Once Maxime is happy, I am usually happy too.
Yeah, you can apply it to your tree
Thanks!
Maxime
Quoted 3 lines · Frank Lee
dt-bindings: pinctrl: sunxi: Get rid of continual nesting
dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings
pinctrl: sunxi: add support for the Allwinner A100 pin controller
These three patches (3,4,5) are now applied to the pinctrl tree.
Yours,
Linus Walleij
Quoted 2 lines · Frank Lee
This patch set adds initial support for allwinner a100 soc, which is a 64-bit tablet chip.
Applied patches 7,8,9
Thanks
-- Daniel
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog