Second step support for A100

From: Yangtao Li <[email protected]>

Add a binding for A100's dma controller.

Signed-off-by Yangtao Li <[email protected]>

---
 .../devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml    | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

From: Yangtao Li <[email protected]>

Add a binding for A100's watchdog controller.

Signed-off-by Yangtao Li <[email protected]>

---
 .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml  | 3 +++
 1 file changed, 3 insertions(+)

From: Yangtao Li <[email protected]>

Add a device tree binding for the A100's USB PHY.

Signed-off-by Yangtao Li <[email protected]>

---
 .../phy/allwinner,sun50i-a100-usb-phy.yaml    | 105 ++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +0 -0

new file mode 100644
index 000000000000..cc9bbebe2bd7

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +41 -0

+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/allwinner,sun50i-a100-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A100 USB PHY Device Tree Bindings
+
+maintainers:
+  - Yangtao Li <[email protected]>
+
+properties:
+  "#phy-cells":
+    const: 1
+
+  compatible:
+    const: allwinner,sun50i-a100-usb-phy
+
+  reg:
+    items:
+      - description: PHY Control registers
+      - description: PHY PMU0 registers
+      - description: PHY PMU1 registers
+
+  reg-names:
+    items:
+      - const: phy_ctrl
+      - const: pmu0
+      - const: pmu1
+
+  clocks:
+    items:
+      - description: USB OTG PHY bus clock
+      - description: USB Host 0 PHY bus clock
+
+  clock-names:
+    items:
+      - const: usb0_phy
+      - const: usb1_phy
+
+  resets:
+    items:

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +41 -0

+
+required:
+  - "#phy-cells"
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - reg-names
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/clock/sun50i-a100-ccu.h>
+    #include <dt-bindings/reset/sun50i-a100-ccu.h>
+
+    phy@5100400 {
+        #phy-cells = <1>;
+        compatible = "allwinner,sun50i-a100-usb-phy";
+        reg = <0x05100400 0x14>,
+              <0x05101800 0x4>,
+              <0x05200800 0x4>;
+        reg-names = "phy_ctrl",
+                    "pmu0",
+                    "pmu1";
+        clocks = <&ccu CLK_USB_PHY0>,
+                 <&ccu CLK_USB_PHY1>;
+        clock-names = "usb0_phy",
+                      "usb1_phy";
+        resets = <&ccu RST_USB_PHY0>,
+                 <&ccu RST_USB_PHY1>;
+        reset-names = "usb0_reset",
+                      "usb1_reset";
+        usb0_id_det-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+        usb0_vbus_power-supply = <&usb_power_supply>;
+        usb0_vbus-supply = <&reg_drivevbus>;
+        usb1_vbus-supply = <&reg_usb1_vbus>;
+    };

Signature · 1 line

2.28.0

From: Yangtao Li <[email protected]>

Add binding for A100's mmc and emmc controller.

Signed-off-by Yangtao Li <[email protected]>

---
 .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml        | 2 ++
 1 file changed, 2 insertions(+)

From: Yangtao Li <[email protected]>

The dma of a100 is similar to h6, with some minor changes to support greater addressing capabilities.

Add support for it.

From: Yangtao Li <[email protected]>

Add a binding for A100's dma controller.

From: Yangtao Li <[email protected]>

For the current code, enable_pmu_unk1 only works in non-a83t and non-h6 types. So let's delete it from the sun50i_h6_cfg.

From: Yangtao Li <[email protected]>

Use the devm_platform_ioremap_resource_byname() and devm_platform_ioremap_resource helper to simplify the code.

From: Yangtao Li <[email protected]>

A100's pin starts with PB, so it should start with 1.

Fixes 473436e7647d6 ("pinctrl: sunxi: add support for the Allwinner A100 pin controller")

Signed-off-by Yangtao Li <[email protected]>

From: Yangtao Li <[email protected]>

The interrupt descriptor cannot be found in the interrupt processing function, and this situation cannot happen when the system is running normally. It doesn't seem right to return directly to the status of not handling gic. In this case, it must be a bug, let's mark it with WARN_ON.

Signed-off-by Yangtao Li <[email protected]>

From: Yangtao Li <[email protected]>

It is found on many allwinner soc that there is a low probability that the interrupt status cannot be read in sunxi_pinctrl_irq_handler. This will cause the interrupt status of a gpio bank to always be active on gic, preventing gic from responding to other spi interrupts correctly.

So we should call the chained_irq_* each time enter sunxi_pinctrl_irq_handler().

Cc [email protected]

Signed-off-by Yangtao Li <[email protected]>

From: Yangtao Li <[email protected]>

Add support for a100's usb phy, which with 2 PHYs.

Signed-off-by Yangtao Li <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

drivers/phy/allwinner/phy-sun4i-usb.c +0 -0

index a6900495baa5..1a0e403131e7 100644

drivers/phy/allwinner/phy-sun4i-usb.c +7 -0

 	sun50i_h6_phy,
 };
 

@@ -289,7 +290,13 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 	}
 
 	if (data->cfg->type == sun8i_a83t_phy ||
+	    data->cfg->type == sun50i_a100_phy ||
 	    data->cfg->type == sun50i_h6_phy) {
+		if (phy->pmu && data->cfg->enable_pmu_unk1) {
+			val = readl(phy->pmu + REG_PMU_UNK1);
+			writel(val & ~BIT(3), phy->pmu + REG_PMU_UNK1);
+		}
+
 		if (phy->index == 0) {
 			val = readl(data->base + data->cfg->phyctl_offset);
 			val |= PHY_CTL_VBUSVLDEXT;

@@ -339,6 +346,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
 
 	if (phy->index == 0) {
 		if (data->cfg->type == sun8i_a83t_phy ||
+		    data->cfg->type == sun50i_a100_phy ||
 		    data->cfg->type == sun50i_h6_phy) {
 			void __iomem *phyctl = data->base +
 				data->cfg->phyctl_offset;

drivers/phy/allwinner/phy-sun4i-usb.c +7 -0

+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.enable_pmu_unk1 = true,
+	.phy0_dual_route = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 	.num_phys = 4,
 	.type = sun50i_h6_phy,

From: Yangtao Li <[email protected]>

This patch adds support for A100 MMC controller, which use word address for internal dma.

Signed-off-by Yangtao Li <[email protected]>

---
 drivers/mmc/host/sunxi-mmc.c | 28 +++++++++++++++++++++++++---
 1 file changed, 25 insertions(+), 3 deletions(-)

drivers/mmc/host/sunxi-mmc.c +2 -1

index fc62773602ec..1518b64112b7 100644
@@ -244,6 +244,7 @@ struct sunxi_idma_des {
 
 struct sunxi_mmc_cfg {
 	u32 idma_des_size_bits;
+	u32 idma_des_shift;
 	const struct sunxi_mmc_clk_delay *clk_delays;
 
 	/* does the IP block support autocalibration? */

@@ -343,7 +344,7 @@ static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
 	/* Enable CEATA support */
 	mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
 	/* Set DMA descriptor list base address */
-	mmc_writel(host, REG_DLBA, host->sg_dma);
+	mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);
 
 	rval = mmc_readl(host, REG_GCTRL);
 	rval |= SDXC_INTERRUPT_ENABLE_BIT;

drivers/mmc/host/sunxi-mmc.c +17 -0

 	}
 
 	pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);

@@ -1178,6 +1181,23 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
 	.needs_new_timings = true,
 };
 
+static const struct sunxi_mmc_cfg sun50i_a100_cfg = {
+	.idma_des_size_bits = 16,
+	.idma_des_shift = 2,
+	.clk_delays = NULL,
+	.can_calibrate = true,
+	.mask_data0 = true,
+	.needs_new_timings = true,
+};
+
+static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
+	.idma_des_size_bits = 13,
+	.idma_des_shift = 2,
+	.clk_delays = NULL,
+	.can_calibrate = true,
+	.needs_new_timings = true,
+};
+
 static const struct of_device_id sunxi_mmc_of_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },

From: Yangtao Li <[email protected]>

The A100 has 3 MMC controllers, one of them being especially targeted to eMMC. Let's add nodes on dts.

Signed-off-by Yangtao Li <[email protected]>

---
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)

arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +64 -0

index c731bb9727c2..4adfc7d4854a 100644
@@ -169,12 +169,83 @@ pio: pinctrl@300b000 {
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3",
+				       "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/
+			mmc1_pins: mmc1-pins {
+				pins = "PG0", "PG1", "PG2", "PG3",
+				       "PG4", "PG5";
+				function = "mmc1";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			mmc2_pins: mmc2-pins {
+				pins = "PC0", "PC1", "PC5", "PC6",
+				       "PC8", "PC9", "PC10", "PC11",
+				       "PC13", "PC14", "PC15", "PC16";
+				function = "mmc2";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
 			uart0_pb_pins: uart0-pb-pins {
 				pins = "PB9", "PB10";
 				function = "uart0";
 			};
 		};
 
+		mmc0: mmc@4020000 {
+			compatible = "allwinner,sun50i-a100-mmc";
+			reg = <0x04020000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@4021000 {
+			compatible = "allwinner,sun50i-a100-mmc";
+			reg = <0x04021000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc1_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@4022000 {
+			compatible = "allwinner,sun50i-a100-emmc";
+			reg = <0x04022000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC2>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

Quoted 3 lines

From: Yangtao Li <[email protected]>

Add a device tree binding for the A100's USB PHY.

Quoted 13 lines

Signed-off-by Yangtao Li <[email protected]>

---
 .../phy/allwinner,sun50i-a100-usb-phy.yaml    | 105 ++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +0 -0

new file mode 100644
index 000000000000..cc9bbebe2bd7

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml line 1

Quoted 1 line

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +1 -0

@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0

Dual license new bindings. checkpatch.pl will tell you which ones.

Quoted 41 lines

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +41 -0

+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/allwinner,sun50i-a100-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A100 USB PHY Device Tree Bindings
+
+maintainers:
+  - Yangtao Li <[email protected]>
+
+properties:
+  "#phy-cells":
+    const: 1
+
+  compatible:
+    const: allwinner,sun50i-a100-usb-phy
+
+  reg:
+    items:
+      - description: PHY Control registers
+      - description: PHY PMU0 registers
+      - description: PHY PMU1 registers
+
+  reg-names:
+    items:
+      - const: phy_ctrl
+      - const: pmu0
+      - const: pmu1
+
+  clocks:
+    items:
+      - description: USB OTG PHY bus clock
+      - description: USB Host 0 PHY bus clock
+
+  clock-names:
+    items:
+      - const: usb0_phy
+      - const: usb1_phy
+
+  resets:
+    items:

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml line 52

Quoted 10 lines

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +10 -0

+      - description: USB OTG reset
+      - description: USB Host 1 Controller reset
+
+  reset-names:
+    items:
+      - const: usb0_reset
+      - const: usb1_reset
+
+  usb0_id_det-gpios:
+    description: GPIO to the USB OTG ID pin

Needs 'maxItems: 1'

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml line 64

Quoted 12 lines

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +12 -0

+
+  usb0_vbus_det-gpios:
+    description: GPIO to the USB OTG VBUS detect pin
+
+  usb0_vbus_power-supply:
+    description: Power supply to detect the USB OTG VBUS
+
+  usb0_vbus-supply:
+    description: Regulator controlling USB OTG VBUS
+
+  usb1_vbus-supply:
+    description: Regulator controlling USB1 Host controller

Are ID and VBus actually connected to the phy h/w? Really, all this should be in a USB connector node for which we have bindings.

Quoted 41 lines

Documentation/devicetree/bindings/phy/allwinner,sun50i-a100-usb-phy.yaml new file +41 -0

+
+required:
+  - "#phy-cells"
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - reg-names
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/clock/sun50i-a100-ccu.h>
+    #include <dt-bindings/reset/sun50i-a100-ccu.h>
+
+    phy@5100400 {
+        #phy-cells = <1>;
+        compatible = "allwinner,sun50i-a100-usb-phy";
+        reg = <0x05100400 0x14>,
+              <0x05101800 0x4>,
+              <0x05200800 0x4>;
+        reg-names = "phy_ctrl",
+                    "pmu0",
+                    "pmu1";
+        clocks = <&ccu CLK_USB_PHY0>,
+                 <&ccu CLK_USB_PHY1>;
+        clock-names = "usb0_phy",
+                      "usb1_phy";
+        resets = <&ccu RST_USB_PHY0>,
+                 <&ccu RST_USB_PHY1>;
+        reset-names = "usb0_reset",
+                      "usb1_reset";
+        usb0_id_det-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+        usb0_vbus_power-supply = <&usb_power_supply>;
+        usb0_vbus-supply = <&reg_drivevbus>;
+        usb1_vbus-supply = <&reg_usb1_vbus>;
+    };

Quoted 3 lines

Signature · 1 line

2.28.0

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

From: Yangtao Li <[email protected]>

Declare A100's watchdog in the device-tree.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +1 -0

index 01ff53b5a7a8..6aa3337ce0e9 100644
@@ -144,6 +144,14 @@ ths_calibration: calib@14 {
 			};
 		};
 
+		watchdog@30090a0 {

From: Yangtao Li <[email protected]>

The dma of a100 is similar to h6, with some minor changes to support greater addressing capabilities.

Add support for it.>

Signed-off-by Yangtao Li <[email protected]>

---
 drivers/dma/sun6i-dma.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

drivers/dma/sun6i-dma.c +24 -0

index f5f9c86c50bc..5cadd4d2b824 100644
@@ -1173,6 +1173,30 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
 			     BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
 };
 
+/*
+ * TODO: Add support for more than 4g physical addressing.
+ *
+ * The A100 binding uses the number of dma channels from the
+ * device tree node.
+ */
+static struct sun6i_dma_config sun50i_a100_dma_cfg = {
+	.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
+	.set_burst_length = sun6i_set_burst_length_h3,
+	.set_drq          = sun6i_set_drq_h6,
+	.set_mode         = sun6i_set_mode_h6,
+	.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+	.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
+	.src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+			     BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+			     BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+			     BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+	.dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
+			     BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
+			     BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
+			     BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
+	.has_mbus_clk = true,
+};
+
 /*
  * The H6 binding uses the number of dma channels from the
  * device tree node.

From: Yangtao Li <[email protected]>

The A100 SoC has a DMA controller that supports 8 DMA channels to and from various peripherals.

Add a device node for it.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +0 -0

index cc321c04f121..c34ed8045363 100644

arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +3 -0

+			reg = <0x03002000 0x1000>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;

From: Yangtao Li <[email protected]>

Add the Performance Monitoring Unit (PMU) device tree node to the A100 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core.

Signed-off-by Yangtao Li <[email protected]>

---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +5 -3

index c34ed8045363..01ff53b5a7a8 100644
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x1>;
 			enable-method = "psci";
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x2>;
 			enable-method = "psci";
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x3>;

@@ -47,6 +47,15 @@ cpu@3 {
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";

On 10/11/2020 06:46, Frank Lee wrote:

Quoted 32 lines

From: Yangtao Li <[email protected]>

This patch adds support for A100 MMC controller, which use word address for internal dma.

Signed-off-by Yangtao Li <[email protected]>

---
 drivers/mmc/host/sunxi-mmc.c | 28 +++++++++++++++++++++++++---
 1 file changed, 25 insertions(+), 3 deletions(-)

drivers/mmc/host/sunxi-mmc.c +2 -1

index fc62773602ec..1518b64112b7 100644
@@ -244,6 +244,7 @@ struct sunxi_idma_des {
 
 struct sunxi_mmc_cfg {
 	u32 idma_des_size_bits;
+	u32 idma_des_shift;
 	const struct sunxi_mmc_clk_delay *clk_delays;
 
 	/* does the IP block support autocalibration? */

@@ -343,7 +344,7 @@ static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
 	/* Enable CEATA support */
 	mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
 	/* Set DMA descriptor list base address */
-	mmc_writel(host, REG_DLBA, host->sg_dma);
+	mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);
 
 	rval = mmc_readl(host, REG_GCTRL);
 	rval |= SDXC_INTERRUPT_ENABLE_BIT;

drivers/mmc/host/sunxi-mmc.c static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, · line 380

Quoted 9 lines

drivers/mmc/host/sunxi-mmc.c +4 -2

@@ -373,8 +374,10 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 
 		next_desc += sizeof(struct sunxi_idma_des);
 		pdes[i].buf_addr_ptr1 =
-			cpu_to_le32(sg_dma_address(&data->sg[i]));
-		pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
+			cpu_to_le32(sg_dma_address(&data->sg[i]) >>
+				    host->cfg->idma_des_shift);
+		pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >>
+						    host->cfg->idma_des_shift);

I think you should cast after the shift, otherwise you lose the ability to run above 4 GB. This won't be a problem at the moment, since we still use the default 32-bit DMA mask, but might bite us later.

Otherwise this patch looks fine, and works on the H616 as well.

Cheers,
Andre

Quoted 7 lines

drivers/mmc/host/sunxi-mmc.c +0 -0

 	}
 
 	pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);

@@ -1178,6 +1181,23 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
 	.needs_new_timings = true,
 };
 

drivers/mmc/host/sunxi-mmc.c static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { · line 1195

Quoted 12 lines

drivers/mmc/host/sunxi-mmc.c +12 -0

+static const struct sunxi_mmc_cfg sun50i_a100_cfg = {
+	.idma_des_size_bits = 16,
+	.idma_des_shift = 2,
+	.clk_delays = NULL,
+	.can_calibrate = true,
+	.mask_data0 = true,
+	.needs_new_timings = true,
+};
+
+static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
+	.idma_des_size_bits = 13,
+	.idma_des_shift = 2,

Quoted 18 lines

drivers/mmc/host/sunxi-mmc.c +7 -0

+	.clk_delays = NULL,
+	.can_calibrate = true,
+	.needs_new_timings = true,
+};
+
 static const struct of_device_id sunxi_mmc_of_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },

@@ -1186,6 +1206,8 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
 	{ .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
 	{ .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
 	{ .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
+	{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
+	{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);

On 11/11/2020 22:50, Rob Herring wrote:

Hi,

Quoted 1 line · Frank Lee

Quoted 3 lines

Quoted 3 lines

From: Yangtao Li <[email protected]>

Add a device tree binding for the A100's USB PHY.

Not your fault, Yangto, but why do we actually have a separate binding document per SoC, when the differences between the PHYs are so minimal that we get away with some flags in the compatible match, in one driver file?

For a start this file is basically identical to the A64 one (apart from the example), so can you just add the A100 compatible string to that one, instead?

From: Yangtao Li <[email protected]>

Add support for a100's usb phy, which with 2 PHYs.

Signed-off-by Yangtao Li <[email protected]>

---
 drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

drivers/phy/allwinner/phy-sun4i-usb.c +1 -0

index a6900495baa5..1a0e403131e7 100644
@@ -107,6 +107,7 @@ enum sun4i_usb_phy_type {
 	sun8i_r40_phy,
 	sun8i_v3s_phy,
 	sun50i_a64_phy,
+	sun50i_a100_phy,
 	sun50i_h6_phy,
 };
 

drivers/phy/allwinner/phy-sun4i-usb.c +12 -0

 		if (phy->index == 0) {
 			val = readl(data->base + data->cfg->phyctl_offset);
 			val |= PHY_CTL_VBUSVLDEXT;

@@ -339,6 +346,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
 
 	if (phy->index == 0) {
 		if (data->cfg->type == sun8i_a83t_phy ||
+		    data->cfg->type == sun50i_a100_phy ||
 		    data->cfg->type == sun50i_h6_phy) {
 			void __iomem *phyctl = data->base +
 				data->cfg->phyctl_offset;

@@ -960,6 +968,16 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.phy0_dual_route = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun50i_a100_cfg = {
+	.num_phys = 2,
+	.type = sun50i_a100_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.enable_pmu_unk1 = true,
+	.phy0_dual_route = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 	.num_phys = 4,
 	.type = sun50i_h6_phy,

@@ -983,6 +1001,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy",
 	  .data = &sun50i_a64_cfg},
+	{ .compatible = "allwinner,sun50i-a100-usb-phy", .data = &sun50i_a100_cfg },
 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
 	{ },
 };