arm64: dts: zynqmp: DT updates to match latest drivers

PATCH In review Michal Simek 3 participants 16 messages Jan 21, 2021 – Feb 1, 2021

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Michal Simek

author

2021-01-21 10:28 UTC #0 lore raw

v2 cover arm64: dts: zynqmp: DT updates to match latest drivers

Hi,

I am sending this series to reflect the latest drivers which have been merged to mainline kernel. I have boot it on zcu102-rev1.0 and also zcu104-rev1.0. That's why I have also added DT for this newer revision.

The series is based on https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt.
And mio-bank patch requires update in dt-binding which has been posted here
https://lore.kernel.org/r/5fa17dfe4b42abefd84b4cbb7b8bcd4d31398f40.1606914986.git.michal.simek@xilinx.com

Thanks,
Michal

Changes in v2:
- Remove reset description for IPs from this patch. IPs will be enabled separately with DT binding update.
- Change patch subject

Michal Simek (12):
arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111
arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
arm64: dts: zynqmp: Enable reset controller driver
arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
arm64: dts: zynqmp: Add label for zynqmp_ipi
arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis
arm64: dts: zynqmp: Wire arasan nand controller
arm64: dts: zynqmp: Wire zynqmp qspi controller
arm64: dts: zynqmp: Add missing lpd watchdog node
arm64: dts: zynqmp: Add missing iommu IDs
arm64: dts: zynqmp: Add description for zcu104 revC

 arch/arm64/boot/dts/xilinx/Makefile           |   1 +
 .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi |  12 +
 .../boot/dts/xilinx/zynqmp-zcu100-revC.dts    |   2 +
 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    |  84 +++++-
 .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    |  29 ++
 .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 282 ++++++++++++++++++
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    |  78 +++++
 .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    |  59 +++-
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi        |  94 +++++-
 9 files changed, 637 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts

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Michal Simek

author

2021-01-21 10:28 UTC #1 lore raw

PATCH v2 1/12 arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111

u48 chip on zcu111 is si5382 not si5328.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +1 -1

index 2e92634c77f9..d9a8fdbbcae8 100644
@@ -410,7 +410,7 @@ i2c@4 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <4>;
-			si5328: clock-generator@69 { /* SI5328 - u48 */
+			si5382: clock-generator@69 { /* SI5382 - u48 */
 				reg = <0x69>;
 			};
 		};

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Michal Simek

author

2021-01-21 10:29 UTC #2 lore raw

PATCH v2 2/12 arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106

In reply to Michal Simek

Origin DT binding just specify driver but wasn't aligned with DT binding which came later. Extend description for zcu102 and zcu106 to cover latest binding.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    | 17 ++++++++++++++
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    | 22 +++++++++++++++++++
 2 files changed, 39 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +17 -0

index f1255f635dfd..5ff7ab665374 100644
@@ -132,6 +132,12 @@ ina226-u75 {
 		compatible = "iio-hwmon";
 		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 	};
+
+	refhdmi: refhdmi {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <114285000>;
+	};
 };
 
 &can1 {

@@ -526,6 +532,17 @@ si5328: clock-generator@69 {/* SI5328 - u20 */
 				 * interrupt-parent = <&>;
 				 * interrupts = <>;
 				 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#clock-cells = <1>;
+				clocks = <&refhdmi>;
+				clock-names = "xtal";
+				clock-output-names = "si5328";
+
+				si5328_clk: clk0@0 {
+					reg = <0>;
+					clock-frequency = <27000000>;
+				};
 			};
 		};
 		/* 5 - 7 unconnected */

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +22 -0

index 6e9efe233838..7910ac125101 100644
@@ -132,6 +132,12 @@ ina226-u75 {
 		compatible = "iio-hwmon";
 		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 	};
+
+	refhdmi: refhdmi {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <114285000>;
+	};
 };
 
 &can1 {

@@ -520,6 +526,22 @@ i2c@4 {
 			reg = <4>;
 			si5328: clock-generator@69 {/* SI5328 - u20 */
 				reg = <0x69>;
+				/*
+				 * Chip has interrupt present connected to PL
+				 * interrupt-parent = <&>;
+				 * interrupts = <>;
+				 */
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#clock-cells = <1>;
+				clocks = <&refhdmi>;
+				clock-names = "xtal";
+				clock-output-names = "si5328";
+
+				si5328_clk: clk0@0 {
+					reg = <0>;
+					clock-frequency = <27000000>;
+				};
 			};
 		};
 		i2c@5 {

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Michal Simek

author

2021-01-21 10:29 UTC #3 lore raw

PATCH v2 3/12 arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111

In reply to Michal Simek

Enable si5341 driver is the main chip for providing preprogrammed clocks for the whole platform.

 # cat /sys/kernel/debug/clk/clk_summary
...
 refhdmi                              1        1        0   114285000          0     0  50000
    xtal_0                            0        0        0   114285000          0     0  50000
       pll_0                          0        0        0 40731174000000          0     0  50000
          clk1_0                      0        0        0    27000000          0     0  50000
          clk0_0                      0        0        0    27000000          0     0  50000
 ref48M                               1        2        0    48000000          0     0  50000
    si5341                            0        4        0    14000000          0     0  50000
       clock-generator.N4             0        0        0           0          0     0  50000
       clock-generator.N3             0        1        0   733260000          0     0  50000
          clock-generator.9           0        1        0    33330000          0     0  50000
       clock-generator.N2             0        1        0   104000000          0     0  50000
          clock-generator.2           0        1        0    26000000          0     0  50000
       clock-generator.N1             0        2        0   594000000          0     0  50000
          clock-generator.7           0        1        0    74250000          0     0  50000
          clock-generator.0           0        1        0    27000000          0     0  50000
       clock-generator.N0             0        4        0  1000000000          0     0  50000
          clock-generator.8           0        0        0           0          0     0  50000
          clock-generator.6           0        1        0   125000000          0     0  50000
          clock-generator.5           0        1        0   100000000          0     0  50000
          clock-generator.4           0        1        0   100000000          0     0  50000
          clock-generator.3           0        1        0   125000000          0     0  50000
          clock-generator.1           0        0        0           0          0     0  50000
...

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    | 56 ++++++++++++++++++-
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    | 45 +++++++++++++++
 .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    | 46 ++++++++++++++-
 3 files changed, 145 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +55 -1

index 5ff7ab665374..68c2ad30d62d 100644
@@ -133,6 +133,13 @@ ina226-u75 {
 		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 	};
 
+	/* 48MHz reference crystal */
+	ref48: ref48M {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <48000000>;
+	};
+
 	refhdmi: refhdmi {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;

@@ -489,9 +496,56 @@ i2c@1 {
 			#size-cells = <0>;
 			reg = <1>;
 			si5341: clock-generator@36 { /* SI5341 - u69 */
+				compatible = "silabs,si5341";
 				reg = <0x36>;
-			};
+				#clock-cells = <2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&ref48>;
+				clock-names = "xtal";
+				clock-output-names = "si5341";
 
+				si5341_0: out@0 {
+					/* refclk0 for PS-GT, used for DP */
+					reg = <0>;
+					always-on;
+				};
+				si5341_2: out@2 {
+					/* refclk2 for PS-GT, used for USB3 */
+					reg = <2>;
+					always-on;
+				};
+				si5341_3: out@3 {
+					/* refclk3 for PS-GT, used for SATA */
+					reg = <3>;
+					always-on;
+				};
+				si5341_4: out@4 {
+					/* refclk4 for PS-GT, used for PCIE slot */
+					reg = <4>;
+					always-on;
+				};
+				si5341_5: out@5 {
+					/* refclk5 for PS-GT, used for PCIE */
+					reg = <5>;
+					always-on;
+				};
+				si5341_6: out@6 {
+					/* refclk6 PL CLK125 */
+					reg = <6>;
+					always-on;
+				};
+				si5341_7: out@7 {
+					/* refclk7 PL CLK74 */
+					reg = <7>;
+					always-on;
+				};
+				si5341_9: out@9 {
+					/* refclk9 used for PS_REF_CLK 33.3 MHz */
+					reg = <9>;
+					always-on;
+				};
+			};
 		};
 		i2c@2 {
 			#address-cells = <1>;

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +45 -0

58 lines not on this page · raw message

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +45 -1

60 lines not on this page · raw message

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Michal Simek

author

2021-01-21 10:29 UTC #4 lore raw

PATCH v2 4/12 arm64: dts: zynqmp: Enable reset controller driver

In reply to Michal Simek

Enable reset controller to be prepared for use.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- Remove reset description for IPs from this patch. IPs will be enabled separately with DT binding update.
- Change patch subject

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +5 -0

index cdc1a0ddfa01..94a2e1f2b713 100644
@@ -187,6 +187,11 @@ zynqmp_pcap: pcap {
 			xlnx_aes: zynqmp-aes {
 				compatible = "xlnx,zynqmp-aes";
 			};
+
+			zynqmp_reset: reset-controller {
+				compatible = "xlnx,zynqmp-reset";
+				#reset-cells = <1>;
+			};
 		};
 	};

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Laurent Pinchart

Reviewed-by on v2 4/12

2021-01-21 22:39 UTC #5 lore raw

Re: [PATCH v2 04/12] arm64: dts: zynqmp: Enable reset controller driver

Hi Michal,

Thank you for the patch.

Quoted 3 lines · Michal Simek

Enable reset controller to be prepared for use.
Signed-off-by Michal Simek <[email protected]>

Reviewed-by Laurent Pinchart <[email protected]>

Quoted 26 lines

---
Changes in v2:
- Remove reset description for IPs from this patch. IPs will be enabled separately with DT binding update.
- Change patch subject
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++++
 1 file changed, 5 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +5 -0
index cdc1a0ddfa01..94a2e1f2b713 100644
@@ -187,6 +187,11 @@ zynqmp_pcap: pcap {
 			xlnx_aes: zynqmp-aes {
 				compatible = "xlnx,zynqmp-aes";
 			};
+
+			zynqmp_reset: reset-controller {
+				compatible = "xlnx,zynqmp-reset";
+				#reset-cells = <1>;
+			};
 		};
 	};
 

Signature · 3 lines

Regards,

Laurent Pinchart

Michal Simek

author

2021-01-21 10:29 UTC #6 lore raw

PATCH v2 5/12 arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106

In reply to Michal Simek

Enable psgtr driver and write clocks property to get sata to work.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    | 10 +++++++
 .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    | 28 +++++++++++++++++++
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    | 10 +++++++
 .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    | 10 +++++++
 4 files changed, 58 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +10 -0

index 68c2ad30d62d..d92698ffbf8c 100644
@@ -13,6 +13,7 @@
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	model = "ZynqMP ZCU102 RevA";

@@ -663,6 +664,13 @@ &pcie {
 	status = "okay";
 };
 
+&psgtr {
+	status = "okay";
+	/* pcie, sata, usb3, dp */
+	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+	clock-names = "ref0", "ref1", "ref2", "ref3";
+};
+
 &rtc {
 	status = "okay";
 };

@@ -678,6 +686,8 @@ &sata {
 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 };
 
 /* SD1 with level shifter */

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +28 -0

index 7a4614e3f5fa..5e2be9abc175 100644
@@ -12,6 +12,7 @@
 #include "zynqmp.dtsi"
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	model = "ZynqMP ZCU104 RevA";

@@ -36,6 +37,24 @@ memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
+
+	clock_8t49n287_5: clk125 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	clock_8t49n287_2: clk26 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+	};
+
+	clock_8t49n287_3: clk27 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
 };
 
 &can1 {

@@ -158,6 +177,13 @@ &rtc {
 	status = "okay";
 };
 
+&psgtr {
+	status = "okay";
+	/* nc, sata, usb3, dp */
+	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
 &sata {
 	status = "okay";
 	/* SATA OOB timing settings */

@@ -169,6 +195,8 @@ &sata {
 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 };
 
 /* SD1 with level shifter */

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +10 -0

index a29ff20090ce..4ec6715abab7 100644
@@ -13,6 +13,7 @@
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	model = "ZynqMP ZCU106 RevA";

@@ -658,6 +659,13 @@ i2c@7 {
 	};
 };
 
+&psgtr {
+	status = "okay";
+	/* nc, sata, usb3, dp */
+	clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
 &rtc {
 	status = "okay";
 };

@@ -673,6 +681,8 @@ &sata {
 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 };
 
 /* SD1 with level shifter */

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +10 -0

index 92b3cee62d11..2969c4b71384 100644
@@ -13,6 +13,7 @@
 #include "zynqmp-clk-ccf.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	model = "ZynqMP ZCU111 RevA";

@@ -541,6 +542,13 @@ i2c@7 {
 	};
 };
 
+&psgtr {
+	status = "okay";
+	/* nc, sata, usb3, dp */
+	clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
 &rtc {
 	status = "okay";
 };

@@ -556,6 +564,8 @@ &sata {
 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 };
 
 /* SD1 with level shifter */

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Michal Simek

author

2021-01-21 10:29 UTC #7 lore raw

PATCH v2 6/12 arm64: dts: zynqmp: Add label for zynqmp_ipi

In reply to Michal Simek

Add label which is used by bootloader for adding bootloader specific flag.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

U-Boot needs to add u-boot,dm-pre-reloc; property

---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +1 -1

index 94a2e1f2b713..31c6943c6217 100644
@@ -99,7 +99,7 @@ opp03 {
 		};
 	};
 
-	zynqmp_ipi {
+	zynqmp_ipi: zynqmp_ipi {
 		compatible = "xlnx,zynqmp-ipi-mailbox";
 		interrupt-parent = <&gic>;
 		interrupts = <0 35 4>;

Signature · 1 line

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Michal Simek

author

2021-01-21 10:30 UTC #8 lore raw

PATCH v2 7/12 arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis

In reply to Michal Simek

Add missing xlnx,mio-bank property to sdhci nodes. Also add properties with 0 value to have it listed in case that files are copied to different projects where default case doesn't need to be handled in the same way. That's why explicitly list them too.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

Based on dt binding fix:
https://lore.kernel.org/r/5fa17dfe4b42abefd84b4cbb7b8bcd4d31398f40.1606914986.git.michal.simek@xilinx.com

---
 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++
 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 1 +
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 +
 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 1 +
 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 +
 5 files changed, 6 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +2 -0

index 68ecd0f7b2f2..71ebcaadb7c8 100644
@@ -233,11 +233,13 @@ &sdhci0 {
 	status = "okay";
 	no-1-8-v;
 	disable-wp;
+	xlnx,mio-bank = <0>;
 };
 
 &sdhci1 {
 	status = "okay";
 	bus-width = <0x4>;
+	xlnx,mio-bank = <0>;
 	non-removable;
 	disable-wp;
 	cap-power-off-card;

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +1 -0

index d92698ffbf8c..9abd10f6785a 100644
@@ -694,6 +694,7 @@ &sata {
 &sdhci1 {
 	status = "okay";
 	no-1-8-v;
+	xlnx,mio-bank = <1>;
 };
 
 &uart0 {

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +1 -0

index 5e2be9abc175..8ede619fea52 100644
@@ -203,6 +203,7 @@ &sata {
 &sdhci1 {
 	status = "okay";
 	no-1-8-v;
+	xlnx,mio-bank = <1>;
 	disable-wp;
 };

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +1 -0

index 4ec6715abab7..d60a30787022 100644
@@ -689,6 +689,7 @@ &sata {
 &sdhci1 {
 	status = "okay";
 	no-1-8-v;
+	xlnx,mio-bank = <1>;
 };
 
 &uart0 {

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +1 -0

index 2969c4b71384..758de05c4a4b 100644
@@ -572,6 +572,7 @@ &sata {
 &sdhci1 {
 	status = "okay";
 	no-1-8-v;
+	xlnx,mio-bank = <1>;
 };
 
 &uart0 {

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Michal Simek

author

2021-01-21 10:30 UTC #9 lore raw

PATCH v2 8/12 arm64: dts: zynqmp: Wire arasan nand controller

In reply to Michal Simek

Add missing arasan controller with clocks. Disable it by default. Every board can enable it with specifying others properties.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi |  4 ++++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi         | 12 ++++++++++++
 2 files changed, 16 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +4 -0

index c94c3bb67edc..7af57619436d 100644
@@ -116,6 +116,10 @@ &lpd_dma_chan8 {
 	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
 };
 
+&nand0 {
+	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
 &gem0 {
 	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
 		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +12 -0

index 31c6943c6217..19b349f00ce7 100644
@@ -462,6 +462,18 @@ mc: memory-controller@fd070000 {
 			interrupts = <0 112 4>;
 		};
 
+		nand0: nand-controller@ff100000 {
+			compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
+			status = "disabled";
+			reg = <0x0 0xff100000 0x0 0x1000>;
+			clock-names = "controller", "bus";
+			interrupt-parent = <&gic>;
+			interrupts = <0 14 4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			power-domains = <&zynqmp_firmware PD_NAND>;
+		};
+
 		gem0: ethernet@ff0b0000 {
 			compatible = "cdns,zynqmp-gem", "cdns,gem";
 			status = "disabled";

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Michal Simek

author

2021-01-21 10:29 UTC #10 lore raw

PATCH v2 9/12 arm64: dts: zynqmp: Wire zynqmp qspi controller

In reply to Michal Simek

Add missing ZynqMP qspi IP. It works in single mode only.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi |  4 ++++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi         | 14 ++++++++++++++
 2 files changed, 18 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +4 -0

index 7af57619436d..6a577e1383c1 100644
@@ -164,6 +164,10 @@ &pcie {
 	clocks = <&zynqmp_clk PCIE_REF>;
 };
 
+&qspi {
+	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
 &sata {
 	clocks = <&zynqmp_clk SATA_REF>;
 };

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +14 -0

index 19b349f00ce7..533c19b80283 100644
@@ -595,6 +595,20 @@ pcie_intc: legacy-interrupt-controller {
 			};
 		};
 
+		qspi: spi@ff0f0000 {
+			compatible = "xlnx,zynqmp-qspi-1.0";
+			status = "disabled";
+			clock-names = "ref_clk", "pclk";
+			interrupts = <0 15 4>;
+			interrupt-parent = <&gic>;
+			num-cs = <1>;
+			reg = <0x0 0xff0f0000 0x0 0x1000>,
+			      <0x0 0xc0000000 0x0 0x8000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			power-domains = <&zynqmp_firmware PD_QSPI>;
+		};
+
 		psgtr: phy@fd400000 {
 			compatible = "xlnx,zynqmp-psgtr-v1.1";
 			status = "disabled";

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Michal Simek

author

2021-01-21 10:30 UTC #11 lore raw

PATCH v2 10/12 arm64: dts: zynqmp: Add missing lpd watchdog node

In reply to Michal Simek

Xilinx ZynqMP SoC has FPD (Full Power Domain) and LPD (Low Power Domain) watchdogs. There are cases where also LPD WDT should be used by Arm cores that's why list it with disabled status.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi         | 9 +++++++++
 2 files changed, 13 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +4 -0

index 6a577e1383c1..3ca7e4ee51b5 100644
@@ -223,3 +223,7 @@ &usb1 {
 &watchdog0 {
 	clocks = <&zynqmp_clk WDT>;
 };
+
+&lpd_watchdog {
+	clocks = <&zynqmp_clk LPD_WDT>;
+};

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +9 -0

index 533c19b80283..467f92c2044b 100644
@@ -786,5 +786,14 @@ watchdog0: watchdog@fd4d0000 {
 			reg = <0x0 0xfd4d0000 0x0 0x1000>;
 			timeout-sec = <10>;
 		};
+
+		lpd_watchdog: watchdog@ff150000 {
+			compatible = "cdns,wdt-r1p2";
+			status = "disabled";
+			interrupt-parent = <&gic>;
+			interrupts = <0 52 1>;
+			reg = <0x0 0xff150000 0x0 0x1000>;
+			timeout-sec = <10>;
+		};
 	};
 };

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Michal Simek

author

2021-01-21 10:30 UTC #12 lore raw

PATCH v2 11/12 arm64: dts: zynqmp: Add missing iommu IDs

In reply to Michal Simek

Add missing iommu IDs to all IPs which have IDs assigned.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 52 ++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

arch/arm64/boot/dts/xilinx/zynqmp.dtsi +52 -0

index 467f92c2044b..66d53521ec58 100644
@@ -270,6 +270,8 @@ fpd_dma_chan1: dma@fd500000 {
 			interrupts = <0 124 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <128>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x14e8>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};

@@ -281,6 +283,8 @@ fpd_dma_chan2: dma@fd510000 {
 			interrupts = <0 125 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <128>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x14e9>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};

@@ -292,6 +296,8 @@ fpd_dma_chan3: dma@fd520000 {
 			interrupts = <0 126 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <128>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x14ea>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};

@@ -303,6 +309,8 @@ fpd_dma_chan4: dma@fd530000 {
 			interrupts = <0 127 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <128>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x14eb>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};

@@ -314,6 +322,8 @@ fpd_dma_chan5: dma@fd540000 {
 			interrupts = <0 128 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <128>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x14ec>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};

@@ -325,6 +335,8 @@ fpd_dma_chan6: dma@fd550000 {
 			interrupts = <0 129 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <128>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x14ed>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};

@@ -336,6 +348,8 @@ fpd_dma_chan7: dma@fd560000 {
 			interrupts = <0 130 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <128>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x14ee>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};

@@ -347,6 +361,8 @@ fpd_dma_chan8: dma@fd570000 {
 			interrupts = <0 131 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <128>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x14ef>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
 		};

@@ -375,6 +391,8 @@ lpd_dma_chan1: dma@ffa80000 {
 			interrupts = <0 77 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <64>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x868>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};

@@ -386,6 +404,8 @@ lpd_dma_chan2: dma@ffa90000 {
 			interrupts = <0 78 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <64>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x869>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};

@@ -397,6 +417,8 @@ lpd_dma_chan3: dma@ffaa0000 {
 			interrupts = <0 79 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <64>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x86a>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};

@@ -408,6 +430,8 @@ lpd_dma_chan4: dma@ffab0000 {
 			interrupts = <0 80 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <64>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x86b>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};

@@ -419,6 +443,8 @@ lpd_dma_chan5: dma@ffac0000 {
 			interrupts = <0 81 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <64>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x86c>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};

@@ -430,6 +456,8 @@ lpd_dma_chan6: dma@ffad0000 {
 			interrupts = <0 82 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <64>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x86d>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};

@@ -441,6 +469,8 @@ lpd_dma_chan7: dma@ffae0000 {
 			interrupts = <0 83 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <64>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x86e>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};

@@ -452,6 +482,8 @@ lpd_dma_chan8: dma@ffaf0000 {
 			interrupts = <0 84 4>;
 			clock-names = "clk_main", "clk_apb";
 			xlnx,bus-width = <64>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x86f>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
 		};

@@ -471,6 +503,8 @@ nand0: nand-controller@ff100000 {
 			interrupts = <0 14 4>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x872>;
 			power-domains = <&zynqmp_firmware PD_NAND>;
 		};

@@ -483,6 +517,8 @@ gem0: ethernet@ff0b0000 {
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x874>;
 			power-domains = <&zynqmp_firmware PD_ETH_0>;
 		};

@@ -495,6 +531,8 @@ gem1: ethernet@ff0c0000 {
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x875>;
 			power-domains = <&zynqmp_firmware PD_ETH_1>;
 		};

@@ -507,6 +545,8 @@ gem2: ethernet@ff0d0000 {
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x876>;
 			power-domains = <&zynqmp_firmware PD_ETH_2>;
 		};

@@ -519,6 +559,8 @@ gem3: ethernet@ff0e0000 {
 			clock-names = "pclk", "hclk", "tx_clk";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x877>;
 			power-domains = <&zynqmp_firmware PD_ETH_3>;
 		};

@@ -606,6 +648,8 @@ qspi: spi@ff0f0000 {
 			      <0x0 0xc0000000 0x0 0x8000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x873>;
 			power-domains = <&zynqmp_firmware PD_QSPI>;
 		};

@@ -635,6 +679,9 @@ sata: ahci@fd0c0000 {
 			interrupt-parent = <&gic>;
 			interrupts = <0 133 4>;
 			power-domains = <&zynqmp_firmware PD_SATA>;
+			#stream-id-cells = <4>;
+			iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
+				 <&smmu 0x4c2>, <&smmu 0x4c3>;
 		};
 
 		sdhci0: mmc@ff160000 {

@@ -644,6 +691,8 @@ sdhci0: mmc@ff160000 {
 			interrupts = <0 48 4>;
 			reg = <0x0 0xff160000 0x0 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x870>;
 			#clock-cells = <1>;
 			clock-output-names = "clk_out_sd0", "clk_in_sd0";
 			power-domains = <&zynqmp_firmware PD_SD_0>;

@@ -656,6 +705,8 @@ sdhci1: mmc@ff170000 {
 			interrupts = <0 49 4>;
 			reg = <0x0 0xff170000 0x0 0x1000>;
 			clock-names = "clk_xin", "clk_ahb";
+			#stream-id-cells = <1>;
+			iommus = <&smmu 0x871>;
 			#clock-cells = <1>;
 			clock-output-names = "clk_out_sd1", "clk_in_sd1";
 			power-domains = <&zynqmp_firmware PD_SD_1>;

@@ -664,6 +715,7 @@ sdhci1: mmc@ff170000 {
 		smmu: iommu@fd800000 {
 			compatible = "arm,mmu-500";
 			reg = <0x0 0xfd800000 0x0 0x20000>;
+			#iommu-cells = <1>;
 			status = "disabled";
 			#global-interrupts = <1>;
 			interrupt-parent = <&gic>;

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Michal Simek

author

2021-01-21 10:30 UTC #13 lore raw

PATCH v2 12/12 arm64: dts: zynqmp: Add description for zcu104 revC

In reply to Michal Simek

Xilinx ZynqMP zcu104 revC and newer board revisions have different i2c structure compare to revA. The rest of the board is the same from software perspective.
Also enable DMAs and QSPI.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/Makefile           |   1 +
 .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 282 ++++++++++++++++++
 2 files changed, 283 insertions(+)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts

arch/arm64/boot/dts/xilinx/Makefile +1 -0

index 60f5443f3ef4..11fb4fd3ebd4 100644
@@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts new file +282 -0

282 lines not on this page · raw message

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Michal Simek

2021-02-01 09:39 UTC #14 lore raw

Re: [PATCH v2 12/12] arm64: dts: zynqmp: Add description for zcu104 revC

Quoted 305 lines · Michal Simek

Xilinx ZynqMP zcu104 revC and newer board revisions have different i2c structure compare to revA. The rest of the board is the same from software perspective.
Also enable DMAs and QSPI.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2: None

 arch/arm64/boot/dts/xilinx/Makefile           |   1 +
 .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 282 ++++++++++++++++++
 2 files changed, 283 insertions(+)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts

arch/arm64/boot/dts/xilinx/Makefile +1 -0

index 60f5443f3ef4..11fb4fd3ebd4 100644
@@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts new file +272 -0

new file mode 100644
index 000000000000..414f98f1831e
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2020, Xilinx, Inc.
+ *
+ * Michal Simek <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+	model = "ZynqMP ZCU104 RevC";
+	compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem3;
+		i2c0 = &i2c1;
+		mmc0 = &sdhci1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &dcc;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	ina226 {
+		compatible = "iio-hwmon";
+		io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
+	};
+
+	clock_8t49n287_5: clk125 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	clock_8t49n287_2: clk26 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+	};
+
+	clock_8t49n287_3: clk27 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+};
+
+&can1 {
+	status = "okay";
+};
+
+&dcc {
+	status = "okay";
+};
+
+&fpd_dma_chan1 {
+	status = "okay";
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+};
+
+&gem3 {
+	status = "okay";
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	phy0: ethernet-phy@c {
+		reg = <0xc>;
+		ti,rx-internal-delay = <0x8>;
+		ti,tx-internal-delay = <0xa>;
+		ti,fifo-depth = <0x1>;
+		ti,dp83867-rxctrl-strap-quirk;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tca6416_u97: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		/*
+		 * IRQ not connected
+		 * Lines:
+		 * 0 - IRPS5401_ALERT_B
+		 * 1 - HDMI_8T49N241_INT_ALM
+		 * 2 - MAX6643_OT_B
+		 * 3 - MAX6643_FANFAIL_B
+		 * 5 - IIC_MUX_RESET_B
+		 * 6 - GEM3_EXP_RESET_B
+		 * 7 - FMC_LPC_PRSNT_M2C_B
+		 * 4, 10 - 17 - not connected
+		 */
+	};
+
+	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
+	i2c-mux@74 { /* u34 */
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			/*
+			 * IIC_EEPROM 1kB memory which uses 256B blocks
+			 * where every block has different address.
+			 *    0 - 256B address 0x54
+			 * 256B - 512B address 0x55
+			 * 512B - 768B address 0x56
+			 * 768B - 1024B address 0x57
+			 */
+			eeprom: eeprom@54 { /* u23 */
+				compatible = "atmel,24c08";
+				reg = <0x54>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+			};
+		};
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
+				reg = <0x6c>;
+			};
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
+				compatible = "infineon,irps5401";
+				reg = <0x43>; /* pmbus / i2c 0x13 */
+			};
+			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
+				compatible = "infineon,irps5401";
+				reg = <0x44>; /* pmbus / i2c 0x14 */
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+			u183: ina226@40 { /* u183 */
+				compatible = "ti,ina226";
+				#io-channel-cells = <1>;
+				reg = <0x40>;
+				shunt-resistor = <5000>;
+			};
+		};
+
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+		};
+
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+		};
+
+		/* 4, 6 not connected */
+	};
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0>;
+	};
+};
+
+&rtc {
+	status = "okay";
+};
+
+&psgtr {
+	status = "okay";
+	/* nc, sata, usb3, dp */
+	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
+	clock-names = "ref1", "ref2", "ref3";
+};
+
+&sata {
+	status = "okay";
+	/* SATA OOB timing settings */
+	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+	status = "okay";
+	no-1-8-v;
+	xlnx,mio-bank = <1>;
+	disable-wp;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts line 282

Quoted 10 lines

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts new file +10 -0
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&watchdog0 {
+	status = "okay";
+};

As I said I applied this but also added revC to Documentation/devicetree/bindings/arm/xilinx.yaml to be listed.

Thanks,
Michal

Signature · 5 lines

Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

Michal Simek

2021-02-01 09:37 UTC #15 lore raw

In reply to Michal Simek

Quoted 32 lines · Michal Simek

Hi,
I am sending this series to reflect the latest drivers which have been merged to mainline kernel. I have boot it on zcu102-rev1.0 and also zcu104-rev1.0. That's why I have also added DT for this newer revision.
The series is based on https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt.
And mio-bank patch requires update in dt-binding which has been posted here
https://lore.kernel.org/r/5fa17dfe4b42abefd84b4cbb7b8bcd4d31398f40.1606914986.git.michal.simek@xilinx.com
Thanks,
Michal
Changes in v2:
- Remove reset description for IPs from this patch. IPs will be enabled separately with DT binding update.
- Change patch subject
Michal Simek (12):
arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111
arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
arm64: dts: zynqmp: Enable reset controller driver
arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
arm64: dts: zynqmp: Add label for zynqmp_ipi
arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis
arm64: dts: zynqmp: Wire arasan nand controller
arm64: dts: zynqmp: Wire zynqmp qspi controller
arm64: dts: zynqmp: Add missing lpd watchdog node
arm64: dts: zynqmp: Add missing iommu IDs
arm64: dts: zynqmp: Add description for zcu104 revC

Quoted 12 lines

 arch/arm64/boot/dts/xilinx/Makefile           |   1 +
 .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi |  12 +
 .../boot/dts/xilinx/zynqmp-zcu100-revC.dts    |   2 +
 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    |  84 +++++-
 .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    |  29 ++
 .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 282 ++++++++++++++++++
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    |  78 +++++
 .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    |  59 +++-
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi        |  94 +++++-
 9 files changed, 637 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts

Applied all.

Thanks,
Michal

Signature · 5 lines

Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs