Convert designware-pcie and kirin-pcie to yaml
Subsystems (15)
cover Convert designware-pcie and kirin-pcie to yaml
Rob,
As I'm preparing some upstream patches for kirin-pcie driver to support Hikey 970, I opted to try first to convert the existing schema to yaml.
It should be noticed that those two patches currently won't pass cleanly with dtbs_check/dt_binding_check.
I'm out of ideas about how to fix. It sounds to me that the checking tools are trying to enforce different types of reference types than the ones used by designware drivers.:
$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/designware,pcie.yaml dt_binding_check LINT Documentation/devicetree/bindings DTEX Documentation/devicetree/bindings/pci/designware,pcie.example.dts CHKDT Documentation/devicetree/bindings/processed-schema-examples.json SCHEMA Documentation/devicetree/bindings/processed-schema-examples.json DTC Documentation/devicetree/bindings/pci/designware,pcie.example.dt.yaml CHECK Documentation/devicetree/bindings/pci/designware,pcie.example.dt.yaml
[[2164260864, 0, 0, 3724541952, 0, 65536, 2181038080, 0, 3493855232, 3493855232, 0, 218103808]] is not of type 'boolean' True was expected [[2164260864, 0, 0, 3724541952, 0, 65536, 2181038080, 0, 3493855232, 3493855232, 0, 218103808]] is not of type 'null' [2164260864, 0, 0, 3724541952, 0, 65536, 2181038080, 0, 3493855232, 3493855232, 0, 218103808] is too long From schema: /home/mchehab/.local/lib/python3.9/site-packages/dtschema/schemas/pci/pci-bus.yaml
$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml dt_binding_check DTEX Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dts DTC Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml CHECK Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml /devel/v4l/hikey970/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: 'reset-gpios' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: /devel/v4l/hikey970/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml /devel/v4l/hikey970/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: '#interrupt-cells', 'bus-range', 'clock-names', 'clocks', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'num-lanes', 'ranges' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: /devel/v4l/hikey970/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
I ran out of ideas about how to solve that. So, I'm posting it as a RFC.
Mauro Carvalho Chehab (2):
dt: pci: designware-pcie.txt: convert it to yaml
dt: pci: kirin-pcie.txt: convert it to yaml
.../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware,pcie.yaml | 194 ++++++++++++++++++ .../bindings/pci/designware-pcie.txt | 77 ------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon,kirin-pcie.yaml | 98 +++++++++ .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos5440-pcie.txt | 4 +- .../pci/socionext,uniphier-pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/ti-pci.txt | 4 +- .../devicetree/bindings/pci/uniphier-pcie.txt | 2 +- MAINTAINERS | 4 +- 20 files changed, 323 insertions(+), 158 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/designware,pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
Signature · 8 lines
2.29.2 _______________________________________________ linux-amlogic mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-amlogic
RFC PATCH 1/2 dt: pci: designware-pcie.txt: convert it to yaml
Convert the file into a JSON description at the yaml format.
--- .../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware,pcie.yaml | 194 ++++++++++++++++++ .../bindings/pci/designware-pcie.txt | 77 ------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 2 +- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos5440-pcie.txt | 4 +- .../pci/socionext,uniphier-pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/ti-pci.txt | 4 +- .../devicetree/bindings/pci/uniphier-pcie.txt | 2 +- MAINTAINERS | 2 +- 19 files changed, 225 insertions(+), 108 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/designware,pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt
Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +2 -2
@@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/designware,pcie.yaml. Additional properties are described here:
@@ -33,7 +33,7 @@ Required properties: - phy-names: must contain "pcie" - device_type: - should be "pci". As specified in designware-pcie.txt + should be "pci". As specified in designware,pcie.yaml Example configuration:
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +1 -1
@@ -1,7 +1,7 @@ * Axis ARTPEC-6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in designware,pcie.yaml. Required properties: - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +194 -0
194 lines not on this page · raw message
Documentation/devicetree/bindings/pci/designware-pcie.txt deleted +0 -77
77 lines not on this page · raw message
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +1 -1
@@ -1,7 +1,7 @@ * Freescale i.MX6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in designware,pcie.yaml. Required properties: - compatible:
Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +1 -1
@@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. It shares common functions with the DesignWare PCIe core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/designware,pcie.yaml. Additional properties are described here:
Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +1 -1
@@ -3,7 +3,7 @@ HiSilicon Hip05 and Hip06 PCIe host bridge DT description HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/designware,pcie.yaml. Additional properties are described here:
Documentation/devicetree/bindings/pci/kirin-pcie.txt +1 -1
@@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/designware,pcie.yaml. Additional properties are described here:
Documentation/devicetree/bindings/pci/layerscape-pci.txt +1 -1
@@ -1,7 +1,7 @@ Freescale Layerscape PCIe controller This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in designware,pcie.yaml. This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset.
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +2 -2
@@ -1,7 +1,7 @@ NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) This PCIe controller is based on the Synopsis Designware PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in designware,pcie.yaml. Some of the controller instances are dual mode where in they can work either in root port mode or endpoint mode but one at a time.
@@ -22,7 +22,7 @@ Required properties: property. - reg-names: Must include the following entries: "appl": Controller's application logic registers - "config": As per the definition in designware-pcie.txt + "config": As per the definition in designware,pcie.yaml "atu_dma": iATU and DMA registers. This is where the iATU (internal Address Translation Unit) registers of the PCIe core are made available for SW access.
Documentation/devicetree/bindings/pci/pci-armada8k.txt +1 -1
@@ -1,7 +1,7 @@ * Marvell Armada 7K/8K PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in designware,pcie.yaml. Required properties: - compatible: "marvell,armada8k-pcie"
Documentation/devicetree/bindings/pci/pci-keystone.txt +5 -5
@@ -3,9 +3,9 @@ TI Keystone PCIe interface Keystone PCI host Controller is based on the Synopsys DesignWare PCI hardware version 3.65. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt +Documentation/devicetree/bindings/pci/designware,pcie.yaml -Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt +Please refer to Documentation/devicetree/bindings/pci/designware,pcie.yaml for the details of DesignWare DT bindings. Additional properties are described here as well as properties that are not applicable.
@@ -82,11 +82,11 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the Address Translation Unit configuration registers and "addr_space" used to map remote RC address space num-ib-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/designware,pcie.yaml num-ob-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/designware,pcie.yaml num-lanes: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/designware,pcie.yaml power-domains: As documented by the generic PM domain bindings in Documentation/devicetree/bindings/power/power_domain.txt. ti,syscon-pcie-mode: phandle to the device control module required to configure
Documentation/devicetree/bindings/pci/pcie-al.txt +1 -1
@@ -2,7 +2,7 @@ Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare PCI core. It inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/designware,pcie.yaml. Properties of the host controller node that differ from it are:
Documentation/devicetree/bindings/pci/qcom,pcie.txt +7 -7
@@ -31,22 +31,22 @@ - device_type: Usage: required Value type: <string> - Definition: Should be "pci". As specified in designware-pcie.txt + Definition: Should be "pci". As specified in designware,pcie.yaml - #address-cells: Usage: required Value type: <u32> - Definition: Should be 3. As specified in designware-pcie.txt + Definition: Should be 3. As specified in designware,pcie.yaml - #size-cells: Usage: required Value type: <u32> - Definition: Should be 2. As specified in designware-pcie.txt + Definition: Should be 2. As specified in designware,pcie.yaml - ranges: Usage: required Value type: <prop-encoded-array> - Definition: As specified in designware-pcie.txt + Definition: As specified in designware,pcie.yaml - interrupts: Usage: required
@@ -61,17 +61,17 @@ - #interrupt-cells: Usage: required Value type: <u32> - Definition: Should be 1. As specified in designware-pcie.txt + Definition: Should be 1. As specified in designware,pcie.yaml - interrupt-map-mask: Usage: required Value type: <prop-encoded-array> - Definition: As specified in designware-pcie.txt + Definition: As specified in designware,pcie.yaml - interrupt-map: Usage: required Value type: <prop-encoded-array> - Definition: As specified in designware-pcie.txt + Definition: As specified in designware,pcie.yaml - clocks: Usage: required
Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt +2 -2
@@ -1,7 +1,7 @@ * Samsung Exynos 5440 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in designware,pcie.yaml. Required properties: - compatible: "samsung,exynos5440-pcie"
@@ -16,7 +16,7 @@ Required properties: Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt For other common properties, refer to - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/designware,pcie.yaml Example:
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +1 -1
@@ -10,7 +10,7 @@ description: | UniPhier PCIe endpoint controller is based on the Synopsys DesignWare PCI core. It shares common features with the PCIe DesignWare core and inherits common properties defined in - Documentation/devicetree/bindings/pci/designware-pcie.txt. + Documentation/devicetree/bindings/pci/designware,pcie.yaml. maintainers: - Kunihiko Hayashi <[email protected]>
Documentation/devicetree/bindings/pci/ti-pci.txt +2 -2
@@ -12,7 +12,7 @@ PCIe DesignWare Controller number of PHYs as specified in *phys* property. - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>", where <X> is the instance number of the pcie from the HW spec. - - num-lanes as specified in ../designware-pcie.txt + - num-lanes as specified in ../designware,pcie.yaml - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the register offset to specify lane selection.
@@ -32,7 +32,7 @@ HOST MODE device_type, ranges, interrupt-map-mask, - interrupt-map : as specified in ../designware-pcie.txt + interrupt-map : as specified in ../designware,pcie.yaml - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument should contain the register offset within syscon and the 2nd argument should contain the bit field
Documentation/devicetree/bindings/pci/uniphier-pcie.txt +1 -1
@@ -6,7 +6,7 @@ on Socionext UniPhier SoCs. UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/designware,pcie.yaml. Required properties: - compatible: Should be "socionext,uniphier-pcie".
MAINTAINERS +1 -1
@@ -13469,7 +13469,7 @@ M: Jingoo Han <[email protected]> M: Gustavo Pimentel <[email protected]> L: [email protected] S: Maintained -F: Documentation/devicetree/bindings/pci/designware-pcie.txt +F: Documentation/devicetree/bindings/pci/designware,pcie.yaml F: drivers/pci/controller/dwc/*designware* PCI DRIVER FOR TI DRA7XX/J721E
Signature · 7 lines
2.29.2 _______________________________________________ linux-amlogic mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-amlogic
Re: [PATCH RFC 1/2] dt: pci: designware-pcie.txt: convert it to yaml
Hi Mauro,
Quoted 19 lines · Mauro Carvalho Chehab
Convert the file into a JSON description at the yaml format.
Signed-off-by Mauro Carvalho Chehab <[email protected]>--- .../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware,pcie.yaml | 194 ++++++++++++++++++ .../bindings/pci/designware-pcie.txt | 77 ------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 2 +- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos5440-pcie.txt | 4 +-
You must have used an old tree for preparing this patchset. The above file is gone in v5.11-rc1 and there is Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml instead.
Quoted 8 lines
.../pci/socionext,uniphier-pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/ti-pci.txt | 4 +- .../devicetree/bindings/pci/uniphier-pcie.txt | 2 +- MAINTAINERS | 2 +- 19 files changed, 225 insertions(+), 108 deletions(-)create mode 100644
Documentation/devicetree/bindings/pci/designware,pcie.yamldelete mode 100644Documentation/devicetree/bindings/pci/designware-pcie.txt
...
Best regards
Signature · 8 lines
Marek Szyprowski, PhD Samsung R&D Institute Poland _______________________________________________ linux-amlogic mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-amlogic
Re: [PATCH RFC 1/2] dt: pci: designware-pcie.txt: convert it to yaml
Hi Marek,
Em Tue, 26 Jan 2021 11:13:20 +0100
Marek Szyprowski <[email protected]> escreveu:
Quoted 23 lines
Hi Mauro,
Quoted 19 lines · Mauro Carvalho Chehab
Convert the file into a JSON description at the yaml format.
Signed-off-by Mauro Carvalho Chehab <[email protected]>--- .../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware,pcie.yaml | 194 ++++++++++++++++++ .../bindings/pci/designware-pcie.txt | 77 ------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 2 +- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos5440-pcie.txt | 4 +-
Quoted 3 lines
You must have used an old tree for preparing this patchset. The above file is gone in v5.11-rc1 and there is
Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yamlinstead.
Yeah, this series was generated against v5.10, as part of my efforts to have Hikey 970 properly supported upstream:
https://github.com/mchehab/linux/commits/devel/hikey970
For the next version, I'll rebase on the top of linux-next.
Thanks,
Mauro
_______________________________________________
linux-amlogic mailing list
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Re: [PATCH RFC 1/2] dt: pci: designware-pcie.txt: convert it to yaml
In reply to Mauro Carvalho ChehabQuoted 2 lines · Mauro Carvalho Chehab
Convert the file into a JSON description at the yaml format.
json-schema, not JSON really. I prefer just 'DT schema' which implies json-schema in yaml file format.
This one is a bit tricky and suspect it needs a few others converted to get right. Not asking for that yet, just keep that in mind.
Quoted 6 lines
Signed-off-by Mauro Carvalho Chehab <[email protected]>--- .../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware,pcie.yaml | 194 ++++++++++++++++++
snps,dw-pcie.yaml
Quoted 39 lines
.../bindings/pci/designware-pcie.txt | 77 ------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 2 +- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos5440-pcie.txt | 4 +- .../pci/socionext,uniphier-pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/ti-pci.txt | 4 +- .../devicetree/bindings/pci/uniphier-pcie.txt | 2 +- MAINTAINERS | 2 +- 19 files changed, 225 insertions(+), 108 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/designware,pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txtDocumentation/devicetree/bindings/pci/designware,pcie.yaml new file +12
-0@@ -0,0 +1,194 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/designware,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare PCIe interface + +maintainers: + - Jingoo Han <[email protected]> + - Gustavo Pimentel <[email protected]> +
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 22
Quoted 10 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +10
-0+description: | + Synopsys DesignWare PCIe host controller + +properties: + compatible: + description: | + The compatible can be either: + - snps,dw-pcie # for RC mode + - snps,dw-pcie-ep # For EP mode + or some other value, when there's a host-specific driver
Needs to be a schema. This is complicated because sometimes it's used and sometimes not. So we need something like this:
anyOf:
- {}
- items:
contains:
enum:
- snps,dw-pcie
- snps,dw-pcie-ep
This will always be true, but at least documents the strings in a parseable form.
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 28
Quoted 6 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +6
-0+ + reg: + description: | + For designware cores version < 4.80 contains the configuration + address space. For designware core version >= 4.80, contains + the configuration and ATU address space
And DBI for all versions.
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 29
Quoted 1 line
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +1
-0+ maxItems: 4
minItems: 2
(dbi and config must always be there)
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 36
Quoted 7 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +7
-0+ + reg-names: + description: | + Must be "config" for the PCIe configuration space and "atu" for + the ATU address space. + (The old way of getting the configuration address space from + "ranges" is deprecated and should be avoided.)
This is getting dropped from the driver and can be dropped here. This only existed for a few months back in 2013.
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 37
Quoted 1 line
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +1
-0+ maxItems: 4
minItems: 2
items:
contains:
enum: [ dbi, dbi2, config, atu ]
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 43
Quoted 6 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +6
-0+ + num-lanes: + description: | + number of lanes to use (this property should be specified unless + the link is brought already up in BIOS) + maxItems: 1
Not an array. IIRC, pci-bus.yaml covers this. If not, needs a type ref and min/max (1-16).
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 46
Quoted 3 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +3
-0+ + reset-gpio: + description: GPIO pin number of power good signal
Isn't this the PERST# signal?
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 53
Quoted 7 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +7
-0+ maxItems: 1 + + clocks: + description: | + Must contain an entry for each entry in clock-names. + See Documentation/devicetree/bindings/clock/clock-bindings.txt for + details.
This is every 'clocks', drop.
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 61
Quoted 8 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +8
-0+ minItems: 2 + maxItems: 8 + + clock-names: + description: | + Must include the following entries: + - "pcie" + - "pcie_bus"
Need to be in a schema.
Quoted 34 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +33
-0+ minItems: 2 + maxItems: 8 + + "snps,enable-cdm-check": + $ref: /schemas/types.yaml#definitions/flag + description: | + This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. + + # The following are mandatory properties for RC Mode + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + device_type: + const: pci + + ranges: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + ranges for the PCI memory and I/O regions + minItems: 1 + maxItems: 8 + + "#interrupt-cells": + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 104
Quoted 10 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +10
-0+ + interrupt-map-mask: + description: | + Standard PCI properties to define the mapping of the PCIe + interface to interrupt numbers. + + interrupt-map: + description: | + Standard PCI properties to define the mapping of the PCIe + interface to interrupt numbers.
pci-bus.yaml already covers these. Drop and reference pci-bus.yaml
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 111
Quoted 7 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +7
-0+ + # The following are optional properties for RC mode + + num-viewport: + description: | + number of view ports configured in hardware. If a platform + does not specify it, the driver assumes 2.
This is detected now and can be marked 'deprecated'.
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 117
Quoted 6 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +6
-0+ + bus-range: + description: | + PCI bus numbers covered (it is recommended for new devicetrees + to specify this property, to keep backwards compatibility a range of + 0x00-0xff is assumed if not present)
Covered by pci-bus.yaml.
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 127
Quoted 10 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +10
-0+ + # The following are mandatory properties for EP Mode + + num-ib-windows: + description: number of inbound address translation windows + maxItems: 1 + + num-ob-windows: + description: number of outbound address translation windows + maxItems: 1
These 2 are detected now and can be marked 'deprecated'.
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 133
Quoted 6 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +6
-0+ + # The following are optional properties for EP mode + + max-functions: + description: maximum number of functions that can be configured + maxItems: 1
Not an array.
Quoted 12 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +12
-0+ +required: + - reg + - reg-names + - compatible + +allOf: + - if: + properties: + compatible: + contains: + const: snps,dw-pcie
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 155
Quoted 10 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +10
-0+ then: + required: + - compatible + - "#address-cells" + - "#size-cells" + - device_type + - ranges + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map
All these are required for all pci hosts.
Quoted 29 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +29
-0+ - if: + properties: + compatible: + contains: + const: snps,dw-pcie-ep + then: + required: + - compatible + - num-ib-windows + - num-ob-windows + +additionalProperties: false + +examples: + - | + pcie: pcie@dfc00000 { + compatible = "snps,dw-pcie"; + reg = <0xdfc00000 0x0001000>, /* IP registers */ + <0xd0000000 0x0002000>; /* Configuration space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000 + 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + interrupts = <25>, <24>; + #interrupt-cells = <1>; + num-lanes = <1>; + };
Documentation/devicetree/bindings/pci/designware,pcie.yaml line 194
Quoted 10 lines
Documentation/devicetree/bindings/pci/designware,pcie.yaml new file +10
-0+ pcie_ep: pcie_ep@dfd00000 { + compatible = "snps,dw-pcie-ep"; + reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ + <0xdfc01000 0x0001000>, /* IP registers 2 */ + <0xd0000000 0x2000000>; /* Configuration space */ + reg-names = "dbi", "dbi2", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-lanes = <1>; + };
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RFC PATCH 2/2 dt: pci: kirin-pcie.txt: convert it to yaml
In reply to Mauro Carvalho ChehabConvert the file into a JSON description at the yaml format.
--- .../bindings/pci/hisilicon,kirin-pcie.yaml | 98 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ---------- MAINTAINERS | 2 +- 3 files changed, 99 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +98 -0
@@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Mauro Carvalho Chehab <[email protected]> + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.yaml. + +properties: + compatible: + const: hisilicon,kirin960-pcie + + reg: + description: | + Should contain rc_dbi, apb, phy, config registers location and length. + + reg-names: + description: | + Must include the following entries: + "dbi": controller configuration registers; + "apb": apb Ctrl register defined by Kirin; + "phy": apb PHY register defined by Kirin; + "config": PCIe configuration space registers. + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reset-gpios: + description: The GPIO to generate PCIe PERST# assert and deassert signal. + maxItems: 1 + +allOf: + - $ref: "designware,pcie.yaml#" + +required: + - compatible + - reg + - reg-names + - reset-gpios + - "#address-cells" + - "#size-cells" + - device_type + - ranges + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/hi3660-clock.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, + <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", + "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; + };
Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted +0 -50
50 lines not on this page · raw message
MAINTAINERS +1 -1
@@ -13611,7 +13611,7 @@ M: Xiaowei Song <[email protected]> M: Binghui Wang <[email protected]> L: [email protected] S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c PCIE DRIVER FOR HISILICON STB
Signature · 1 line
2.29.2
Re: [PATCH RFC 2/2] dt: pci: kirin-pcie.txt: convert it to yaml
Quoted 24 lines · Mauro Carvalho Chehab
Convert the file into a JSON description at the yaml format.
Signed-off-by Mauro Carvalho Chehab <[email protected]>--- .../bindings/pci/hisilicon,kirin-pcie.yaml | 98 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ---------- MAINTAINERS | 2 +- 3 files changed, 99 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txtDocumentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +6
-0@@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 16
Quoted 10 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +10
-0+title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Mauro Carvalho Chehab <[email protected]> + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.yaml.
Drop this and move the $ref to here.
Quoted 6 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +6
-0+ +properties: + compatible: + const: hisilicon,kirin960-pcie + + reg:
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 32
Quoted 10 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +10
-0+ description: | + Should contain rc_dbi, apb, phy, config registers location and length. + + reg-names: + description: | + Must include the following entries: + "dbi": controller configuration registers; + "apb": apb Ctrl register defined by Kirin; + "phy": apb PHY register defined by Kirin; + "config": PCIe configuration space registers.
That needs to be a schema listing the entries.
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 38
Quoted 6 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +6
-0+ + "#address-cells": + const: 3 + + "#size-cells": + const: 2
Covered by pci-bus.yaml.
Quoted 10 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +10
-0+ + reset-gpios: + description: The GPIO to generate PCIe PERST# assert and deassert signal. + maxItems: 1 + +allOf: + - $ref: "designware,pcie.yaml#" + +required: + - compatible
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 58
Quoted 10 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +10
-0+ - reg + - reg-names + - reset-gpios + - "#address-cells" + - "#size-cells" + - device_type + - ranges + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map
pci-bus.yaml covers most of these.
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 60
Quoted 2 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +2
-0+ +additionalProperties: false
This will cause the example to fail (some reason these didn't get picked up by PW). You need to use 'unevaluatedProperties: false' here.
Quoted 110 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +38
-0+ +examples: + - | + #include <dt-bindings/clock/hi3660-clock.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, + <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", + "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; + };Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted +0
-50@@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/designware,pcie.yaml. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC -- reg: Should contain rc_dbi, apb, phy, config registers location and length. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - };MAINTAINERS +1
-2@@ -13611,7 +13611,7 @@ M: Xiaowei Song <[email protected]> M: Binghui Wang <[email protected]> L: [email protected] S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c PCIE DRIVER FOR HISILICON STB --2.29.2
Re: [PATCH RFC 2/2] dt: pci: kirin-pcie.txt: convert it to yaml
Em Tue, 26 Jan 2021 09:49:18 -0600
Rob Herring <[email protected]> escreveu:
Quoted 30 lines
Quoted 28 lines · Mauro Carvalho Chehab
Convert the file into a JSON description at the yaml format.
Signed-off-by Mauro Carvalho Chehab <[email protected]>--- .../bindings/pci/hisilicon,kirin-pcie.yaml | 98 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ---------- MAINTAINERS | 2 +- 3 files changed, 99 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txtDocumentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +10
-0@@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Mauro Carvalho Chehab <[email protected]>
Quoted 8 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 16
Quoted 6 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +6
-0+ +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.yaml.Drop this and move the $ref to here.
That doesn't pass at dt_binding_check. If I do either:
allOf:
- $ref: snps,pcie.yaml#
or:
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: snps,pcie.yaml#
Then dt-binding-check starts to think that this DT is for a pinctrl:
make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64 dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
LINT Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dts
./Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml:10:4: [warning] wrong indentation: expected 2 but found 3 (indentation)
./Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml:102:10: [warning] wrong indentation: expected 10 but found 9 (indentation)
CHKDT Documentation/devicetree/bindings/processed-schema-examples.json
SCHEMA Documentation/devicetree/bindings/processed-schema-examples.json
DTC Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml
CHECK Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml
.../Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: '#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'interrupt-names', 'interrupts', 'num-lanes', 'ranges', 'reg-names', 'reset-gpios' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema: .../Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
No idea why. Perhaps something broken at pinctrl schema?
Thanks,
Mauro
Rob Herring
maintainerRe: [PATCH RFC 2/2] dt: pci: kirin-pcie.txt: convert it to yaml
Quoted 67 lines · Mauro Carvalho Chehab
Em Tue, 26 Jan 2021 09:49:18 -0600
Rob Herring <[email protected]> escreveu:Quoted 30 lines
Quoted 28 lines · Mauro Carvalho Chehab
Convert the file into a JSON description at the yaml format.
Signed-off-by Mauro Carvalho Chehab <[email protected]>--- .../bindings/pci/hisilicon,kirin-pcie.yaml | 98 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ---------- MAINTAINERS | 2 +- 3 files changed, 99 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txtDocumentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +10
-0@@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Mauro Carvalho Chehab <[email protected]>Quoted 8 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml line 16
Quoted 6 lines
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file +6
-0+ +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.yaml.Drop this and move the $ref to here.
That doesn't pass at
dt_binding_check. If I do either:allOf:
- $ref: snps,pcie.yaml#or:
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: snps,pcie.yaml#Then dt-binding-check starts to think that this DT is for a pinctrl:
make CROSS_COMPILE=aarch64-linux-gnu- ARCH=arm64
dt_binding_checkDT_SCHEMA_FILES=Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
LINTDocumentation/devicetree/bindings
DTEXDocumentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dts
./Documentation/devicetree/bindings/sound/mt8192-mt6359-rt1015-rt5682.yaml:10:4: [warning] wrong indentation: expected 2 but found 3 (indentation)
./Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml:102:10: [warning] wrong indentation: expected 10 but found 9 (indentation)
CHKDTDocumentation/devicetree/bindings/processed-schema-examples.json
SCHEMADocumentation/devicetree/bindings/processed-schema-examples.json
DTCDocumentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml
CHECKDocumentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml
.../Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: '#address-cells', '#interrupt-cells', '#size-cells', 'bus-range', 'device_type', 'interrupt-map', 'interrupt-map-mask', 'interrupt-names', 'interrupts', 'num-lanes', 'ranges', 'reg-names', 'reset-gpios' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema:.../Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
Quoted 1 line
No idea why. Perhaps something broken at pinctrl schema?
You'll need to use unevaluatedProperties instead of additionalProperties.
Rob