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Add driver support for Data Capture and Compare Engine(DCC) for SM8150

PATCH In review Souradeep Chowdhury 4 participants 15 messages Feb 17, 2021 – Feb 18, 2021

Subsystems (3)
Device tree bindings Arm Qualcomm mailing list Arm Qualcomm support
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#1 lore raw

PATCH 1/6 dt-bindings: Added the yaml bindings for DCC

In reply to Souradeep Chowdhury

Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format.

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +49 -0
new file mode 100644
index 0000000..8f09578
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Data Capture and Compare
+
+maintainers:
+  - Souradeep Chowdhury <[email protected]>
+
+description: |
+    DCC (Data Capture and Compare) is a DMA engine which is used to save
+    configuration data or system memory contents during catastrophic failure
+    or SW trigger.DCC is used to capture and store data for debugging purpose
+
+
+properties:
+  compatible:
+    items:
+    - enum:
+      - qcom,sm8150-dcc
+    - const: qcom,dcc
+
+  reg:
+    items:
+      - description: DCC base register region
+      - description: DCC RAM base register region
+
+  reg-names:
+    items:
+      - const: dcc-base
+      - const: dcc-ram-base
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+additionalProperties: false
+
+examples:
+  - |
+    dcc@010a2000{
+                compatible = "qcom,sm8150-dcc";
+                reg = <0 0x010a2000 0  0x1000>,
+                      <0 0x010ae000 0  0x2000>;
+                reg-names = "dcc-base", "dcc-ram-base";
+    };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Souradeep Chowdhury

author
#0 lore raw

cover Add driver support for Data Capture and Compare Engine(DCC) for SM8150

DCC(Data Capture and Compare) is a DMA engine designed for debugging purposes.In case of a system crash or manual software triggers by the user the DCC hardware stores the value at the register addresses which can be used for debugging purposes.The DCC driver provides the user with sysfs interface to configure the register addresses.The options that the DCC hardware provides include reading from registers,writing to registers,first reading and then writing to registers and looping through the values of the same register.
In certain cases a register write needs to be executed for
accessing the rest of the registers,also the user might want to recaord the changing values of a particular register with time for which he has the option to use the loop feature. The options mentioned above are exposed to the user by sysfs files once the driver is probed.The details and usage of this sysfs files are documented in Documentation/ABI/testing/sysfs-driver-dcc. As an example if a user wants to configure to store 100 words starting from address 0x80000050 he should give inputs as following to the sysfs config file:-
echo 0x80000050 100 > /sys/bus/platform/devices/.../config
Similarly if he wants to write to a register using DCC hardware he should give following input to config_write sysfs file:-
echo 0x80000000 0xFF > /sys/bus/platform/devices/10a2000.dcc/config_write
This will write the value 0xFF on address 0x80000000.
All this read and write occurs at crash time or if the user manually invokes a software trigger.

Souradeep Chowdhury (6):
dt-bindings: Added the yaml bindings for DCC
arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support
node
soc: qcom: dcc:Add driver support for Data Capture and Compare
unit(DCC)
soc: qcom: dcc:Add the sysfs variables to the Data Capture and Compare
driver(DCC)
DCC:Added the sysfs entries for DCC(Data Capture and Compare) driver MAINTAINERS:Added the entry for DCC(Data Capture and Compare) driver
support

 Documentation/ABI/testing/sysfs-driver-dcc         |   74 +
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      |   49 +
 MAINTAINERS                                        |    8 +
 arch/arm64/boot/dts/qcom/sm8150.dtsi               |    7 +
 drivers/soc/qcom/Kconfig                           |    8 +
 drivers/soc/qcom/Makefile                          |    1 +
 drivers/soc/qcom/dcc.c                             | 1574 ++++++++++++++++++++
 7 files changed, 1721 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
 create mode 100644 drivers/soc/qcom/dcc.c

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

author
#5 lore raw

PATCH 2/6 arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node

Add the DCC(Data Capture and Compare) device tree node entry along with the addresses for register regions.

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/sm8150.dtsi +7 -0
index e5bb17b..3198bd3 100644
@@ -654,6 +654,13 @@
 			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		dcc@010a2000{
+			compatible = "qcom,sm8150-dcc", "qcom,dcc";
+			reg = <0x0 0x010a2000 0x0 0x1000>,
+				<0x0 0x010ad000 0x0 0x3000>;
+			reg-names = "dcc-base", "dcc-ram-base";
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#8 lore raw

PATCH 3/6 soc: qcom: dcc:Add driver support for Data Capture and Compare unit(DCC)

In reply to Souradeep Chowdhury

The DCC is a DMA Engine designed to capture and store data during system crash or software triggers.The DCC operates based on link list entries which provides it with data and addresses and the function it needs to perform.These functions are read,write and loop.Added the basic driver in this patch which contains a probe method which instantiates all the link list data specific to a SoC.Methods have also been added to handle all the functionalities specific to a linked list.Each DCC has it's own SRAM which needs to be instantiated at probe time as well.

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 drivers/soc/qcom/Kconfig  |    8 +
 drivers/soc/qcom/Makefile |    1 +
 drivers/soc/qcom/dcc.c    | 1055 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1064 insertions(+)
 create mode 100644 drivers/soc/qcom/dcc.c
drivers/soc/qcom/Kconfig +8 -0
index 79b568f..8819e0b 100644
@@ -69,6 +69,14 @@ config QCOM_LLCC
 	  SDM845. This provides interfaces to clients that use the LLCC.
 	  Say yes here to enable LLCC slice driver.
 
+config QCOM_DCC
+	tristate "Qualcomm Technologies, Inc. Data Capture and Compare engine driver"
+	depends on ARCH_QCOM || COMPILE_TEST
+	help
+	  This option enables driver for Data Capture and Compare engine. DCC
+	  driver provides interface to configure DCC block and read back
+	  captured data from DCC's internal SRAM.
+
 config QCOM_KRYO_L2_ACCESSORS
 	bool
 	depends on ARCH_QCOM && ARM64 || COMPILE_TEST
drivers/soc/qcom/Makefile +1 -0
index ad675a6..1b00870 100644
@@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
 obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
 obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
+obj-$(CONFIG_QCOM_DCC) += dcc.o
drivers/soc/qcom/dcc.c new file +1055 -0

1,055 lines not on this page · raw message

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#12 lore raw

PATCH 4/6 soc: qcom: dcc:Add the sysfs variables to the Data Capture and Compare driver(DCC)

In reply to Souradeep Chowdhury

Added the sysfs variables to expose the user space functionalities like DCC enable,disable,configure addresses and software triggers. Also added the necessary methods along with the same.

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 drivers/soc/qcom/dcc.c | 519 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 519 insertions(+)
drivers/soc/qcom/dcc.c +519 -0
index d67452b..02eee96 100644
@@ -185,6 +185,82 @@ static int dcc_sram_writel(struct dcc_drvdata *drvdata,
 	return 0;
 }
 
+static bool dcc_ready(struct dcc_drvdata *drvdata)
+{
+	u32 val;
+
+	/* poll until DCC ready */
+	if (!readl_poll_timeout((drvdata->base + DCC_STATUS), val,
+				(BMVAL(val, 0, 1) == 0), 1, TIMEOUT_US))
+		return true;
+
+	return false;
+}
+
+static int dcc_read_status(struct dcc_drvdata *drvdata)
+{
+	int curr_list;
+	u32 bus_status;
+	u32 ll_cfg = 0;
+	u32 tmp_ll_cfg = 0;
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+
+		bus_status = dcc_readl(drvdata, DCC_LL_BUS_ACCESS_STATUS(curr_list));
+
+		if (bus_status) {
+			dev_err(drvdata->dev,
+				"Read access error for list %d err: 0x%x.\n",
+				curr_list, bus_status);
+
+			ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
+			tmp_ll_cfg = ll_cfg & ~BIT(9);
+			dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
+			dcc_writel(drvdata, 0x3,
+				DCC_LL_BUS_ACCESS_STATUS(curr_list));
+			dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
+			return -ENODATA;
+		}
+	}
+
+	return 0;
+}
+
+static int dcc_sw_trigger(struct dcc_drvdata *drvdata)
+{
+	int ret = 0;
+	int curr_list;
+	u32 ll_cfg = 0;
+	u32 tmp_ll_cfg = 0;
+
+	mutex_lock(&drvdata->mutex);
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+		ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list));
+		tmp_ll_cfg = ll_cfg & ~BIT(9);
+		dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list));
+		dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list));
+		dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list));
+	}
+
+	if (!dcc_ready(drvdata)) {
+		dev_err(drvdata->dev,
+			"DCC is busy after receiving sw tigger.\n");
+		ret = -EBUSY;
+		goto err;
+	}
+
+	ret = dcc_read_status(drvdata);
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
 static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata,
 struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg)
 {

@@ -628,6 +704,211 @@ static int dcc_enable(struct dcc_drvdata *drvdata)
 	return ret;
 }
 
+static void dcc_disable(struct dcc_drvdata *drvdata)
+{
+	int curr_list;
+
+	mutex_lock(&drvdata->mutex);
+
+	if (!dcc_ready(drvdata))
+		dev_err(drvdata->dev, "DCC is not ready Disabling DCC...\n");
+
+	for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) {
+		if (!drvdata->enable[curr_list])
+			continue;
+		dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list));
+		dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list));
+		dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list));
+		dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list));
+		drvdata->enable[curr_list] = false;
+	}
+	memset_io(drvdata->ram_base, 0, drvdata->ram_size);
+	drvdata->ram_cfg = 0;
+	drvdata->ram_start = 0;
+	mutex_unlock(&drvdata->mutex);
+}
+
+static ssize_t curr_list_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list == DCC_INVALID_LINK_LIST) {
+		dev_err(dev, "curr_list is not set.\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = scnprintf(buf, PAGE_SIZE, "%d\n",	drvdata->curr_list);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t curr_list_store(struct device *dev,
+						struct device_attribute *attr,
+						const char *buf, size_t size)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	unsigned long val;
+	u32 lock_reg;
+	bool dcc_enable = false;
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val >= drvdata->nr_link_list)
+		return -EINVAL;
+
+	mutex_lock(&drvdata->mutex);
+
+	dcc_enable = is_dcc_enabled(drvdata);
+	if (drvdata->curr_list != DCC_INVALID_LINK_LIST	&& dcc_enable) {
+		dev_err(drvdata->dev, "DCC is enabled, please disable it first.\n");
+		mutex_unlock(&drvdata->mutex);
+		return -EINVAL;
+	}
+
+	lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val));
+	if (lock_reg & 0x1) {
+		dev_err(drvdata->dev, "DCC linked list is already configured\n");
+		mutex_unlock(&drvdata->mutex);
+		return -EINVAL;
+	}
+	drvdata->curr_list = val;
+	mutex_unlock(&drvdata->mutex);
+
+	return size;
+}
+
+static DEVICE_ATTR_RW(curr_list);
+
+
+static ssize_t trigger_store(struct device *dev,
+					struct device_attribute *attr,
+					const char *buf, size_t size)
+{
+	int ret = 0;
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+	if (val != 1)
+		return -EINVAL;
+
+	ret = dcc_sw_trigger(drvdata);
+	if (!ret)
+		ret = size;
+
+	return ret;
+}
+static DEVICE_ATTR_WO(trigger);
+
+static ssize_t enable_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	bool dcc_enable = false;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	dcc_enable = is_dcc_enabled(drvdata);
+
+	ret = scnprintf(buf, PAGE_SIZE, "%u\n",
+				(unsigned int)dcc_enable);
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static ssize_t enable_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	int ret = 0;
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val)
+		ret = dcc_enable(drvdata);
+	else
+		dcc_disable(drvdata);
+
+	if (!ret)
+		ret = size;
+
+	return ret;
+
+}
+
+static DEVICE_ATTR_RW(enable);
+
+static ssize_t config_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	struct dcc_config_entry *entry;
+	char local_buf[64];
+	int len = 0, count = 0;
+
+	buf[0] = '\0';
+
+	mutex_lock(&drvdata->mutex);
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		count = -EINVAL;
+		goto err;
+	}
+
+	list_for_each_entry(entry,
+	&drvdata->cfg_head[drvdata->curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+			len = snprintf(local_buf, 64, "Index: 0x%x, mask: 0x%x, val: 0x%x\n",
+				entry->index, entry->mask, entry->write_val);
+			break;
+		case DCC_LOOP_TYPE:
+			len = snprintf(local_buf, 64, "Index: 0x%x, Loop: %d\n",
+				entry->index, entry->loop_cnt);
+			break;
+		case DCC_WRITE_TYPE:
+			len = snprintf(local_buf, 64,
+				"Write Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
+				entry->index, entry->base, entry->offset, entry->len,
+				entry->apb_bus);
+			break;
+		default:
+			len = snprintf(local_buf, 64,
+				"Read Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n",
+				entry->index, entry->base, entry->offset,
+				entry->len, entry->apb_bus);
+		}
+
+		if ((count + len) > PAGE_SIZE) {
+			dev_err(dev, "DCC: Couldn't write complete config\n");
+			break;
+		}
+		strlcat(buf, local_buf, PAGE_SIZE);
+		count += len;
+	}
+
+err:
+	mutex_unlock(&drvdata->mutex);
+	return count;
+}
+
 static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
 				unsigned int len, int apb_bus)
 {

@@ -709,6 +990,38 @@ static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
 	return ret;
 }
 
+static ssize_t config_store(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t size)
+{
+	int ret, len, apb_bus;
+	unsigned int base;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+	int nval;
+
+	nval = sscanf(buf, "%x %i %d", &base, &len, &apb_bus);
+	if (nval <= 0 || nval > 3)
+		return -EINVAL;
+
+	if (nval == 1) {
+		len = 1;
+		apb_bus = 0;
+	} else if (nval == 2) {
+		apb_bus = 0;
+	} else {
+		apb_bus = 1;
+	}
+
+	ret = dcc_config_add(drvdata, base, len, apb_bus);
+	if (ret)
+		return ret;
+
+	return size;
+
+}
+
+static DEVICE_ATTR_RW(config);
+
 static void dcc_config_reset(struct dcc_drvdata *drvdata)
 {
 	struct dcc_config_entry *entry, *temp;

@@ -730,6 +1043,80 @@ static void dcc_config_reset(struct dcc_drvdata *drvdata)
 	mutex_unlock(&drvdata->mutex);
 }
 
+static ssize_t config_reset_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	if (val)
+		dcc_config_reset(drvdata);
+
+	return size;
+}
+
+static DEVICE_ATTR_WO(config_reset);
+
+static ssize_t ready_show(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	int ret;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (!drvdata->enable[drvdata->curr_list]) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = scnprintf(buf, PAGE_SIZE, "%u\n",
+			(unsigned int)BVAL(dcc_readl(drvdata, DCC_STATUS), 1));
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_RO(ready);
+
+static ssize_t interrupt_disable_show(struct device *dev,
+						struct device_attribute *attr,
+						char *buf)
+{
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n",
+				(unsigned int)drvdata->interrupt_disable);
+}
+
+static ssize_t interrupt_disable_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	unsigned long val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	if (kstrtoul(buf, 16, &val))
+		return -EINVAL;
+
+	mutex_lock(&drvdata->mutex);
+	drvdata->interrupt_disable = (val ? 1:0);
+	mutex_unlock(&drvdata->mutex);
+	return size;
+}
+
+static DEVICE_ATTR_RW(interrupt_disable);
+
 static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt)
 {
 	struct dcc_config_entry *entry;

@@ -747,6 +1134,40 @@ static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt)
 	return 0;
 }
 
+static ssize_t loop_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	int ret;
+	unsigned long loop_cnt;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	if (kstrtoul(buf, 16, &loop_cnt)) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = dcc_add_loop(drvdata, loop_cnt);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&drvdata->mutex);
+	return size;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_WO(loop);
+
 static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask,
 				unsigned int val)
 {

@@ -784,6 +1205,30 @@ static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask,
 	return ret;
 }
 
+static ssize_t rd_mod_wr_store(struct device *dev,
+	struct device_attribute *attr,
+	const char *buf, size_t size)
+{
+	int ret;
+	int nval;
+	unsigned int mask, val;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	nval = sscanf(buf, "%x %x", &mask, &val);
+
+	if (nval <= 1 || nval > 2)
+		return -EINVAL;
+
+	ret = dcc_rd_mod_wr_add(drvdata, mask, val);
+	if (ret)
+		return ret;
+
+	return size;
+
+}
+
+static DEVICE_ATTR_WO(rd_mod_wr);
+
 static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr,
 				unsigned int write_val, int apb_bus)
 {

@@ -806,6 +1251,77 @@ static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr,
 	return 0;
 }
 
+static ssize_t config_write_store(struct device *dev,
+						struct device_attribute *attr,
+						const char *buf, size_t size)
+{
+	int ret;
+	int nval;
+	unsigned int addr, write_val;
+	int apb_bus = 0;
+	struct dcc_drvdata *drvdata = dev_get_drvdata(dev);
+
+	mutex_lock(&drvdata->mutex);
+
+	nval = sscanf(buf, "%x %x %d", &addr, &write_val, &apb_bus);
+
+	if (nval <= 1 || nval > 3) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (drvdata->curr_list >= drvdata->nr_link_list) {
+		dev_err(dev, "Select link list to program using curr_list\n");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (nval == 3 && apb_bus != 0)
+		apb_bus = 1;
+
+	ret = dcc_add_write(drvdata, addr, write_val, apb_bus);
+	if (ret)
+		goto err;
+
+	mutex_unlock(&drvdata->mutex);
+	return size;
+err:
+	mutex_unlock(&drvdata->mutex);
+	return ret;
+}
+
+static DEVICE_ATTR_WO(config_write);
+
+static const struct device_attribute *dcc_attrs[] = {
+	&dev_attr_trigger,
+	&dev_attr_enable,
+	&dev_attr_config,
+	&dev_attr_config_reset,
+	&dev_attr_ready,
+	&dev_attr_interrupt_disable,
+	&dev_attr_loop,
+	&dev_attr_rd_mod_wr,
+	&dev_attr_curr_list,
+	&dev_attr_config_write,
+	NULL,
+};
+
+static int dcc_create_files(struct device *dev,
+					const struct device_attribute **attrs)
+{
+	int ret = 0, i;
+
+	for (i = 0; attrs[i] != NULL; i++) {
+		ret = device_create_file(dev, attrs[i]);
+		if (ret) {
+			dev_err(dev, "DCC: Couldn't create sysfs attribute: %s\n",
+				attrs[i]->attr.name);
+			break;
+		}
+	}
+	return ret;
+}
+
 static int dcc_sram_open(struct inode *inode, struct file *file)
 {
 	struct dcc_drvdata *drvdata = container_of(inode->i_cdev,

@@ -1018,6 +1534,9 @@ static int dcc_probe(struct platform_device *pdev)
 	ret = dcc_sram_dev_init(drvdata);
 	if (ret)
 		goto err;
+	ret = dcc_create_files(dev, dcc_attrs);
+	if (ret)
+		goto err;
 
 	return ret;
 err:
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#13 lore raw

PATCH 5/6 DCC:Added the sysfs entries for DCC(Data Capture and Compare) driver

In reply to Souradeep Chowdhury

The DCC is a DMA engine designed to store register values either in case of a system crash or in case of software triggers manually done by the user.Using DCC hardware and the sysfs interface of the driver the user can exploit various functionalities of DCC.The user can specify the register addresses,the values of which is stored by DCC in it's dedicated SRAM.The register addresses can be used either to read from, write to,first read and store value and then write or to loop.All these options can be exploited using the sysfs interface given to the user. Following are the sysfs interfaces exposed in DCC driver which are documented
1)trigger
2)config
3)config_write
4)config_reset
5)enable
6)rd_mod_wr
7)loop

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 Documentation/ABI/testing/sysfs-driver-dcc | 74 ++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc
Documentation/ABI/testing/sysfs-driver-dcc new file +74 -0
new file mode 100644
index 0000000..7a855ca
@@ -0,0 +1,74 @@
+What:           /sys/bus/platform/devices/.../trigger
+Date:           February 2021
+Contact:        Souradeep Chowdhury <[email protected]>
+Description:
+		This file allows the software trigger to be enabled
+		by the user through the sysfs interface.Through this
+		interface the user can manually start a software trigger
+		in dcc where by the dcc driver stores the current status
+		of the specified registers in dcc sram.
+
+What:           /sys/bus/platform/devices/.../enable
+Date:           February 2021
+Contact:        Souradeep Chowdhury <[email protected]>
+Description:
+		This file allows the user to manually enable or
+		disable dcc driver.The dcc hardware needs to be
+		enabled before use.
+
+What:           /sys/bus/platform/devices/.../config
+Date:           February 2021
+Contact:        Souradeep Chowdhury <[email protected]>
+Description:
+		This file allows user to configure the register values
+		along with addresses to the dcc driver.This register
+		addresses are used to read from,write or loop through.
+		To enable all these options separate sysfs files have
+		are created.
+
+What:           /sys/bus/platform/devices/.../config_write
+Date:           February 2021
+Contact:        Souradeep Chowdhury <[email protected]>
+Description:
+		This file allows user to write a value to the register
+		address given as argument.The values are entered in the
+		form of <register_address> <value>.
+
+What:           /sys/bus/platform/devices/.../config_reset
+Date:           February 2021
+Contact:        Souradeep Chowdhury <[email protected]>
+Description:
+		This file is used to reset the configuration of
+		a dcc driver to the default configuration.
+
+What:           /sys/bus/platform/devices/.../loop
+Date:           February 2021
+Contact:        Souradeep Chowdhury <[email protected]>
+Description:
+		This file is used to enter the loop count as dcc
+		driver gives the option to loop multiple times on
+		the same register and store the values for each
+		loop.
+
+What:           /sys/bus/platform/devices/.../rd_mod_wr
+Date:           February 2021
+Contact:        Souradeep Chowdhury <[email protected]>
+Description:
+		This file is used to read the value of the register
+		and then write the value given as an argument to the
+		register address in config.The address argument should
+		be given of the form <mask> <value>.
+
+What:           /sys/bus/platform/devices/.../ready
+Date:           February 2021
+Contact:        Souradeep Chowdhury <[email protected]>
+Description:
+		This file is used to check the status of the dcc
+		hardware if it's ready to take the inputs.
+
+What:		/sys/bus/platform/devices/.../curr_list
+Date:		February 2021
+Contact:	Souradeep Chowdhury <[email protected]>
+Description:
+		This file is used to configure the linkedlist data
+		to be used while configuring addresses.
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#14 lore raw

PATCH 6/6 MAINTAINERS:Added the entry for DCC(Data Capture and Compare) driver support

In reply to Souradeep Chowdhury

Added the entries for all the files added as a part of driver support for DCC(Data Capture and Compare).

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)
MAINTAINERS +8 -0
index 546aa66..f0d208a 100644
@@ -4931,6 +4931,14 @@ F:	include/linux/tfrc.h
 F:	include/uapi/linux/dccp.h
 F:	net/dccp/
 
+QUALCOMM DCC DRIVER
+M:	Souradeep Chowdhury <[email protected]>
+L:	[email protected]
+S:	Maintained
+F:	Documentation/ABI/testing/sysfs-driver-dcc
+F:	Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
+F:	drivers/soc/qcom/dcc.c
+
 DECnet NETWORK LAYER
 L:	[email protected]
 S:	Orphan
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
build bot
#9 lore raw

Re: [PATCH V0 3/6] soc: qcom: dcc:Add driver support for Data Capture and Compare unit(DCC)

In reply to Souradeep Chowdhury
Thank you for the patch! Perhaps something to improve:

Hi Souradeep,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v5.11 next-20210216] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Souradeep-Chowdhury/Add-driver-support-for-Data-Capture-and-Compare-Engine-DCC-for-SM8150/20210217-145428
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 9.3.0

reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/98f7664a4e41764c0d2111d6b17905d974aad65d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Souradeep-Chowdhury/Add-driver-support-for-Data-Capture-and-Compare-Engine-DCC-for-SM8150/20210217-145428 git checkout 98f7664a4e41764c0d2111d6b17905d974aad65d
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc

If you fix the issue, kindly add following tag as appropriate

Reported-by kernel test robot <[email protected]>

All warnings (new ones prefixed by >>):

drivers/soc/qcom/dcc.c: In function '_dcc_ll_cfg_default':

>> drivers/soc/qcom/dcc.c:360:4: warning: this 'if' clause does not guard... [-Wmisleading-indentation]
     360 |    if (ret)
         |    ^~
   drivers/soc/qcom/dcc.c:362:5: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
     362 |     cfg->sram_offset += 4;
         |     ^~~

At top level:
drivers/soc/qcom/dcc.c:787:12: warning: 'dcc_add_write' defined but not used [-Wunused-function]
787 | static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr,
| ^~~~~~~~~~~~~
drivers/soc/qcom/dcc.c:750:12: warning: 'dcc_rd_mod_wr_add' defined but not used [-Wunused-function]
750 | static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask,
| ^~~~~~~~~~~~~~~~~
drivers/soc/qcom/dcc.c:733:12: warning: 'dcc_add_loop' defined but not used [-Wunused-function]
733 | static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt)
| ^~~~~~~~~~~~
drivers/soc/qcom/dcc.c:631:12: warning: 'dcc_config_add' defined but not used [-Wunused-function]
631 | static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr,
| ^~~~~~~~~~~~~~
drivers/soc/qcom/dcc.c:574:12: warning: 'dcc_enable' defined but not used [-Wunused-function]
574 | static int dcc_enable(struct dcc_drvdata *drvdata)
| ^~~~~~~~~~

vim +/if +360 drivers/soc/qcom/dcc.c

338
339 static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
340 struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg, u32 *pos, u32 *total_len)
341 {
342 int ret = 0;
343 u32 off;
344
345 cfg->addr = (entry->base >> 4) & BM(0, 27);
346
347 if (entry->apb_bus)
348 cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND;
349 else
350 cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND;
351
352 off = entry->offset/4;
353
354 *total_len += entry->len * 4;
355
356 if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) {
357 /* Check if we need to write prev link entry */
358 if (cfg->link) {
359 ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);

 > 360				if (ret)

361 return ret;
362 cfg->sram_offset += 4;
363 }
364 dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset);
365
366 /* Write address */
367 ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
368
369 if (ret)
370 return ret;
371
372 cfg->sram_offset += 4;
373
374 /* Reset link and prev_off */
375 cfg->link = 0;
376 cfg->prev_off = 0;
377 }
378
379 if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
380 dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n",
381 entry->base, entry->offset);
382 ret = -EINVAL;
383 return ret;
384 }
385
386 if (cfg->link) {
387 /*
388 * link already has one offset-length so new
389 * offset-length needs to be placed at
390 * bits [29:15]
391 */
392 *pos = 15;
393
394 /* Clear bits [31:16] */
395 cfg->link &= BM(0, 14);
396 } else {
397 /*
398 * link is empty, so new offset-length needs
399 * to be placed at bits [15:0]
400 */
401 *pos = 0;
402 cfg->link = 1 << 15;
403 }
404
405 /* write new offset-length pair to correct position */
406 cfg->link |= (((off-cfg->prev_off) & BM(0, 7)) | ((entry->len << 8) & BM(8, 14))) << *pos;
407
408 cfg->link |= DCC_LINK_DESCRIPTOR;
409
410 if (*pos) {
411 ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
412 if (ret)
413 return ret;
414 cfg->sram_offset += 4;
415 cfg->link = 0;
416 }
417
418 cfg->prev_off = off + entry->len - 1;
419 cfg->prev_addr = cfg->addr;
420 return ret;
421 }
422

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

#2 lore raw

Re: [PATCH V0 1/6] dt-bindings: Added the yaml bindings for DCC

In reply to Souradeep Chowdhury
Quoted 20 lines · Souradeep Chowdhury

Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format.

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +5 -0
new file mode 100644
index 0000000..8f09578
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#

Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml line 15

Quoted 10 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +10 -0
+
+title: Data Capture and Compare
+
+maintainers:
+  - Souradeep Chowdhury <[email protected]>
+
+description: |
+    DCC (Data Capture and Compare) is a DMA engine which is used to save
+    configuration data or system memory contents during catastrophic failure
+    or SW trigger.DCC is used to capture and store data for debugging purpose

space after .

Quoted 8 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +8 -0
+
+
+properties:
+  compatible:
+    items:
+    - enum:
+      - qcom,sm8150-dcc
+    - const: qcom,dcc

Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml line 33

Quoted 10 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +10 -0
+
+  reg:
+    items:
+      - description: DCC base register region
+      - description: DCC RAM base register region
+
+  reg-names:
+    items:
+      - const: dcc-base
+      - const: dcc-ram-base

drop dcc from names

Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml line 45

Quoted 12 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +12 -0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+additionalProperties: false
+
+examples:
+  - |
+    dcc@010a2000{
+                compatible = "qcom,sm8150-dcc";

should this not be:

                compatible = "qcom,sm8150-dcc", "qcom,dcc";
Quoted 7 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +4 -0
+                reg = <0 0x010a2000 0  0x1000>,
+                      <0 0x010ae000 0  0x2000>;
+                reg-names = "dcc-base", "dcc-ram-base";
+    };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Signature · 1 line
~Vinod
#6 lore raw

Re: [PATCH V0 2/6] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node

In reply to Souradeep Chowdhury
Quoted 2 lines · Souradeep Chowdhury

Add the DCC(Data Capture and Compare) device tree node entry along with the addresses for register regions.

This should be last patch..

Quoted 11 lines
Signed-off-by Souradeep Chowdhury <[email protected]>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/sm8150.dtsi +0 -0
index e5bb17b..3198bd3 100644

arch/arm64/boot/dts/qcom/sm8150.dtsi line 657

Quoted 4 lines
arch/arm64/boot/dts/qcom/sm8150.dtsi +1 -0
@@ -654,6 +654,13 @@
 			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		dcc@010a2000{

no leading zero here and space before {

arch/arm64/boot/dts/qcom/sm8150.dtsi line 660

Quoted 3 lines
arch/arm64/boot/dts/qcom/sm8150.dtsi +3 -0
+			compatible = "qcom,sm8150-dcc", "qcom,dcc";
+			reg = <0x0 0x010a2000 0x0 0x1000>,
+				<0x0 0x010ad000 0x0 0x3000>;

pls align this to preceding line

Quoted 9 lines
arch/arm64/boot/dts/qcom/sm8150.dtsi +3 -0
+			reg-names = "dcc-base", "dcc-ram-base";
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Signature · 1 line
~Vinod
author
#7 lore raw

Re: [PATCH V0 2/6] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node

Hi,

Please find the replies inline.

Quoted 5 lines · Vinod Koul
Quoted 2 lines · Souradeep Chowdhury

Add the DCC(Data Capture and Compare) device tree node entry along with the addresses for register regions.

This should be last patch..

Ack

Quoted 15 lines
Quoted 15 lines
Signed-off-by Souradeep Chowdhury <[email protected]>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/qcom/sm8150.dtsi +0 -0
index e5bb17b..3198bd3 100644
@@ -654,6 +654,13 @@
 			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 		};
Quoted 3 lines

arch/arm64/boot/dts/qcom/sm8150.dtsi line 657

Quoted 1 line
arch/arm64/boot/dts/qcom/sm8150.dtsi +1 -0
+		dcc@010a2000{

no leading zero here and space before {

Ack

Quoted 6 lines

arch/arm64/boot/dts/qcom/sm8150.dtsi line 660

Quoted 4 lines
arch/arm64/boot/dts/qcom/sm8150.dtsi +3 -0
+			compatible = "qcom,sm8150-dcc", "qcom,dcc";
+			reg = <0x0 0x010a2000 0x0 0x1000>,
+				<0x0 0x010ad000 0x0 0x3000>;

pls align this to preceding line

Ack

Quoted 10 lines
Quoted 10 lines
arch/arm64/boot/dts/qcom/sm8150.dtsi +3 -1
+			reg-names = "dcc-base", "dcc-ram-base";
+		};
+
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 				     "jedec,ufs-2.0";
--

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

author
#3 lore raw

Re: [PATCH V0 1/6] dt-bindings: Added the yaml bindings for DCC

In reply to Vinod Koul
Quoted 30 lines · Vinod Koul
Quoted 29 lines · Souradeep Chowdhury

Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format.

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 
++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644

Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml

Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +12 -0
new file mode 100644
index 0000000..8f09578
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Data Capture and Compare
+
+maintainers:
+  - Souradeep Chowdhury <[email protected]>
+
+description: |
Quoted 8 lines
Quoted 6 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +1 -0
+    DCC (Data Capture and Compare) is a DMA engine which is used to

save
+ configuration data or system memory contents during catastrophic
failure
+ or SW trigger.DCC is used to capture and store data for debugging
purpose

space after .

Ack

Quoted 13 lines
Quoted 13 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +12 -0
+
+
+properties:
+  compatible:
+    items:
+    - enum:
+      - qcom,sm8150-dcc
+    - const: qcom,dcc
+
+  reg:
+    items:
+      - description: DCC base register region
Quoted 8 lines

Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml line 33

Quoted 6 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +6 -0
+      - description: DCC RAM base register region
+
+  reg-names:
+    items:
+      - const: dcc-base
+      - const: dcc-ram-base

drop dcc from names

Since DCC has a dedicated SRAM, this has been named like this as only base and ram-base are generic names. Let me know if this is still required to be changed.

Quoted 15 lines

Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml line 45

Quoted 13 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +12 -0
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+additionalProperties: false
+
+examples:
+  - |
+    dcc@010a2000{
+                compatible = "qcom,sm8150-dcc";

should this not be:

Quoted 1 line
                compatible = "qcom,sm8150-dcc", "qcom,dcc";

Ack

Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file +4 -1
+                reg = <0 0x010a2000 0  0x1000>,
+                      <0 0x010ae000 0  0x2000>;
+                reg-names = "dcc-base", "dcc-ram-base";
+    };
--

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

maintainer
#4 lore raw

Re: [PATCH V0 1/6] dt-bindings: Added the yaml bindings for DCC

In reply to Souradeep Chowdhury
Quoted 9 lines · Souradeep Chowdhury

Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format.

Signed-off-by Souradeep Chowdhury <[email protected]>
---
 .../devicetree/bindings/arm/msm/qcom,dcc.yaml      | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml:21:5: [warning] wrong indentation: expected 6 but found 4 (indentation) ./Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml:22:7: [warning] wrong indentation: expected 8 but found 6 (indentation)

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/arm/msm/qcom,dcc.example.dts:19.21-24.11: Warning (unit_address_format): /example-0/dcc@010a2000: unit name should not have leading 0s /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/msm/qcom,dcc.example.dt.yaml: example-0: dcc@010a2000:reg:0: [0, 17440768, 0, 4096] is too long
From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/msm/qcom,dcc.example.dt.yaml: example-0: dcc@010a2000:reg:1: [0, 17489920, 0, 8192] is too long
From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/msm/qcom,dcc.example.dt.yaml: dcc@010a2000: compatible: ['qcom,sm8150-dcc'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml

See https://patchwork.ozlabs.org/patch/1441182

This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:

pip3 install dtschema --upgrade

Please check and re-submit.

#10 lore raw

Re: [PATCH V0 3/6] soc: qcom: dcc:Add driver support for Data Capture and Compare unit(DCC)

In reply to Souradeep Chowdhury
Quoted 2 lines · Souradeep Chowdhury

The DCC is a DMA Engine designed to capture and store data during system crash or software triggers.The DCC operates

                                        ^^^

Space after . (quite a few here, pls fix them)

Quoted 8 lines

based on link list entries which provides it with data and addresses and the function it needs to perform.These functions are read,write and loop.Added the basic driver in this patch which contains a probe method which instantiates all the link list data specific to a SoC.Methods have also been added to handle all the functionalities specific to a linked list.Each DCC has it's own SRAM which needs to be instantiated at probe time as well.

So help me understand, in case of system crash how will this be used..?

Quoted 56 lines
Signed-off-by Souradeep Chowdhury <[email protected]>
---
 drivers/soc/qcom/Kconfig  |    8 +
 drivers/soc/qcom/Makefile |    1 +
 drivers/soc/qcom/dcc.c    | 1055 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1064 insertions(+)
 create mode 100644 drivers/soc/qcom/dcc.c
drivers/soc/qcom/Kconfig +8 -0
index 79b568f..8819e0b 100644
@@ -69,6 +69,14 @@ config QCOM_LLCC
 	  SDM845. This provides interfaces to clients that use the LLCC.
 	  Say yes here to enable LLCC slice driver.
 
+config QCOM_DCC
+	tristate "Qualcomm Technologies, Inc. Data Capture and Compare engine driver"
+	depends on ARCH_QCOM || COMPILE_TEST
+	help
+	  This option enables driver for Data Capture and Compare engine. DCC
+	  driver provides interface to configure DCC block and read back
+	  captured data from DCC's internal SRAM.
+
 config QCOM_KRYO_L2_ACCESSORS
 	bool
 	depends on ARCH_QCOM && ARM64 || COMPILE_TEST
drivers/soc/qcom/Makefile +1 -0
index ad675a6..1b00870 100644
@@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
 obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
 obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
+obj-$(CONFIG_QCOM_DCC) += dcc.o
drivers/soc/qcom/dcc.c new file +13 -0
new file mode 100644
index 0000000..d67452b
@@ -0,0 +1,1055 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/bitops.h>
+#include <linux/cdev.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>

drivers/soc/qcom/dcc.c line 23

Quoted 10 lines
drivers/soc/qcom/dcc.c new file +10 -0
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+#define TIMEOUT_US		100
+
+#define BM(lsb, msb)		((BIT(msb) - BIT(lsb)) + BIT(msb))
+#define BMVAL(val, lsb, msb)	((val & BM(lsb, msb)) >> lsb)
+#define BVAL(val, n)		((val & BIT(n)) >> n)

Pls use macros available in bitfield.h rather than inventing your own..

Quoted 38 lines
drivers/soc/qcom/dcc.c new file +38 -0
+
+#define dcc_writel(drvdata, val, off)					\
+	writel((val), drvdata->base + dcc_offset_conv(drvdata, off))
+#define dcc_readl(drvdata, off)						\
+	readl(drvdata->base + dcc_offset_conv(drvdata, off))
+
+#define dcc_sram_readl(drvdata, off)					\
+	readl(drvdata->ram_base + off)
+
+/* DCC registers */
+#define DCC_HW_INFO					0x04
+#define DCC_LL_NUM_INFO					0x10
+#define DCC_STATUS					0x1C
+#define DCC_LL_LOCK(m)					(0x34 + 0x80 * m)
+#define DCC_LL_CFG(m)					(0x38 + 0x80 * m)
+#define DCC_LL_BASE(m)					(0x3c + 0x80 * m)
+#define DCC_FD_BASE(m)					(0x40 + 0x80 * m)
+#define DCC_LL_TIMEOUT(m)				(0x44 + 0x80 * m)
+#define DCC_LL_INT_ENABLE(m)				(0x4C + 0x80 * m)
+#define DCC_LL_INT_STATUS(m)				(0x50 + 0x80 * m)
+#define DCC_LL_SW_TRIGGER(m)				(0x60 + 0x80 * m)
+#define DCC_LL_BUS_ACCESS_STATUS(m)			(0x64 + 0x80 * m)
+
+#define DCC_MAP_LEVEL1			0x18
+#define DCC_MAP_LEVEL2			0x34
+#define DCC_MAP_LEVEL3			0x4C
+
+#define DCC_MAP_OFFSET1			0x10
+#define DCC_MAP_OFFSET2			0x18
+#define DCC_MAP_OFFSET3			0x1C
+#define DCC_MAP_OFFSET4			0x8
+
+#define DCC_FIX_LOOP_OFFSET		16
+#define DCC_VER_INFO_BIT		9
+
+#define DCC_READ        0
+#define DCC_WRITE       1
+#define DCC_LOOP        2

drivers/soc/qcom/dcc.c line 71

Quoted 10 lines
drivers/soc/qcom/dcc.c new file +10 -0
+#define DCC_READ_WRITE  3
+
+#define MAX_DCC_OFFSET				(0xFF * 4)
+#define MAX_DCC_LEN				0x7F
+#define MAX_LOOP_CNT				0xFF
+
+#define DCC_ADDR_DESCRIPTOR			0x00
+#define DCC_LOOP_DESCRIPTOR			(BIT(30))
+#define DCC_RD_MOD_WR_DESCRIPTOR		(BIT(31))
+#define DCC_LINK_DESCRIPTOR			(BIT(31) | BIT(30))

we have GENMASK() for this

drivers/soc/qcom/dcc.c line 83

Quoted 12 lines
drivers/soc/qcom/dcc.c new file +12 -0
+
+#define DCC_READ_IND				0x00
+#define DCC_WRITE_IND				(BIT(28))
+
+#define DCC_AHB_IND				0x00
+#define DCC_APB_IND				BIT(29)
+
+#define DCC_MAX_LINK_LIST			8
+#define DCC_INVALID_LINK_LIST			0xFF
+
+#define DCC_VER_MASK1				0x7F
+#define DCC_VER_MASK2				0x3F

Genmask for these too...

drivers/soc/qcom/dcc.c line 93

Quoted 10 lines
drivers/soc/qcom/dcc.c new file +10 -0
+
+#define DCC_RD_MOD_WR_ADDR                      0xC105E
+
+struct qcom_dcc_config {
+	const int dcc_ram_offset;
+};
+
+static const struct qcom_dcc_config sm8150_cfg = {
+	.dcc_ram_offset				= 0x5000,
+};

maybe move it down near compatible table?

Quoted 86 lines
drivers/soc/qcom/dcc.c new file +86 -0
+
+enum dcc_descriptor_type {
+	DCC_ADDR_TYPE,
+	DCC_LOOP_TYPE,
+	DCC_READ_WRITE_TYPE,
+	DCC_WRITE_TYPE
+};
+
+enum dcc_mem_map_ver {
+	DCC_MEM_MAP_VER1,
+	DCC_MEM_MAP_VER2,
+	DCC_MEM_MAP_VER3
+};
+
+struct dcc_config_entry {
+	u32				base;
+	u32				offset;
+	u32				len;
+	u32				index;
+	u32				loop_cnt;
+	u32				write_val;
+	u32				mask;
+	bool				apb_bus;
+	enum dcc_descriptor_type	desc_type;
+	struct list_head		list;
+};
+
+struct dcc_drvdata {
+	void __iomem		*base;
+	u32			reg_size;
+	struct device		*dev;
+	struct mutex		mutex;
+	void __iomem		*ram_base;
+	u32			ram_size;
+	u32			ram_offset;
+	enum dcc_mem_map_ver	mem_map_ver;
+	u32			ram_cfg;
+	u32			ram_start;
+	bool			*enable;
+	bool			*configured;
+	bool			interrupt_disable;
+	char			*sram_node;
+	struct cdev		sram_dev;
+	struct class		*sram_class;
+	struct list_head	*cfg_head;
+	u32			*nr_config;
+	u32			nr_link_list;
+	u8			curr_list;
+	u8			loopoff;
+};
+
+struct dcc_cfg_attr {
+	u32	addr;
+	u32	prev_addr;
+	u32	prev_off;
+	u32	link;
+	u32	sram_offset;
+};
+
+struct dcc_cfg_loop_attr {
+	u32	loop;
+	bool	loop_start;
+	u32	loop_cnt;
+	u32	loop_len;
+	u32	loop_off;
+};
+
+static u32 dcc_offset_conv(struct dcc_drvdata *drvdata, u32 off)
+{
+	if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL3)
+			return (off - DCC_MAP_OFFSET3);
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET2);
+		else if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL1)
+			return (off - DCC_MAP_OFFSET1);
+	} else if (drvdata->mem_map_ver == DCC_MEM_MAP_VER2) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET4);
+	}
+	return off;
+}
+
+static int dcc_sram_writel(struct dcc_drvdata *drvdata,
+					u32 val, u32 off)
+{

drivers/soc/qcom/dcc.c line 189

Quoted 10 lines
drivers/soc/qcom/dcc.c new file +10 -0
+	if (unlikely(off > (drvdata->ram_size - 4)))
+		return -EINVAL;
+
+	writel((val), drvdata->ram_base + off);
+
+	return 0;
+}
+
+static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata,
+struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg)

this looks a bit hard to read, can you make it better (also you can go upto 100 chars now), do you checkpatch with --strict option to get better alignment of code

drivers/soc/qcom/dcc.c line 191

Quoted 2 lines
drivers/soc/qcom/dcc.c new file +2 -0
+{
+	int ret = 0;

Superfluous init?

drivers/soc/qcom/dcc.c line 195

Quoted 4 lines
drivers/soc/qcom/dcc.c new file +4 -0
+
+	if (cfg->link) {
+		/* write new offset = 1 to continue
+		 * processing the list

kernel uses:
/*
* this is a
* multi line comment style
*/

drivers/soc/qcom/dcc.c line 205

Quoted 10 lines
drivers/soc/qcom/dcc.c new file +10 -0
+		 */
+
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		cfg->addr = 0x00;
+		cfg->link = 0;
+		cfg->prev_off = 0;

memset cfg first?

drivers/soc/qcom/dcc.c line 212

Quoted 7 lines
drivers/soc/qcom/dcc.c new file +7 -0
+		cfg->prev_addr = cfg->addr;
+	}
+
+	cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR;
+
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+

drop this empty line

Quoted 16 lines
drivers/soc/qcom/dcc.c new file +16 -0
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->mask, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+
+	if (ret)
+		return ret;

drivers/soc/qcom/dcc.c line 238

Quoted 10 lines
drivers/soc/qcom/dcc.c new file +10 -0
+
+	cfg->sram_offset += 4;
+
+	cfg->addr = 0;
+
+	return ret;
+}
+
+static int _dcc_ll_cfg_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry,
+struct dcc_cfg_attr *cfg, struct dcc_cfg_loop_attr *cfg_loop, u32 *total_len)

here as well

Quoted 18 lines
drivers/soc/qcom/dcc.c new file +18 -0
+{
+
+	int ret = 0;
+
+	/* Check if we need to write link of prev entry */
+	if (cfg->link) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+	}
+
+	if (cfg_loop->loop_start) {
+		cfg_loop->loop = (cfg->sram_offset - cfg_loop->loop_off) / 4;
+		cfg_loop->loop |= (cfg_loop->loop_cnt << drvdata->loopoff) &
+		BM(drvdata->loopoff, 27);
+		cfg_loop->loop |= DCC_LOOP_DESCRIPTOR;
+		*total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt;

drivers/soc/qcom/dcc.c line 266

Quoted 10 lines
drivers/soc/qcom/dcc.c new file +10 -0
+
+		ret = dcc_sram_writel(drvdata, cfg_loop->loop, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+
+		cfg_loop->loop_start = false;
+		cfg_loop->loop_len = 0;
+		cfg_loop->loop_off = 0;

seems quite similar to last one..? Maybe a helper for common code

Quoted 164 lines
drivers/soc/qcom/dcc.c new file +164 -0
+	} else {
+		cfg_loop->loop_start = true;
+		cfg_loop->loop_cnt = entry->loop_cnt - 1;
+		cfg_loop->loop_len = *total_len;
+		cfg_loop->loop_off = cfg->sram_offset;
+	}
+
+	/* Reset link and prev_off */
+
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	cfg->prev_off = 0;
+	cfg->prev_addr = cfg->addr;
+
+	return ret;
+}
+
+static int _dcc_ll_cfg_write(struct dcc_drvdata *drvdata,
+struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg, u32 *total_len)
+{
+	u32 off;
+	int ret = 0;
+
+	if (cfg->link) {
+		/* write new offset = 1 to continue
+		 * processing the list
+		 */
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		cfg->addr = 0x00;
+		cfg->prev_off = 0;
+		cfg->prev_addr = cfg->addr;
+	}
+
+	off = entry->offset/4;
+	/* write new offset-length pair to correct position */
+	cfg->link |= ((off & BM(0, 7)) | BIT(15) | ((entry->len << 8) & BM(8, 14)));
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	/* Address type */
+	cfg->addr = (entry->base >> 4) & BM(0, 27);
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND;
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	return ret;
+}
+
+static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
+struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg, u32 *pos, u32 *total_len)
+{
+	int ret = 0;
+	u32 off;
+
+	cfg->addr = (entry->base >> 4) & BM(0, 27);
+
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND;
+
+	off = entry->offset/4;
+
+	*total_len += entry->len * 4;
+
+	if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) {
+		/* Check if we need to write prev link entry */
+		if (cfg->link) {
+			ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+			if (ret)
+				return ret;
+				cfg->sram_offset += 4;
+		}
+		dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset);
+
+		/* Write address */
+		ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+
+		/* Reset link and prev_off */
+		cfg->link = 0;
+		cfg->prev_off = 0;
+	}
+
+	if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
+		dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n",
+		entry->base, entry->offset);
+		ret = -EINVAL;
+		return ret;
+	}
+
+	if (cfg->link) {
+		/*
+		 * link already has one offset-length so new
+		 * offset-length needs to be placed at
+		 * bits [29:15]
+		 */
+		*pos = 15;
+
+		/* Clear bits [31:16] */
+		cfg->link &= BM(0, 14);
+	} else {
+		/*
+		 * link is empty, so new offset-length needs
+		 * to be placed at bits [15:0]
+		 */
+		*pos = 0;
+		cfg->link = 1 << 15;
+	}
+
+	/* write new offset-length pair to correct position */
+	cfg->link |= (((off-cfg->prev_off) & BM(0, 7)) | ((entry->len << 8) & BM(8, 14))) << *pos;
+
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	if (*pos) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		cfg->link = 0;
+	}
+
+	cfg->prev_off  = off + entry->len - 1;
+	cfg->prev_addr = cfg->addr;
+	return ret;
+}
+
+static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list)
+{
+	int ret = 0;
+	u32 total_len, pos;
+	struct dcc_config_entry *entry;
+	struct dcc_cfg_attr cfg;
+	struct dcc_cfg_loop_attr cfg_loop;
+

drivers/soc/qcom/dcc.c line 440

Quoted 10 lines
drivers/soc/qcom/dcc.c new file +10 -0
+	cfg.sram_offset = drvdata->ram_cfg * 4;
+	cfg.prev_off = 0;
+	cfg_loop.loop_off = 0;
+	total_len = 0;
+	cfg_loop.loop_len = 0;
+	cfg_loop.loop_cnt = 0;
+	cfg_loop.loop_start = false;
+	cfg.prev_addr = 0;
+	cfg.addr = 0;
+	cfg.link = 0;

again use memset for these

drivers/soc/qcom/dcc.c line 445

Quoted 5 lines
drivers/soc/qcom/dcc.c new file +5 -0
+
+	list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+		{

checkpatch should have told you this is not typical kernel style, pls fix this and many other things before we process further

Signature · 6 lines
~Vinod

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
author
#11 lore raw

Re: [PATCH V0 3/6] soc: qcom: dcc:Add driver support for Data Capture and Compare unit(DCC)

Quoted 5 lines · Vinod Koul
Quoted 2 lines · Souradeep Chowdhury

The DCC is a DMA Engine designed to capture and store data during system crash or software triggers.The DCC operates

                                        ^^^

Space after . (quite a few here, pls fix them)

Ack

Quoted 11 lines
Quoted 9 lines

based on link list entries which provides it with data and addresses and the function it needs to perform.These functions are read,write and loop.Added the basic driver in this patch which contains a probe method which instantiates all the link list data specific to a SoC.Methods have also been added to handle all the functionalities specific to a linked list.Each DCC has it's own SRAM which needs to be instantiated at probe time as well.

So help me understand, in case of system crash how will this be used..?

In case of system crashes like secure WDog bite, the DCC hardware captures and stores the values at the configured register addresses in it's dedicated SRAM. The driver only enables the DCC hardware during probe time and configures register addresses via user space.

Quoted 65 lines
Quoted 65 lines
Signed-off-by Souradeep Chowdhury <[email protected]>
---
 drivers/soc/qcom/Kconfig  |    8 +
 drivers/soc/qcom/Makefile |    1 +
 drivers/soc/qcom/dcc.c    | 1055 
+++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1064 insertions(+)
 create mode 100644 drivers/soc/qcom/dcc.c
drivers/soc/qcom/Kconfig +2 -0
index 79b568f..8819e0b 100644
@@ -69,6 +69,14 @@ config QCOM_LLCC
 	  SDM845. This provides interfaces to clients that use the LLCC.
 	  Say yes here to enable LLCC slice driver.
 
+config QCOM_DCC
+	tristate "Qualcomm Technologies, Inc. Data Capture and Compare

engine driver"

drivers/soc/qcom/Kconfig +3 -0
+	depends on ARCH_QCOM || COMPILE_TEST
+	help
+	  This option enables driver for Data Capture and Compare engine.

DCC

drivers/soc/qcom/Kconfig +3 -0
+	  driver provides interface to configure DCC block and read back
+	  captured data from DCC's internal SRAM.
+
 config QCOM_KRYO_L2_ACCESSORS
 	bool
 	depends on ARCH_QCOM && ARM64 || COMPILE_TEST
drivers/soc/qcom/Makefile +1 -0
index ad675a6..1b00870 100644
@@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
 obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
 obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
 obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
+obj-$(CONFIG_QCOM_DCC) += dcc.o
drivers/soc/qcom/dcc.c new file +3 -0
new file mode 100644
index 0000000..d67452b
@@ -0,0 +1,1055 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights

reserved.
+ */

drivers/soc/qcom/dcc.c new file +13 -0
+
+#include <linux/bitops.h>
+#include <linux/cdev.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
Quoted 8 lines

drivers/soc/qcom/dcc.c line 23

Quoted 6 lines
drivers/soc/qcom/dcc.c new file +6 -0
+
+#define TIMEOUT_US		100
+
+#define BM(lsb, msb)		((BIT(msb) - BIT(lsb)) + BIT(msb))
+#define BMVAL(val, lsb, msb)	((val & BM(lsb, msb)) >> lsb)
+#define BVAL(val, n)		((val & BIT(n)) >> n)

Pls use macros available in bitfield.h rather than inventing your own..

Ack

Quoted 43 lines
Quoted 43 lines
drivers/soc/qcom/dcc.c new file +42 -0
+
+#define dcc_writel(drvdata, val, off)					\
+	writel((val), drvdata->base + dcc_offset_conv(drvdata, off))
+#define dcc_readl(drvdata, off)						\
+	readl(drvdata->base + dcc_offset_conv(drvdata, off))
+
+#define dcc_sram_readl(drvdata, off)					\
+	readl(drvdata->ram_base + off)
+
+/* DCC registers */
+#define DCC_HW_INFO					0x04
+#define DCC_LL_NUM_INFO					0x10
+#define DCC_STATUS					0x1C
+#define DCC_LL_LOCK(m)					(0x34 + 0x80 * m)
+#define DCC_LL_CFG(m)					(0x38 + 0x80 * m)
+#define DCC_LL_BASE(m)					(0x3c + 0x80 * m)
+#define DCC_FD_BASE(m)					(0x40 + 0x80 * m)
+#define DCC_LL_TIMEOUT(m)				(0x44 + 0x80 * m)
+#define DCC_LL_INT_ENABLE(m)				(0x4C + 0x80 * m)
+#define DCC_LL_INT_STATUS(m)				(0x50 + 0x80 * m)
+#define DCC_LL_SW_TRIGGER(m)				(0x60 + 0x80 * m)
+#define DCC_LL_BUS_ACCESS_STATUS(m)			(0x64 + 0x80 * m)
+
+#define DCC_MAP_LEVEL1			0x18
+#define DCC_MAP_LEVEL2			0x34
+#define DCC_MAP_LEVEL3			0x4C
+
+#define DCC_MAP_OFFSET1			0x10
+#define DCC_MAP_OFFSET2			0x18
+#define DCC_MAP_OFFSET3			0x1C
+#define DCC_MAP_OFFSET4			0x8
+
+#define DCC_FIX_LOOP_OFFSET		16
+#define DCC_VER_INFO_BIT		9
+
+#define DCC_READ        0
+#define DCC_WRITE       1
+#define DCC_LOOP        2
+#define DCC_READ_WRITE  3
+
+#define MAX_DCC_OFFSET				(0xFF * 4)
+#define MAX_DCC_LEN				0x7F
Quoted 8 lines

drivers/soc/qcom/dcc.c line 71

Quoted 6 lines
drivers/soc/qcom/dcc.c new file +6 -0
+#define MAX_LOOP_CNT				0xFF
+
+#define DCC_ADDR_DESCRIPTOR			0x00
+#define DCC_LOOP_DESCRIPTOR			(BIT(30))
+#define DCC_RD_MOD_WR_DESCRIPTOR		(BIT(31))
+#define DCC_LINK_DESCRIPTOR			(BIT(31) | BIT(30))

we have GENMASK() for this

Ack

Quoted 15 lines

drivers/soc/qcom/dcc.c line 83

Quoted 13 lines
drivers/soc/qcom/dcc.c new file +12 -0
+
+#define DCC_READ_IND				0x00
+#define DCC_WRITE_IND				(BIT(28))
+
+#define DCC_AHB_IND				0x00
+#define DCC_APB_IND				BIT(29)
+
+#define DCC_MAX_LINK_LIST			8
+#define DCC_INVALID_LINK_LIST			0xFF
+
+#define DCC_VER_MASK1				0x7F
+#define DCC_VER_MASK2				0x3F

Genmask for these too...

Ack

Quoted 13 lines

drivers/soc/qcom/dcc.c line 93

Quoted 11 lines
drivers/soc/qcom/dcc.c new file +10 -0
+
+#define DCC_RD_MOD_WR_ADDR                      0xC105E
+
+struct qcom_dcc_config {
+	const int dcc_ram_offset;
+};
+
+static const struct qcom_dcc_config sm8150_cfg = {
+	.dcc_ram_offset				= 0x5000,
+};

maybe move it down near compatible table?

Ack

Quoted 93 lines
Quoted 93 lines
drivers/soc/qcom/dcc.c new file +92 -0
+
+enum dcc_descriptor_type {
+	DCC_ADDR_TYPE,
+	DCC_LOOP_TYPE,
+	DCC_READ_WRITE_TYPE,
+	DCC_WRITE_TYPE
+};
+
+enum dcc_mem_map_ver {
+	DCC_MEM_MAP_VER1,
+	DCC_MEM_MAP_VER2,
+	DCC_MEM_MAP_VER3
+};
+
+struct dcc_config_entry {
+	u32				base;
+	u32				offset;
+	u32				len;
+	u32				index;
+	u32				loop_cnt;
+	u32				write_val;
+	u32				mask;
+	bool				apb_bus;
+	enum dcc_descriptor_type	desc_type;
+	struct list_head		list;
+};
+
+struct dcc_drvdata {
+	void __iomem		*base;
+	u32			reg_size;
+	struct device		*dev;
+	struct mutex		mutex;
+	void __iomem		*ram_base;
+	u32			ram_size;
+	u32			ram_offset;
+	enum dcc_mem_map_ver	mem_map_ver;
+	u32			ram_cfg;
+	u32			ram_start;
+	bool			*enable;
+	bool			*configured;
+	bool			interrupt_disable;
+	char			*sram_node;
+	struct cdev		sram_dev;
+	struct class		*sram_class;
+	struct list_head	*cfg_head;
+	u32			*nr_config;
+	u32			nr_link_list;
+	u8			curr_list;
+	u8			loopoff;
+};
+
+struct dcc_cfg_attr {
+	u32	addr;
+	u32	prev_addr;
+	u32	prev_off;
+	u32	link;
+	u32	sram_offset;
+};
+
+struct dcc_cfg_loop_attr {
+	u32	loop;
+	bool	loop_start;
+	u32	loop_cnt;
+	u32	loop_len;
+	u32	loop_off;
+};
+
+static u32 dcc_offset_conv(struct dcc_drvdata *drvdata, u32 off)
+{
+	if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL3)
+			return (off - DCC_MAP_OFFSET3);
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET2);
+		else if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL1)
+			return (off - DCC_MAP_OFFSET1);
+	} else if (drvdata->mem_map_ver == DCC_MEM_MAP_VER2) {
+		if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2)
+			return (off - DCC_MAP_OFFSET4);
+	}
+	return off;
+}
+
+static int dcc_sram_writel(struct dcc_drvdata *drvdata,
+					u32 val, u32 off)
+{
+	if (unlikely(off > (drvdata->ram_size - 4)))
+		return -EINVAL;
+
+	writel((val), drvdata->ram_base + off);
+
+	return 0;
Quoted 8 lines

drivers/soc/qcom/dcc.c line 189

Quoted 4 lines
drivers/soc/qcom/dcc.c new file +4 -0
+}
+
+static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata,
+struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg)

this looks a bit hard to read, can you make it better (also you can go upto 100 chars now), do you checkpatch with --strict option to get better alignment of code

Ack

Quoted 6 lines

drivers/soc/qcom/dcc.c

Quoted 4 lines
drivers/soc/qcom/dcc.c new file +2 -0
+{
+	int ret = 0;

Superfluous init?

Ack

Quoted 11 lines

drivers/soc/qcom/dcc.c line 195

Quoted 5 lines
drivers/soc/qcom/dcc.c new file +4 -0
+
+	if (cfg->link) {
+		/* write new offset = 1 to continue
+		 * processing the list

kernel uses:
/*
* this is a
* multi line comment style
*/

Ack

Quoted 13 lines

drivers/soc/qcom/dcc.c line 205

Quoted 11 lines
drivers/soc/qcom/dcc.c new file +10 -0
+		 */
+
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		cfg->addr = 0x00;
+		cfg->link = 0;
+		cfg->prev_off = 0;

memset cfg first?

Ack

Quoted 10 lines

drivers/soc/qcom/dcc.c line 212

Quoted 8 lines
drivers/soc/qcom/dcc.c new file +7 -0
+		cfg->prev_addr = cfg->addr;
+	}
+
+	cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR;
+
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+

drop this empty line

Ack

Quoted 23 lines
Quoted 23 lines
drivers/soc/qcom/dcc.c new file +22 -0
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->mask, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+
+	cfg->addr = 0;
+
+	return ret;
Quoted 8 lines
Quoted 6 lines
drivers/soc/qcom/dcc.c new file +3 -0
+}
+
+static int _dcc_ll_cfg_loop(struct dcc_drvdata *drvdata, struct

dcc_config_entry *entry,
+struct dcc_cfg_attr *cfg, struct dcc_cfg_loop_attr *cfg_loop, u32 *total_len)

here as well

Ack

Quoted 24 lines
Quoted 24 lines
drivers/soc/qcom/dcc.c new file +18 -0
+{
+
+	int ret = 0;
+
+	/* Check if we need to write link of prev entry */
+	if (cfg->link) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+	}
+
+	if (cfg_loop->loop_start) {
+		cfg_loop->loop = (cfg->sram_offset - cfg_loop->loop_off) / 4;
+		cfg_loop->loop |= (cfg_loop->loop_cnt << drvdata->loopoff) &
+		BM(drvdata->loopoff, 27);
+		cfg_loop->loop |= DCC_LOOP_DESCRIPTOR;
+		*total_len += (*total_len - cfg_loop->loop_len) *

cfg_loop->loop_cnt;

drivers/soc/qcom/dcc.c new file +4 -0
+
+		ret = dcc_sram_writel(drvdata, cfg_loop->loop, cfg->sram_offset);
+
+		if (ret)
Quoted 8 lines

drivers/soc/qcom/dcc.c line 266

Quoted 6 lines
drivers/soc/qcom/dcc.c new file +6 -0
+			return ret;
+		cfg->sram_offset += 4;
+
+		cfg_loop->loop_start = false;
+		cfg_loop->loop_len = 0;
+		cfg_loop->loop_off = 0;

seems quite similar to last one..? Maybe a helper for common code

Ack

Quoted 176 lines
Quoted 176 lines
drivers/soc/qcom/dcc.c new file +19 -0
+	} else {
+		cfg_loop->loop_start = true;
+		cfg_loop->loop_cnt = entry->loop_cnt - 1;
+		cfg_loop->loop_len = *total_len;
+		cfg_loop->loop_off = cfg->sram_offset;
+	}
+
+	/* Reset link and prev_off */
+
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	cfg->prev_off = 0;
+	cfg->prev_addr = cfg->addr;
+
+	return ret;
+}
+
+static int _dcc_ll_cfg_write(struct dcc_drvdata *drvdata,
+struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg, u32

*total_len)

drivers/soc/qcom/dcc.c new file +23 -0
+{
+	u32 off;
+	int ret = 0;
+
+	if (cfg->link) {
+		/* write new offset = 1 to continue
+		 * processing the list
+		 */
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+		/* Reset link and prev_off */
+		cfg->addr = 0x00;
+		cfg->prev_off = 0;
+		cfg->prev_addr = cfg->addr;
+	}
+
+	off = entry->offset/4;
+	/* write new offset-length pair to correct position */
+	cfg->link |= ((off & BM(0, 7)) | BIT(15) | ((entry->len << 8) &

BM(8, 14)));

drivers/soc/qcom/dcc.c new file +32 -0
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	/* Address type */
+	cfg->addr = (entry->base >> 4) & BM(0, 27);
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND;
+	ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+	if (ret)
+		return ret;
+	cfg->sram_offset += 4;
+
+	ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset);
+
+	if (ret)
+		return ret;
+
+	cfg->sram_offset += 4;
+	cfg->addr = 0x00;
+	cfg->link = 0;
+	return ret;
+}
+
+static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata,
+struct dcc_config_entry *entry, struct dcc_cfg_attr *cfg, u32 *pos,

u32 *total_len)

drivers/soc/qcom/dcc.c new file +16 -0
+{
+	int ret = 0;
+	u32 off;
+
+	cfg->addr = (entry->base >> 4) & BM(0, 27);
+
+	if (entry->apb_bus)
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND;
+	else
+		cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND;
+
+	off = entry->offset/4;
+
+	*total_len += entry->len * 4;
+
+	if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off
Quoted 1 line

off) {

drivers/soc/qcom/dcc.c new file +8 -0
+		/* Check if we need to write prev link entry */
+		if (cfg->link) {
+			ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+			if (ret)
+				return ret;
+				cfg->sram_offset += 4;
+		}
+		dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n",

cfg->sram_offset);

drivers/soc/qcom/dcc.c new file +16 -0
+
+		/* Write address */
+		ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset);
+
+		if (ret)
+			return ret;
+
+		cfg->sram_offset += 4;
+
+		/* Reset link and prev_off */
+		cfg->link = 0;
+		cfg->prev_off = 0;
+	}
+
+	if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) {
+		dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset

0x%x\n",

drivers/soc/qcom/dcc.c new file +26 -0
+		entry->base, entry->offset);
+		ret = -EINVAL;
+		return ret;
+	}
+
+	if (cfg->link) {
+		/*
+		 * link already has one offset-length so new
+		 * offset-length needs to be placed at
+		 * bits [29:15]
+		 */
+		*pos = 15;
+
+		/* Clear bits [31:16] */
+		cfg->link &= BM(0, 14);
+	} else {
+		/*
+		 * link is empty, so new offset-length needs
+		 * to be placed at bits [15:0]
+		 */
+		*pos = 0;
+		cfg->link = 1 << 15;
+	}
+
+	/* write new offset-length pair to correct position */
+	cfg->link |= (((off-cfg->prev_off) & BM(0, 7)) | ((entry->len << 8)

& BM(8, 14))) << *pos;

drivers/soc/qcom/dcc.c new file +28 -0
+
+	cfg->link |= DCC_LINK_DESCRIPTOR;
+
+	if (*pos) {
+		ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset);
+		if (ret)
+			return ret;
+		cfg->sram_offset += 4;
+		cfg->link = 0;
+	}
+
+	cfg->prev_off  = off + entry->len - 1;
+	cfg->prev_addr = cfg->addr;
+	return ret;
+}
+
+static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list)
+{
+	int ret = 0;
+	u32 total_len, pos;
+	struct dcc_config_entry *entry;
+	struct dcc_cfg_attr cfg;
+	struct dcc_cfg_loop_attr cfg_loop;
+
+	cfg.sram_offset = drvdata->ram_cfg * 4;
+	cfg.prev_off = 0;
+	cfg_loop.loop_off = 0;
+	total_len = 0;
Quoted 8 lines

drivers/soc/qcom/dcc.c line 440

Quoted 6 lines
drivers/soc/qcom/dcc.c new file +6 -0
+	cfg_loop.loop_len = 0;
+	cfg_loop.loop_cnt = 0;
+	cfg_loop.loop_start = false;
+	cfg.prev_addr = 0;
+	cfg.addr = 0;
+	cfg.link = 0;

again use memset for these

Ack

Quoted 9 lines

drivers/soc/qcom/dcc.c line 445

Quoted 6 lines
drivers/soc/qcom/dcc.c new file +5 -0
+
+	list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) {
+		switch (entry->desc_type) {
+		case DCC_READ_WRITE_TYPE:
+		{

checkpatch should have told you this is not typical kernel style, pls fix this and many other things before we process further

Checkpatch with --strict option has been run for these patches but it seems to be not detecting these. They have been fixed now.