Add SiFive FU740 PCIe host controller driver support
Subsystems (9)
Greentime Hu
maintainerv2 cover Add SiFive FU740 PCIe host controller driver support
This patchset includes SiFive FU740 PCIe host controller driver. We also add pcie_aux clock and pcie_power_on_reset controller to prci driver for PCIe driver to use it.
This is tested with e1000e: Intel(R) PRO/1000 Network Card, AMD Radeon R5 230 graphics card and SP M.2 PCIe Gen 3 SSD in SiFive Unmatched based on v5.11 Linux kernel.
Changes in v2:
- Refine codes based on reviewers' feedback
- Remove define and use the common one
- Replace __raw_writel with writel_relaxed
- Split fu740_phyregreadwrite to write function
- Use readl_poll_timeout in stead of while loop checking
- Use dwc common codes
- Use gpio descriptors and the gpiod_* api.
- Replace devm_ioremap_resource with devm_platform_ioremap_resource_byname
- Replace devm_reset_control_get with devm_reset_control_get_exclusive
- Add more comments for delay and sleep
- Remove "phy ? x : y" expressions
- Refine code logic to remove possible infinite loop
- Replace magic number with meaningful define
- Remove fu740_pcie_pm_ops
- Use builtin_platform_driver
Greentime Hu (5):
clk: sifive: Add pcie_aux clock in prci driver for PCIe driver
clk: sifive: Use reset-simple in prci driver for PCIe driver
MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver
dt-bindings: PCI: Add SiFive FU740 PCIe host controller
riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
Paul Walmsley (1):
PCI: fu740: Add SiFive FU740 PCIe host controller driver
.../bindings/pci/sifive,fu740-pcie.yaml | 119 +++++++ MAINTAINERS | 8 + arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++ drivers/clk/sifive/Kconfig | 2 + drivers/clk/sifive/fu740-prci.c | 11 + drivers/clk/sifive/fu740-prci.h | 2 +- drivers/clk/sifive/sifive-prci.c | 54 +++ drivers/clk/sifive/sifive-prci.h | 13 + drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-fu740.c | 324 ++++++++++++++++++ drivers/reset/Kconfig | 3 +- include/dt-bindings/clock/sifive-fu740-prci.h | 1 + 13 files changed, 579 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-fu740.c
Signature · 1 line
2.30.2
Greentime Hu
maintainerPATCH v2 1/6 clk: sifive: Add pcie_aux clock in prci driver for PCIe driver
We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock.
--- drivers/clk/sifive/fu740-prci.c | 11 +++++ drivers/clk/sifive/fu740-prci.h | 2 +- drivers/clk/sifive/sifive-prci.c | 41 +++++++++++++++++++ drivers/clk/sifive/sifive-prci.h | 9 ++++ include/dt-bindings/clock/sifive-fu740-prci.h | 1 + 5 files changed, 63 insertions(+), 1 deletion(-)
drivers/clk/sifive/fu740-prci.c +11 -0
@@ -72,6 +72,12 @@ static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, }; +static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { + .enable = sifive_prci_pcie_aux_clock_enable, + .disable = sifive_prci_pcie_aux_clock_disable, + .is_enabled = sifive_prci_pcie_aux_clock_is_enabled, +}; +/* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu740[] = { [PRCI_CLK_COREPLL ] = {
@@ -120,4 +126,9 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .parent_name = "hfpclkpll", .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, }, + [PRCI_CLK_PCIE_AUX] = { + .name = "pcie_aux", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_pcie_aux_clk_ops, + }, };
drivers/clk/sifive/fu740-prci.h +1 -1
@@ -9,7 +9,7 @@#include "sifive-prci.h" -#define NUM_CLOCK_FU740 8 +#define NUM_CLOCK_FU740 9extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740 ];
drivers/clk/sifive/sifive-prci.c +41 -0
47 lines not on this page · raw message
drivers/clk/sifive/sifive-prci.h +9 -0
@@ -67,6 +67,11 @@#define PRCI_DDRPLLCFG1_CKE_SHIFT 31#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) +/* PCIEAUX */ +#define PRCI_PCIE_AUX_OFFSET 0x14 +#define PRCI_PCIE_AUX_EN_SHIFT 0 +#define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT) +/* GEMGXLPLLCFG0 */ #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
@@ -296,4 +301,8 @@ unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,unsigned long sifive_prci_hfpclkplldiv_recalc_rate (struct clk_hw *hw,unsigned long parent_rate); +int sifive_prci_pcie_aux_clock_is_enabled (struct clk_hw *hw); +int sifive_prci_pcie_aux_clock_enable (struct clk_hw *hw); +void sifive_prci_pcie_aux_clock_disable (struct clk_hw *hw); +#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
include/dt-bindings/clock/sifive-fu740-prci.h +1 -0
@@ -19,5 +19,6 @@#define PRCI_CLK_CLTXPLL 5#define PRCI_CLK_TLCLK 6#define PRCI_CLK_PCLK 7 +#define PRCI_CLK_PCIE_AUX 8#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
Signature · 1 line
2.30.2
Greentime Hu
maintainerPATCH v2 2/6 clk: sifive: Use reset-simple in prci driver for PCIe driver
In reply to Greentime HuWe use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n.
--- drivers/clk/sifive/Kconfig | 2 ++ drivers/clk/sifive/sifive-prci.c | 13 +++++++++++++ drivers/clk/sifive/sifive-prci.h | 4 ++++ drivers/reset/Kconfig | 3 ++- 4 files changed, 21 insertions(+), 1 deletion(-)
drivers/clk/sifive/Kconfig +2 -0
@@ -10,6 +10,8 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" + select RESET_CONTROLLER + select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in
drivers/clk/sifive/sifive-prci.c +13 -0
@@ -583,6 +583,19 @@ static int sifive_prci_probe(struct platform_device *pdev)if (IS_ERR (pd->va))return PTR_ERR (pd->va); + pd->reset.rcdev.owner =THIS_MODULE ; + pd->reset.rcdev.nr_resets =PRCI_RST_NR ; + pd->reset.rcdev.ops = &reset_simple_ops; + pd->reset.rcdev.of_node = pdev->dev.of_node; + pd->reset.active_low = true; + pd->reset.membase = pd->va +PRCI_DEVICESRESETREG_OFFSET ; +spin_lock_init (&pd->reset.lock); + + r =devm_reset_controller_register (&pdev->dev, &pd->reset.rcdev); +if (r) { +dev_err (dev,"could not register reset controller: %d\n" , r); +return r; + } r =__prci_register_clocks (dev, pd, desc);if (r) {dev_err (dev,"could not register clocks: %d\n" , r);
drivers/clk/sifive/sifive-prci.h +4 -0
@@ -11,6 +11,7 @@#include <linux/clk/analogbits-wrpll-cln28hpc.h> #include <linux/clk-provider.h> +#include <linux/reset/reset-simple.h> #include <linux/platform_device.h> /*
@@ -121,6 +122,8 @@#define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) +#define PRCI_RST_NR 7 +/* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
@@ -221,6 +224,7 @@*/ struct __prci_data {void __iomem *va; +struct reset_simple_data reset;struct clk_hw_onecell_data hw_clks; };
drivers/reset/Kconfig +2 -1
@@ -173,7 +173,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC || RISCV help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous,
@@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST
Signature · 7 lines
2.30.2 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Stephen Boyd
maintainerRe: [PATCH v2 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver
Quoting Greentime Hu (2021-03-17 23:08:09)
drivers/reset/Kconfig config RESET_SCMI · line 176
Quoted 10 lines
drivers/reset/Kconfig +1
-1@@ -173,7 +173,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC || RISCV
This conflicts. Can this default be part of the riscv defconfig instead?
Quoted 11 lines
drivers/reset/Kconfig +1
-0help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous,@@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST
Greentime Hu
maintainerRe: [PATCH v2 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver
Stephen Boyd <[email protected]> 於 2021年3月30日 週二 上午3:14寫道：
Quoted 8 lines
Quoting Greentime Hu (2021-03-17 23:08:09)
Quoted 6 lines
drivers/reset/Kconfig +0
-0@@ -173,7 +173,7 @@ config RESET_SCMI
Quoted 7 lines
drivers/reset/Kconfig config RESET_SCMI · line 176
Quoted 4 lines
drivers/reset/Kconfig +1
-1config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC || RISCVThis conflicts. Can this default be part of the riscv defconfig instead?
Maybe I should remove this since it has been selected by CLK_SIFIVE_PRCI?
config CLK_SIFIVE_PRCI
bool "PRCI driver for SiFive SoCs"
+ select RESET_CONTROLLER
+ select RESET_SIMPLE
Quoted 11 lines
drivers/reset/Kconfig config RESET_SIMPLE · line 193
Quoted 11 lines
drivers/reset/Kconfig +1
-0help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous,@@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST
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Palmer Dabbelt
maintainerRe: [PATCH v2 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver
Quoted 21 lines · On Mon, 29 Mar 2021 20:36:12 PDT (-0700), [email protected] wrote:
Stephen Boyd <[email protected]> 於 2021年3月30日 週二 上午3:14寫道：
Quoted 8 lines
Quoting Greentime Hu (2021-03-17 23:08:09)
Quoted 6 lines
drivers/reset/Kconfig +0
-0@@ -173,7 +173,7 @@ config RESET_SCMIQuoted 7 lines
drivers/reset/Kconfig config RESET_SCMI · line 176
Quoted 4 lines
drivers/reset/Kconfig +1
-1config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC || RISCVThis conflicts. Can this default be part of the riscv defconfig instead?
Maybe I should remove this since it has been selected by
CLK_SIFIVE_PRCI?config
CLK_SIFIVE_PRCI
bool "PRCI driver for SiFive SoCs"
drivers/clk/sifive/Kconfig if CLK_SIFIVE · line 14
Quoted 2 lines
drivers/clk/sifive/Kconfig +2
-0+ select RESET_CONTROLLER + select RESET_SIMPLE
Ya, that's better. IIRC I suggested something similar in some other version, but I might have not actually sent the mail.
Quoted 10 lines
Quoted 10 lines
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drivers/reset/Kconfig +1
-0help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous,@@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs
Quoted 2 lines
Quoted 2 lines
drivers/reset/Kconfig config RESET_SIMPLE · line 193
Quoted 2 lines
drivers/reset/Kconfig +0
-0config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST
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Greentime Hu
maintainerPATCH v2 3/6 MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver
In reply to Greentime HuHere add maintainer information for SiFive FU740 PCIe driver.
--- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+)
MAINTAINERS +8 -0
@@ -13592,6 +13592,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt F: drivers/pci/controller/dwc/*imx6* +PCI DRIVER FOR FU740 +M: Paul Walmsley <[email protected]> +M: Greentime Hu <[email protected]> +L: [email protected] +S: Maintained +F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +F: drivers/pci/controller/dwc/pcie-fu740.c + PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD) M: Jonathan Derrick <[email protected]> L: [email protected]
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2.30.2 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Greentime Hu
maintainerPATCH v2 4/6 dt-bindings: PCI: Add SiFive FU740 PCIe host controller
In reply to Greentime HuAdd PCIe host controller DT bindings of SiFive FU740.
--- .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +119 -0
@@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive fu740 PCIe host controller + +description: + SiFive fu740 PCIe host controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.txt. + +maintainers: + - Paul Walmsley <[email protected]> + - Greentime Hu <[email protected]> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: sifive,fu740-pcie + + reg: + maxItems: 4 + + reg-names: + items: + - const: dbi + - const: config + - const: mgmt + + device_type: + const: pci + + dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + + bus-range: + description: Range of bus numbers associated with this controller. + + num-lanes: true + + msi-parent: true + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + + resets: + description: A phandle to the PCIe power up reset line + + pwren-gpios: + description: Should specify the GPIO for controlling the PCI bus device power on + + perstn-gpios: + description: Should specify the GPIO for controlling the PCI bus device reset + +required: + - compatible + - reg + - reg-names + - device_type + - dma-coherent + - bus-range + - ranges + - num-lanes + - interrupts + - interrupt-names + - interrupt-parent + - interrupt-map-mask + - interrupt-map + - clock-names + - clocks + - resets + - pwren-gpios + - perstn-gpios + +additionalProperties: false + +examples: + - | + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0 + 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */ + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */ + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */ + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + resets = <&prci 4>; + pwren-gpios = <&gpio 5 0>; + perstn-gpios = <&gpio 8 0>; + };
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2.30.2 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller
Hi,
Thank you for sending the patches over!
A few nitpicks.
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 13
Quoted 7 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +7
-0+title: SiFive fu740 PCIe host controller + +description: + SiFive fu740 PCIe host controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.txt.
[...]
In the above title and description it would be "FU740" to keep this consistent with everything else.
Also, as this is a YAML file, a multi-line description might be better expressed as "description: |" or "description: |+", of course it depends on whether you would like or not to preserve line endings.
[...]
Quoted 5 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +5
-0+ dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + + bus-range: + description: Range of bus numbers associated with this controller.
[...]
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 63
Quoted 8 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +8
-0+ resets: + description: A phandle to the PCIe power up reset line + + pwren-gpios: + description: Should specify the GPIO for controlling the PCI bus device power on + + perstn-gpios: + description: Should specify the GPIO for controlling the PCI bus device reset
[...]
All the above descriptions should end with a period, so that we keep things consistent throughout.
Krzysztof
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Rob Herring
maintainerRe: [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller
In reply to Greentime HuQuoted 8 lines · Greentime Hu
Add PCIe host controller DT bindings of SiFive FU740.
Signed-off-by Greentime Hu <[email protected]>--- .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dts:45.29-30 syntax error FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:349: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1380: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1455121
This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit.
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Rob Herring
maintainerRe: [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller
In reply to Greentime HuQuoted 31 lines · Greentime Hu
Add PCIe host controller DT bindings of SiFive FU740.
Signed-off-by Greentime Hu <[email protected]>--- .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yamlDocumentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +17
-0@@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive fu740 PCIe host controller + +description: + SiFive fu740 PCIe host controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.txt. + +maintainers: + - Paul Walmsley <[email protected]> + - Greentime Hu <[email protected]>
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 27
Quoted 10 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +10
-0+ +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: sifive,fu740-pcie + + reg: + maxItems: 4
What's the 4th item because there's only 3 names:
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 36
Quoted 9 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +9
-0+ + reg-names: + items: + - const: dbi + - const: config + - const: mgmt + + device_type: + const: pci
Already in pci-bus.yaml
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 42
Quoted 6 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +6
-0+ + dma-coherent: + description: Indicates that the PCIe IP block can ensure the coherency + + bus-range: + description: Range of bus numbers associated with this controller.
Already in pci-bus.yaml
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 44
Quoted 2 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +2
-0+ + num-lanes: true
Need to define possible values if not all of 1,2,4,8,16.
Quoted 6 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +6
-0+ + msi-parent: true + + interrupt-names: + items: + - const: msi
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 60
Quoted 10 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +10
-0+ - const: inta + - const: intb + - const: intc + - const: intd + + resets: + description: A phandle to the PCIe power up reset line + + pwren-gpios: + description: Should specify the GPIO for controlling the PCI bus device power on
maxItems: 1
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 63
Quoted 3 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +3
-0+ + perstn-gpios: + description: Should specify the GPIO for controlling the PCI bus device reset
The DWC binding and pci.txt already define 'reset-gpios' for this purpose.
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 69
Quoted 6 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +6
-0+ +required: + - compatible + - reg + - reg-names + - device_type
pci-bus.yaml already requires this.
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 71
Quoted 2 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +2
-0+ - dma-coherent + - bus-range
This generally doesn't need to be required unless the h/w can't support 0-0xff.
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 72
Quoted 1 line
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +1
-0+ - ranges
pci-bus.yaml already requires this.
Quoted 12 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +12
-0+ - num-lanes + - interrupts + - interrupt-names + - interrupt-parent + - interrupt-map-mask + - interrupt-map + - clock-names + - clocks + - resets + - pwren-gpios + - perstn-gpios +
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 94
Quoted 10 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +10
-0+additionalProperties: false + +examples: + - | + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0
Humm, 4GB for DBI space? The DWC controller doesn't have that much space, and the kernel will map *all* of that. That's not an insignificant amount of memory just for page tables.
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 96
Quoted 2 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +2
-0+ 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>;
<> around each reg entry.
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 104
Quoted 8 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +8
-0+ reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */ + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */ + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */ + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
<> around each ranges entry.
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 106
Quoted 2 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +2
-0+ num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>;
And here.
Quoted 16 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +13
-0+ interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + resets = <&prci 4>; + pwren-gpios = <&gpio 5 0>; + perstn-gpios = <&gpio 8 0>; + };Signature · 1 line
2.30.2
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Greentime Hu
maintainerRe: [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller
Rob Herring <[email protected]> 於 2021年3月24日 週三 上午4:35寫道：
Quoted 9 lines · Greentime Hu
Quoted 7 lines
Add PCIe host controller DT bindings of SiFive FU740.
Signed-off-by Greentime Hu <[email protected]>--- .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
[...]
Quoted 9 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml line 94
Quoted 8 lines
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file +8
-0+examples: + - | + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0
Quoted 3 lines
Humm, 4GB for DBI space? The DWC controller doesn't have that much space, and the kernel will map *all* of that. That's not an insignificant amount of memory just for page tables.
Thank you for review and point this out. :)
I check the spec description for DBI in DWC_pcie_ctl_dm_databook.pdf section 3.15 3.16 and table 3-17.
I think CX_SRIOV_ENABLE and CX_ARI_ENABLE will be set to 0 because these 2 are endpoint mode features.
Single Root I/O Virtualization (SR-IOV) This section describes the SR-IOV features implemented in EP mode. The parameter for enabling SR-IOV is CX_SRIOV_ENABLE
Alternative Routing-ID Interpretation (ARI) ARI allows an endpoint to support more than eight physical functions (PFs). ARI is enabled by the CX_ARI_ENABLE parameter.
So based on Table 3-17, we will need to map 2GB(bit30) instead of 4GB(bit31).
Greentime Hu
maintainerPATCH v2 5/6 PCI: fu740: Add SiFive FU740 PCIe host controller driver
In reply to Greentime HuFrom: Paul Walmsley <[email protected]>
Add driver for the SiFive FU740 PCIe host controller. This controller is based on the DesignWare PCIe core.
--- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-fu740.c | 324 ++++++++++++++++++++++++ 3 files changed, 334 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-fu740.c
drivers/pci/controller/dwc/Kconfig +9 -0
@@ -318,4 +318,13 @@ config PCIE_AL required only for DT-based platforms. ACPI platforms with the Annapurna Labs PCIe controller don't need to enable this. +config PCIE_FU740 + bool "SiFive FU740 PCIe host controller" + depends on PCI_MSI_IRQ_DOMAIN + depends on SOC_SIFIVE || COMPILE_TEST + select PCIE_DW_HOST + help + Say Y here if you want PCIe controller support for the SiFive + FU740. + endmenu
drivers/pci/controller/dwc/Makefile +1 -0
@@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o +obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
drivers/pci/controller/dwc/pcie-fu740.c new file +324 -0
324 lines not on this page · raw message
Signature · 7 lines
2.30.2 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v2 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver
Hi,
[...]
Quoted 21 lines
drivers/pci/controller/dwc/pcie-fu740.c new file +21
-0+static void fu740_phyregwrite (const uint8_t phy,const uint16_t addr, +const uint16_t wrdata,struct fu740_pcie *afp) +{ +struct device *dev = afp->pci.dev; +void __iomem *phy_cr_para_addr; +void __iomem *phy_cr_para_wr_data; +void __iomem *phy_cr_para_wr_en; +void __iomem *phy_cr_para_ack; +int ret, val; + +/* Setup */ +if (phy) { + phy_cr_para_addr = afp->mgmt_base +PCIEX8MGMT_PHY1_CR_PARA_ADDR ; + phy_cr_para_wr_data = afp->mgmt_base +PCIEX8MGMT_PHY1_CR_PARA_WR_DATA ; + phy_cr_para_wr_en = afp->mgmt_base +PCIEX8MGMT_PHY1_CR_PARA_WR_EN ; + phy_cr_para_ack = afp->mgmt_base +PCIEX8MGMT_PHY1_CR_PARA_ACK ; + }else { + phy_cr_para_addr = afp->mgmt_base +PCIEX8MGMT_PHY0_CR_PARA_ADDR ; + phy_cr_para_wr_data = afp->mgmt_base +PCIEX8MGMT_PHY0_CR_PARA_WR_DATA ; + phy_cr_para_wr_en = afp->mgmt_base +PCIEX8MGMT_PHY0_CR_PARA_WR_EN ; + phy_cr_para_ack = afp->mgmt_base +PCIEX8MGMT_PHY0_CR_PARA_ACK ;
drivers/pci/controller/dwc/pcie-fu740.c line 150
Quoted 10 lines
drivers/pci/controller/dwc/pcie-fu740.c new file +10
-0+ } + +writel_relaxed (addr, phy_cr_para_addr); +writel_relaxed (wrdata, phy_cr_para_wr_data); +writel_relaxed (1 , phy_cr_para_wr_en); + +/* Wait for wait_idle */ + ret =readl_poll_timeout (phy_cr_para_ack, val, val,10 ,5000 ); +if (ret) +dev_err (dev,"Wait for wait_ilde state failed!\n" );
It would be "wait_idle" rather than "wait_idle".
[...]
drivers/pci/controller/dwc/pcie-fu740.c line 158
Quoted 4 lines
drivers/pci/controller/dwc/pcie-fu740.c new file +4
-0+/* Wait for ~wait_idle */ + ret =readl_poll_timeout (phy_cr_para_ack, val, !val,10 ,5000 ); +if (ret) +dev_err (dev,"Wait for !wait_ilde state failed!\n" );
[...]
Same as above, it would be "wait_idle" in the above.
drivers/pci/controller/dwc/pcie-fu740.c line 196
Quoted 13 lines
drivers/pci/controller/dwc/pcie-fu740.c new file +13
-0+static void fu740_pcie_ltssm_enable (struct device *dev) +{ +struct fu740_pcie *afp =dev_get_drvdata (dev); + +/* Enable LTSSM */ +writel_relaxed (0x1 , afp->mgmt_base +PCIEX8MGMT_APP_LTSSM_ENABLE ); +} + +static int fu740_pcie_start_link (struct dw_pcie *pci) +{ +struct device *dev = pci->dev; + +/* Start LTSSM. */
Nitpick. No need for a dot in this comment to keep it consistent with the comment in the function above this one.
Quoted 29 lines
drivers/pci/controller/dwc/pcie-fu740.c new file +29
-0+static int fu740_pcie_host_init (struct pcie_port *pp) +{ +struct dw_pcie *pci =to_dw_pcie_from_pp (pp); +struct fu740_pcie *afp =to_fu740_pcie (pci); +struct device *dev = pci->dev; +int ret; + +/* Power on reset */ +fu740_pcie_drive_perstn (afp); + +/* Enable pcieauxclk */ + ret =clk_prepare_enable (afp->pcie_aux); +if (ret) +dev_err (dev,"unable to enable pcie_aux clock\n" ); + +/* +* Assert hold_phy_rst (hold the controller LTSSM in reset after +* power_up_rst_n for register programming with cr_para) +*/ +writel_relaxed (0x1 , afp->mgmt_base +PCIEX8MGMT_APP_HOLD_PHY_RST ); + +/* Deassert power_up_rst_n */ + ret =reset_control_deassert (afp->rst); +if (ret) +dev_err (dev,"unable to deassert pcie_power_up_rst_n\n" ); + +fu740_pcie_init_phy (afp); + +/* Disable pcieauxclk */
drivers/pci/controller/dwc/pcie-fu740.c line 239
Quoted 10 lines
drivers/pci/controller/dwc/pcie-fu740.c new file +10
-0+clk_disable_unprepare (afp->pcie_aux); +/* Clear hold_phy_rst */ +writel_relaxed (0x0 , afp->mgmt_base +PCIEX8MGMT_APP_HOLD_PHY_RST ); +/* Enable pcieauxclk */ + ret =clk_prepare_enable (afp->pcie_aux); +/* Set RC mode */ +writel_relaxed (0x4 , afp->mgmt_base +PCIEX8MGMT_DEVICE_TYPE ); + +return 0 ; +}
[...]
It seems that the error handling is somewhat broken in the above function, especially when you look at how the "ret" variables does not seem to be used for anything once there was an error.
Krzysztof
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Re: [PATCH v2 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver
Hi,
[...]
Quoted 6 lines
drivers/pci/controller/dwc/pcie-fu740.c line 150
Quoted 4 lines
drivers/pci/controller/dwc/pcie-fu740.c new file +4
-0+/* Wait for wait_idle */ + ret =readl_poll_timeout (phy_cr_para_ack, val, val,10 ,5000 ); +if (ret) +dev_err (dev,"Wait for wait_ilde state failed!\n" );It would be "
wait_idle" rather than "wait_idle".
[...]
Apologies, meant to say "wait_ilde" in the "rather than" part, but went ahead and somehow used the correct spelling. :)
Krzysztof
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Greentime Hu
maintainerPATCH v2 6/6 riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
In reply to Greentime Hu--- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+)
arch/riscv/boot/dts/sifive/fu740-c000.dtsi +34 -0
@@ -158,6 +158,7 @@ prci: clock-controller@10000000 { reg = <0x0 0x10000000 0x0 0x1000>; clocks = <&hfclk>, <&rtcclk>; #clock-cells = <1>; + #reset-cells = <1>; }; uart0: serial@10010000 { compatible = "sifive,fu740-c000-uart", "sifive,uart0";
@@ -288,5 +289,38 @@ gpio: gpio@10060000 { clocks = <&prci PRCI_CLK_PCLK>; status = "disabled"; }; + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #num-lanes = <8>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0 + 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */ + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */ + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */ + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + pwren-gpios = <&gpio 5 0>; + perstn-gpios = <&gpio 8 0>; + resets = <&prci 4>; + status = "okay"; + }; }; };
Signature · 7 lines
2.30.2 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
Quoted 46 lines · On Wed, 17 Mar 2021 23:08:13 PDT (-0700), [email protected] wrote:
Signed-off-by Greentime Hu <[email protected]>--- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+)arch/riscv/boot/dts/sifive/fu740-c000.dtsi +26
-0@@ -158,6 +158,7 @@ prci: clock-controller@10000000 { reg = <0x0 0x10000000 0x0 0x1000>; clocks = <&hfclk>, <&rtcclk>; #clock-cells = <1>; + #reset-cells = <1>; }; uart0: serial@10010000 { compatible = "sifive,fu740-c000-uart", "sifive,uart0";@@ -288,5 +289,38 @@ gpio: gpio@10060000 { clocks = <&prci PRCI_CLK_PCLK>; status = "disabled"; }; + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #num-lanes = <8>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0 + 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */ + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */ + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */ + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>,
arch/riscv/boot/dts/sifive/fu740-c000.dtsi gpio: gpio@10060000 { · line 326
Quoted 10 lines
arch/riscv/boot/dts/sifive/fu740-c000.dtsi +8
-0+ <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + pwren-gpios = <&gpio 5 0>; + perstn-gpios = <&gpio 8 0>; + resets = <&prci 4>; + status = "okay"; + }; }; };
I'm happy to take these all through the RISC-V tree if that helps, but as usual I'd like reviews or acks from the subsystem maintainers. It looks like there are some issues so I'm going to drop this from my inbox.
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Greentime Hu
maintainerRe: [PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
Palmer Dabbelt <[email protected]> 於 2021年3月31日 週三 上午8:24寫道：
Quoted 61 lines · On Wed, 17 Mar 2021 23:08:13 PDT (-0700), [email protected] wrote:
Quoted 46 lines
Signed-off-by Greentime Hu <[email protected]>--- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+)arch/riscv/boot/dts/sifive/fu740-c000.dtsi +26
-0@@ -158,6 +158,7 @@ prci: clock-controller@10000000 { reg = <0x0 0x10000000 0x0 0x1000>; clocks = <&hfclk>, <&rtcclk>; #clock-cells = <1>; + #reset-cells = <1>; }; uart0: serial@10010000 { compatible = "sifive,fu740-c000-uart", "sifive,uart0";@@ -288,5 +289,38 @@ gpio: gpio@10060000 { clocks = <&prci PRCI_CLK_PCLK>; status = "disabled"; }; + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #num-lanes = <8>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0 + 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */ + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */ + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */ + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>,arch/riscv/boot/dts/sifive/fu740-c000.dtsi gpio: gpio@10060000 { · line 326
Quoted 10 lines
arch/riscv/boot/dts/sifive/fu740-c000.dtsi +8
-0+ <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + pwren-gpios = <&gpio 5 0>; + perstn-gpios = <&gpio 8 0>; + resets = <&prci 4>; + status = "okay"; + }; }; };Acked-by Palmer Dabbelt <[email protected]>
Quoted 4 lines
I'm happy to take these all through the RISC-V tree if that helps, but as usual I'd like reviews or acks from the subsystem maintainers. It looks like there are some issues so I'm going to drop this from my inbox.
Hi Palmer,
Since the subsystem maintainer has pick the first 5 patches to his branch, would you please help to pick the 6th patch of version 6? Thank you. :)
https://www.spinics.net/lists/linux-clk/msg57213.html
https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/
Greentime Hu
maintainerRe: [PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
Greentime Hu <[email protected]> 於 2021年4月19日 週一 上午10:43寫道：
Quoted 68 lines
Palmer Dabbelt <[email protected]> 於 2021年3月31日 週三 上午8:24寫道：
Quoted 61 lines · On Wed, 17 Mar 2021 23:08:13 PDT (-0700), [email protected] wrote:
Quoted 46 lines
Signed-off-by Greentime Hu <[email protected]>--- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+)arch/riscv/boot/dts/sifive/fu740-c000.dtsi +26
-0@@ -158,6 +158,7 @@ prci: clock-controller@10000000 { reg = <0x0 0x10000000 0x0 0x1000>; clocks = <&hfclk>, <&rtcclk>; #clock-cells = <1>; + #reset-cells = <1>; }; uart0: serial@10010000 { compatible = "sifive,fu740-c000-uart", "sifive,uart0";@@ -288,5 +289,38 @@ gpio: gpio@10060000 { clocks = <&prci PRCI_CLK_PCLK>; status = "disabled"; }; + pcie@e00000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #num-lanes = <8>; + #size-cells = <2>; + compatible = "sifive,fu740-pcie"; + reg = <0xe 0x00000000 0x1 0x0 + 0xd 0xf0000000 0x0 0x10000000 + 0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000 /* I/O */ + 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000 /* mem */ + 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000 /* mem */ + 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56 57 58 59 60 61 62 63 64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>,arch/riscv/boot/dts/sifive/fu740-c000.dtsi gpio: gpio@10060000 { · line 326
Quoted 10 lines
arch/riscv/boot/dts/sifive/fu740-c000.dtsi +8
-0+ <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + pwren-gpios = <&gpio 5 0>; + perstn-gpios = <&gpio 8 0>; + resets = <&prci 4>; + status = "okay"; + }; }; };Acked-by Palmer Dabbelt <[email protected]>Quoted 4 lines
I'm happy to take these all through the RISC-V tree if that helps, but as usual I'd like reviews or acks from the subsystem maintainers. It looks like there are some issues so I'm going to drop this from my inbox.
Quoted 4 lines
Hi Palmer,
Since the subsystem maintainer has pick the first 5 patches to his branch, would you please help to pick the 6th patch of version 6?
Sorry there is no version 6, I mean version 5. :p
Stephen Boyd
maintainerQuoting Greentime Hu (2021-03-17 23:08:07)
Quoted 7 lines
This patchset includes SiFive FU740 PCIe host controller driver. We also add
pcie_auxclock andpcie_power_on_resetcontroller to prci driver for PCIe driver to use it.This is tested with e1000e: Intel(R) PRO/1000 Network Card, AMD Radeon R5 230 graphics card and SP M.2 PCIe Gen 3 SSD in SiFive Unmatched based on v5.11 Linux kernel.
Can I merge the clk patches to clk-next? Or is the dts patch going to be sent in for the merge window? I'd like to merge the clk patches if the other patches are going to miss the next merge window.
Quoted 4 lines
Changes in v2:
- Refine codes based on reviewers' feedback
- Remove define and use the common one
Greentime Hu
maintainerStephen Boyd <[email protected]> 於 2021年3月30日 週二 上午3:12寫道：
Quoted 6 lines
Quoting Greentime Hu (2021-03-17 23:08:07)
Quoted 4 lines
This patchset includes SiFive FU740 PCIe host controller driver. We also add
pcie_auxclock andpcie_power_on_resetcontroller to prci driver for PCIe driver to use it.
Quoted 7 lines
Quoted 3 lines
This is tested with e1000e: Intel(R) PRO/1000 Network Card, AMD Radeon R5 230 graphics card and SP M.2 PCIe Gen 3 SSD in SiFive Unmatched based on v5.11 Linux kernel.
Can I merge the clk patches to clk-next? Or is the dts patch going to be sent in for the merge window? I'd like to merge the clk patches if the other patches are going to miss the next merge window.
Hi Stephen,
Thank you for reviewing. I am ok with either way. :)
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