Hyper-V nested virt enlightenments for SVM
Subsystems (6)
v3 cover Hyper-V nested virt enlightenments for SVM
This patch series enables the nested virtualization enlightenments for SVM. This is very similar to the enlightenments for VMX except for the fact that there is no enlightened VMCS. For SVM, VMCB is already an architectural in-memory data structure.
The supported enlightenments are:
Enlightened TLB Flush: If this is enabled, ASID invalidations invalidate only gva -> hpa entries. To flush entries derived from NPT, hyper-v provided hypercalls (HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList) should be used.
Enlightened MSR bitmap(TLFS 16.5.3): "When enabled, L0 hypervisor does not monitor the MSR bitmaps for changes. Instead, the L1 hypervisor must invalidate the corresponding clean field after making changes to one of the MSR bitmaps."
Direct Virtual Flush(TLFS 16.8): The hypervisor exposes hypercalls (HvFlushVirtualAddressSpace, HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressList, and HvFlushVirtualAddressListEx) that allow operating systems to more efficiently manage the virtual TLB. The L1 hypervisor can choose to allow its guest to use those hypercalls and delegate the responsibility to handle them to the L0 hypervisor. This requires the use of a partition assist page."
L2 Windows boot time was measured with and without the patch. Time was measured from power on to the login screen and was averaged over a consecutive 5 trials:
Without the patch: 42 seconds
With the patch: 29 seconds
--
Changes from v2:
- Refactored the Remote TLB Flush logic into separate hyperv specific source files (kvm_onhyperv.[ch]).
- Reverted the VMCB Clean bits macro changes as it is no longer needed.
Changes from v1:
- Move the remote TLB flush related fields from kvm_vcpu_hv and kvm_hv to kvm_vcpu_arch and kvm_arch.
- Modify the VMCB clean mask runtime based on whether L1 hypervisor is running on Hyper-V or not.
- Detect Hyper-V nested enlightenments based on HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS.
- Address other minor review comments.
---
Vineeth Pillai (7):
hyperv: Detect Nested virtualization support for SVM
hyperv: SVM enlightened TLB flush support flag
KVM: x86: hyper-v: Move the remote TLB flush logic out of vmx
KVM: SVM: hyper-v: Nested enlightenments in VMCB
KVM: SVM: hyper-v: Remote TLB flush for SVM
KVM: SVM: hyper-v: Enlightened MSR-Bitmap support
KVM: SVM: hyper-v: Direct Virtual Flush support
arch/x86/include/asm/hyperv-tlfs.h | 9 +++ arch/x86/include/asm/kvm_host.h | 14 ++++ arch/x86/include/asm/svm.h | 24 +++++- arch/x86/kernel/cpu/mshyperv.c | 10 ++- arch/x86/kvm/Makefile | 5 ++ arch/x86/kvm/kvm_onhyperv.c | 94 ++++++++++++++++++++++ arch/x86/kvm/kvm_onhyperv.h | 31 ++++++++ arch/x86/kvm/svm/svm.c | 121 +++++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.h | 12 ++- arch/x86/kvm/vmx/vmx.c | 97 ++--------------------- arch/x86/kvm/vmx/vmx.h | 10 --- arch/x86/kvm/x86.c | 8 ++ 12 files changed, 330 insertions(+), 105 deletions(-) create mode 100644 arch/x86/kvm/kvm_onhyperv.c create mode 100644 arch/x86/kvm/kvm_onhyperv.h
Signature · 1 line
2.25.1
PATCH v3 1/7 hyperv: Detect Nested virtualization support for SVM
Previously, to detect nested virtualization enlightenment support, we were using HV_X64_ENLIGHTENED_VMCS_RECOMMENDED feature bit of HYPERV_CPUID_ENLIGHTMENT_INFO.EAX CPUID as docuemented in TLFS:
"Bit 14: Recommend a nested hypervisor using the enlightened VMCS
interface. Also indicates that additional nested enlightenments may be available (see leaf 0x4000000A)".
Enlightened VMCS, however, is an Intel only feature so the above detection method doesn't work for AMD. So, use the HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS.EAX CPUID information ("The maximum input value for hypervisor CPUID information.") and this works for both AMD and Intel.
--- arch/x86/kernel/cpu/mshyperv.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
arch/x86/kernel/cpu/mshyperv.c +7 -3
@@ -252,6 +252,7 @@ static void __init hv_smp_prepare_cpus(unsigned int max_cpus)static void __init ms_hyperv_init_platform (void ) { +int hv_max_functions_eax;int hv_host_info_eax;int hv_host_info_ebx;int hv_host_info_ecx;
@@ -269,6 +270,8 @@ static void __init ms_hyperv_init_platform(void) ms_hyperv.misc_features =cpuid_edx (HYPERV_CPUID_FEATURES ); ms_hyperv.hints =cpuid_eax (HYPERV_CPUID_ENLIGHTMENT_INFO ); + hv_max_functions_eax =cpuid_eax (HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS ); +pr_info ("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n" , ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints, ms_hyperv.misc_features);
@@ -298,8 +301,7 @@ static void __init ms_hyperv_init_platform(void)/* * Extract host information. */ -if (cpuid_eax (HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS ) >= -HYPERV_CPUID_VERSION ) { +if (hv_max_functions_eax >=HYPERV_CPUID_VERSION ) { hv_host_info_eax =cpuid_eax (HYPERV_CPUID_VERSION ); hv_host_info_ebx =cpuid_ebx (HYPERV_CPUID_VERSION ); hv_host_info_ecx =cpuid_ecx (HYPERV_CPUID_VERSION );
@@ -325,9 +327,11 @@ static void __init ms_hyperv_init_platform(void) ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); } -if (ms_hyperv.hints &HV_X64_ENLIGHTENED_VMCS_RECOMMENDED ) { +if (hv_max_functions_eax >=HYPERV_CPUID_NESTED_FEATURES ) { ms_hyperv.nested_features =cpuid_eax (HYPERV_CPUID_NESTED_FEATURES ); +pr_info ("Hyper-V: Nested features: 0x%x\n" , + ms_hyperv.nested_features); }/*
Signature · 1 line
2.25.1
PATCH v3 2/7 hyperv: SVM enlightened TLB flush support flag
In reply to Vineeth PillaiBit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies support for enlightened TLB flush. With this enlightenment enabled, ASID invalidations flushes only gva->hpa entries. To flush TLB entries derived from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList)
--- arch/x86/include/asm/hyperv-tlfs.h | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/x86/include/asm/hyperv-tlfs.h +9 -0
@@ -133,6 +133,15 @@#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)#define HV_X64_NESTED_MSR_BITMAP BIT(19) +/* +* This is specific to AMD and specifies that enlightened TLB flush is +* supported. If guest opts in to this feature, ASID invalidations only +* flushes gva -> hpa mapping entries. To flush the TLB entries derived +* from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace +* or HvFlushGuestPhysicalAddressList). +*/ +#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) +/* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ #define HV_PARAVISOR_PRESENT BIT(0)
Signature · 1 line
2.25.1
PATCH v3 3/7 KVM: x86: hyper-v: Move the remote TLB flush logic out of vmx
In reply to Vineeth PillaiCurrently the remote TLB flush logic is specific to VMX. Move it to a common place so that SVM can use it as well.
--- arch/x86/include/asm/kvm_host.h | 14 +++++ arch/x86/kvm/Makefile | 5 ++ arch/x86/kvm/kvm_onhyperv.c | 94 ++++++++++++++++++++++++++++++++ arch/x86/kvm/kvm_onhyperv.h | 31 +++++++++++ arch/x86/kvm/vmx/vmx.c | 97 +++------------------------------ arch/x86/kvm/vmx/vmx.h | 10 ---- arch/x86/kvm/x86.c | 8 +++ 7 files changed, 159 insertions(+), 100 deletions(-) create mode 100644 arch/x86/kvm/kvm_onhyperv.c create mode 100644 arch/x86/kvm/kvm_onhyperv.h
arch/x86/include/asm/kvm_host.h +14 -0
@@ -838,6 +838,15 @@ struct kvm_vcpu_arch {/* Protected Guests */ bool guest_state_protected; + +#if IS_ENABLED (CONFIG_HYPERV ) +/* +* Two Dimensional paging CR3 +* EPTP for Intel +* nCR3 for AMD +*/ +u64 tdp_pointer; +#endif };struct kvm_lpage_info {
@@ -1079,6 +1088,11 @@ struct kvm_arch {*/ spinlock_t tdp_mmu_pages_lock;#endif /* CONFIG_X86_64 */ + +#if IS_ENABLED (CONFIG_HYPERV ) +int tdp_pointers_match; +spinlock_t tdp_pointer_lock; +#endif };struct kvm_vm_stat {
arch/x86/kvm/Makefile +5 -0
@@ -18,6 +18,11 @@ kvm-y += x86.o emulate.o i8259.o irq.o lapic.o \ i8254.o ioapic.o irq_comm.o cpuid.o pmu.o mtrr.o \ hyperv.o debugfs.o mmu/mmu.o mmu/page_track.o \ mmu/spte.o + +ifdef CONFIG_HYPERV +kvm-y += kvm_onhyperv.o +endif + kvm-$(CONFIG_X86_64) += mmu/tdp_iter.o mmu/tdp_mmu.o kvm-$(CONFIG_KVM_XEN) += xen.o
arch/x86/kvm/kvm_onhyperv.c new file +94 -0
94 lines not on this page · raw message
arch/x86/kvm/kvm_onhyperv.h new file +31 -0
@@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* KVM L1 hypervisor optimizations on Hyper-V. +*/ + +#ifndef __ARCH_X86_KVM_KVM_ONHYPERV_H__ +#define __ARCH_X86_KVM_KVM_ONHYPERV_H__ + +#if IS_ENABLED (CONFIG_HYPERV ) + +enum tdp_pointers_status { +TDP_POINTERS_CHECK =0 , +TDP_POINTERS_MATCH =1 , +TDP_POINTERS_MISMATCH =2 +}; + +static inline void kvm_update_arch_tdp_pointer (struct kvm *kvm, +struct kvm_vcpu *vcpu,u64 tdp_pointer) +{ +spin_lock (&kvm->arch.tdp_pointer_lock); + vcpu->arch.tdp_pointer = tdp_pointer; + kvm->arch.tdp_pointers_match =TDP_POINTERS_CHECK ; +spin_unlock (&kvm->arch.tdp_pointer_lock); +} + +int kvm_hv_remote_flush_tlb (struct kvm *kvm); +int kvm_hv_remote_flush_tlb_with_range (struct kvm *kvm, +struct kvm_tlb_range *range); +#endif +#endif +
arch/x86/kvm/vmx/vmx.c +7 -90
134 lines not on this page · raw message
arch/x86/kvm/vmx/vmx.h +0 -10
@@ -325,7 +325,6 @@ struct vcpu_vmx {*/ u64 msr_ia32_feature_control;u64 msr_ia32_feature_control_valid_bits; -u64 ept_pointer;struct pt_desc pt_desc;struct lbr_desc lbr_desc;
@@ -338,21 +337,12 @@ struct vcpu_vmx { } shadow_msr_intercept; }; -enum ept_pointers_status { -EPT_POINTERS_CHECK =0 , -EPT_POINTERS_MATCH =1 , -EPT_POINTERS_MISMATCH =2 -}; -struct kvm_vmx {struct kvm kvm;unsigned int tss_addr;bool ept_identity_pagetable_done;gpa_t ept_identity_map_addr; - -enum ept_pointers_status ept_pointers_match; -spinlock_t ept_pointer_lock; };bool nested_vmx_allowed (struct kvm_vcpu *vcpu);
arch/x86/kvm/x86.c +8 -0
@@ -10115,6 +10115,10 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) vcpu->arch.pending_external_vector =-1 ; vcpu->arch.preempted_in_kernel = false; +#if IS_ENABLED (CONFIG_HYPERV ) + vcpu->arch.tdp_pointer =INVALID_PAGE ; +#endif + r =static_call (kvm_x86_vcpu_create)(vcpu);if (r) goto free_guest_fpu;
@@ -10498,6 +10502,10 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) kvm->arch.guest_can_read_msr_platform_info = true; +#if IS_ENABLED (CONFIG_HYPERV ) +spin_lock_init (&kvm->arch.tdp_pointer_lock); +#endif +INIT_DELAYED_WORK (&kvm->arch.kvmclock_update_work, kvmclock_update_fn);INIT_DELAYED_WORK (&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
Signature · 1 line
2.25.1
PATCH v3 4/7 KVM: SVM: hyper-v: Nested enlightenments in VMCB
In reply to Vineeth PillaiAdd Hyper-V specific fields in VMCB to support SVM enlightenments. Also a small refactoring of VMCB clean bits handling.
--- arch/x86/include/asm/svm.h | 24 +++++++++++++++++++++++- arch/x86/kvm/svm/svm.c | 8 ++++++++ arch/x86/kvm/svm/svm.h | 12 +++++++++++- 3 files changed, 42 insertions(+), 2 deletions(-)
arch/x86/include/asm/svm.h +23 -1
@@ -322,9 +322,31 @@ static inline void __unused_size_checks(void)BUILD_BUG_ON (sizeof (struct ghcb ) !=EXPECTED_GHCB_SIZE ); } + +#if IS_ENABLED (CONFIG_HYPERV ) +struct __packed hv_enlightenments { +struct __packed hv_enlightenments_control { + u32 nested_flush_hypercall:1; + u32 msr_bitmap:1; + u32 enlightened_npt_tlb: 1; + u32 reserved:29; + } hv_enlightenments_control; +u32 hv_vp_id; +u64 hv_vm_id; +u64 partition_assist_page; +u64 reserved; +}; +#define VMCB_CONTROL_END 992 // 32 bytes for Hyper-V +#else +#define VMCB_CONTROL_END 1024 +#endif +struct vmcb {struct vmcb_control_area control; -u8 reserved_control[1024 -sizeof (struct vmcb_control_area )]; +u8 reserved_control[VMCB_CONTROL_END -sizeof (struct vmcb_control_area )]; +#if IS_ENABLED (CONFIG_HYPERV ) +struct hv_enlightenments hv_enlightenments; +#endif struct vmcb_save_area save; } __packed;
arch/x86/kvm/svm/svm.c +8 -0
@@ -31,6 +31,7 @@#include <asm/tlbflush.h> #include <asm/desc.h> #include <asm/debugreg.h> +#include <asm/hypervisor.h> #include <asm/kvm_para.h> #include <asm/irq_remapping.h> #include <asm/spec-ctrl.h>
@@ -122,6 +123,8 @@ bool npt_enabled = true;bool npt_enabled;#endif +u32 __read_mostly vmcb_all_clean_mask = ((1 <<VMCB_DIRTY_MAX ) -1 ); +/* * These 2 parameters are used to config the controls for Pause-Loop Exiting: * pause_filter_count: On processors that support Pause filtering(indicated
@@ -1051,6 +1054,11 @@ static __init int svm_hardware_setup(void)*/ allow_smaller_maxphyaddr = !npt_enabled; +#if IS_ENABLED (CONFIG_HYPERV ) +if (hypervisor_is_type (X86_HYPER_MS_HYPERV )) + vmcb_all_clean_mask |=BIT (VMCB_HV_NESTED_ENLIGHTENMENTS ); +#endif +return 0 ; err:
arch/x86/kvm/svm/svm.h +11 -1
@@ -51,11 +51,16 @@ enum {* AVIC LOGICAL_TABLE pointer */ VMCB_DIRTY_MAX, +#if IS_ENABLED (CONFIG_HYPERV ) + VMCB_HV_NESTED_ENLIGHTENMENTS = 31, +#endif };/* TPR and CR2 are always written before VMRUN */ #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) +extern u32 vmcb_all_clean_mask__read_mostly ; +struct kvm_sev_info {bool active;/* SEV enabled guest */ bool es_active;/* SEV-ES enabled guest */
@@ -230,7 +235,7 @@ static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)static inline void vmcb_mark_all_clean (struct vmcb *vmcb) { - vmcb->control.clean = ((1 <<VMCB_DIRTY_MAX ) -1 ) + vmcb->control.clean = vmcb_all_clean_mask & ~VMCB_ALWAYS_DIRTY_MASK ; }
@@ -239,6 +244,11 @@ static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) vmcb->control.clean &= ~(1 << bit); } +static inline bool vmcb_is_clean (struct vmcb *vmcb,int bit) +{ +return (vmcb->control.clean & (1 << bit)); +} +static inline struct vcpu_svm *to_svm (struct kvm_vcpu *vcpu) { return container_of(vcpu, struct vcpu_svm, vcpu);
Signature · 1 line
2.25.1
Re: [PATCH v3 4/7] KVM: SVM: hyper-v: Nested enlightenments in VMCB
Quoted 34 lines · Vineeth Pillai
Add Hyper-V specific fields in VMCB to support SVM enlightenments. Also a small refactoring of VMCB clean bits handling.
Signed-off-by Vineeth Pillai <[email protected]>--- arch/x86/include/asm/svm.h | 24 +++++++++++++++++++++++- arch/x86/kvm/svm/svm.c | 8 ++++++++ arch/x86/kvm/svm/svm.h | 12 +++++++++++- 3 files changed, 42 insertions(+), 2 deletions(-)arch/x86/include/asm/svm.h +16
-0@@ -322,9 +322,31 @@ static inline void __unused_size_checks(void)BUILD_BUG_ON (sizeof (struct ghcb ) !=EXPECTED_GHCB_SIZE ); } + +#if IS_ENABLED (CONFIG_HYPERV ) +struct __packed hv_enlightenments { +struct __packed hv_enlightenments_control { + u32 nested_flush_hypercall:1; + u32 msr_bitmap:1; + u32 enlightened_npt_tlb: 1; + u32 reserved:29; + } hv_enlightenments_control; +u32 hv_vp_id; +u64 hv_vm_id; +u64 partition_assist_page; +u64 reserved; +}; +#define VMCB_CONTROL_END 992 // 32 bytes for Hyper-V +#else
arch/x86/include/asm/svm.h static inline void __unused_size_checks(void) · line 349
Quoted 10 lines
arch/x86/include/asm/svm.h +7
-1+#define VMCB_CONTROL_END 1024 +#endif +struct vmcb {struct vmcb_control_area control; -u8 reserved_control[1024 -sizeof (struct vmcb_control_area )]; +u8 reserved_control[VMCB_CONTROL_END -sizeof (struct vmcb_control_area )]; +#if IS_ENABLED (CONFIG_HYPERV ) +struct hv_enlightenments hv_enlightenments; +#endif
I believe the 32 bytes at the end of the VMCB control area will be for use by any software/hypervisor. The APM update that documents this change, along with clean bit 31, isn't public, yet, but should be in a month or so (from what I was told).
So these fields should be added generically and then your code should make use of the generic field mapped with your structure.
To my knowledge (until the APM is public and documents everything), I believe the following will be in place:
VMCB offset 0x3e0 - 0x3ff is reserved for software Clean bit 31 is reserved for software
SVM intercept exit code 0xf0000000 is reserved for software
Quoted 25 lines
arch/x86/include/asm/svm.h +0
-0struct vmcb_save_area save; } __packed;arch/x86/kvm/svm/svm.c +3
-0@@ -31,6 +31,7 @@#include <asm/tlbflush.h> #include <asm/desc.h> #include <asm/debugreg.h> +#include <asm/hypervisor.h> #include <asm/kvm_para.h> #include <asm/irq_remapping.h> #include <asm/spec-ctrl.h> @@ -122,6 +123,8 @@ bool npt_enabled = true;bool npt_enabled;#endif +u32 __read_mostly vmcb_all_clean_mask = ((1 <<VMCB_DIRTY_MAX ) -1 ); +/* * These 2 parameters are used to config the controls for Pause-Loop Exiting: * pause_filter_count: On processors that support Pause filtering(indicated
arch/x86/kvm/svm/svm.c static __init int svm_hardware_setup(void) · line 1061
Quoted 8 lines
arch/x86/kvm/svm/svm.c +5
-0@@ -1051,6 +1054,11 @@ static __init int svm_hardware_setup(void)*/ allow_smaller_maxphyaddr = !npt_enabled; +#if IS_ENABLED (CONFIG_HYPERV ) +if (hypervisor_is_type (X86_HYPER_MS_HYPERV )) + vmcb_all_clean_mask |=BIT (VMCB_HV_NESTED_ENLIGHTENMENTS ); +#endif +
Is there any way to hide all the #if's in this and the other patches so that the .c files are littered with the #if IS_ENABLED() lines. Put them in svm.h or a new svm-hv.h file?
Quoted 8 lines
arch/x86/kvm/svm/svm.c +0
-0return 0 ; err:arch/x86/kvm/svm/svm.h +0
-0
arch/x86/kvm/svm/svm.h enum { · line 56
Quoted 6 lines
arch/x86/kvm/svm/svm.h +3
-0@@ -51,11 +51,16 @@ enum {* AVIC LOGICAL_TABLE pointer */ VMCB_DIRTY_MAX, +#if IS_ENABLED (CONFIG_HYPERV ) + VMCB_HV_NESTED_ENLIGHTENMENTS = 31, +#endif
Again, this should be generic.
Thanks,
Tom
Quoted 32 lines
arch/x86/kvm/svm/svm.h +8
-1};/* TPR and CR2 are always written before VMRUN */ #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) +extern u32 vmcb_all_clean_mask__read_mostly ; +struct kvm_sev_info {bool active;/* SEV enabled guest */ bool es_active;/* SEV-ES enabled guest */ @@ -230,7 +235,7 @@ static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)static inline void vmcb_mark_all_clean (struct vmcb *vmcb) { - vmcb->control.clean = ((1 <<VMCB_DIRTY_MAX ) -1 ) + vmcb->control.clean = vmcb_all_clean_mask & ~VMCB_ALWAYS_DIRTY_MASK ; }@@ -239,6 +244,11 @@ static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit) vmcb->control.clean &= ~(1 << bit); } +static inline bool vmcb_is_clean (struct vmcb *vmcb,int bit) +{ +return (vmcb->control.clean & (1 << bit)); +} +static inline struct vcpu_svm *to_svm (struct kvm_vcpu *vcpu) { return container_of(vcpu, struct vcpu_svm, vcpu);
Re: [PATCH v3 4/7] KVM: SVM: hyper-v: Nested enlightenments in VMCB
Hi Tom,
Quoted 35 lines
Quoted 17 lines
arch/x86/include/asm/svm.h +16
-0+ +#if IS_ENABLED (CONFIG_HYPERV ) +struct __packed hv_enlightenments { +struct __packed hv_enlightenments_control { + u32 nested_flush_hypercall:1; + u32 msr_bitmap:1; + u32 enlightened_npt_tlb: 1; + u32 reserved:29; + } hv_enlightenments_control; +u32 hv_vp_id; +u64 hv_vm_id; +u64 partition_assist_page; +u64 reserved; +}; +#define VMCB_CONTROL_END 992 // 32 bytes for Hyper-V +#else arch/x86/include/asm/svm.h static inline void __unused_size_checks(void) · line 349
Quoted 10 lines
arch/x86/include/asm/svm.h +7
-1+#define VMCB_CONTROL_END 1024 +#endif +struct vmcb {struct vmcb_control_area control; -u8 reserved_control[1024 -sizeof (struct vmcb_control_area )]; +u8 reserved_control[VMCB_CONTROL_END -sizeof (struct vmcb_control_area )]; +#if IS_ENABLED (CONFIG_HYPERV ) +struct hv_enlightenments hv_enlightenments; +#endif I believe the 32 bytes at the end of the VMCB control area will be for use by any software/hypervisor. The APM update that documents this change, along with clean bit 31, isn't public, yet, but should be in a month or so (from what I was told).
So these fields should be added generically and then your code should make use of the generic field mapped with your structure.
Quoted 6 lines
To my knowledge (until the APM is public and documents everything), I believe the following will be in place:
VMCB offset
0x3e0-0x3ffis reserved for software Clean bit 31 is reserved for software
SVM intercept exit code0xf0000000is reserved for software
Thanks for the details. I shall modify the code to accommodate this.
Quoted 9 lines
arch/x86/kvm/svm/svm.c +5
-0+#if IS_ENABLED (CONFIG_HYPERV ) +if (hypervisor_is_type (X86_HYPER_MS_HYPERV )) + vmcb_all_clean_mask |=BIT (VMCB_HV_NESTED_ENLIGHTENMENTS ); +#endif +Is there any way to hide all the #if's in this and the other patches so that the .c files are littered with the #if
IS_ENABLED()lines. Put them insvm.hor a newsvm-hv.hfile?
Will do.
Quoted 7 lines
arch/x86/kvm/svm/svm.h enum { · line 56
Quoted 6 lines
*/
VMCB_DIRTY_MAX,arch/x86/kvm/svm/svm.h +3
-0+#if IS_ENABLED (CONFIG_HYPERV ) + VMCB_HV_NESTED_ENLIGHTENMENTS = 31, +#endif Again, this should be generic.
Will do.
Thanks,
Vineeth
PATCH v3 5/7 KVM: SVM: hyper-v: Remote TLB flush for SVM
In reply to Vineeth PillaiEnable remote TLB flush for SVM.
--- arch/x86/kvm/svm/svm.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
arch/x86/kvm/svm/svm.c +38 -0
@@ -37,6 +37,7 @@#include <asm/spec-ctrl.h> #include <asm/cpu_device_id.h> #include <asm/traps.h> +#include <asm/mshyperv.h> #include <asm/virtext.h> #include "trace.h"
@@ -44,6 +45,9 @@#include "svm.h" #include "svm_ops.h" +#include "hyperv.h" +#include "kvm_onhyperv.h" +#define __ex (x) __kvm_handle_fault_on_reboot(x)MODULE_AUTHOR ("Qumranet" );
@@ -931,6 +935,8 @@ static __init void svm_set_cpu_caps(void)kvm_cpu_cap_set (X86_FEATURE_VIRT_SSBD ); } +static struct kvm_x86_ops svm_x86_ops; +static __init int svm_hardware_setup (void ) {int cpu;
@@ -1000,6 +1006,16 @@ static __init int svm_hardware_setup(void)kvm_configure_mmu (npt_enabled,get_max_npt_level (),PG_LEVEL_1G );pr_info ("kvm: Nested Paging %sabled\n" , npt_enabled ?"en" :"dis" ); +#if IS_ENABLED (CONFIG_HYPERV ) +if (ms_hyperv.nested_features &HV_X64_NESTED_ENLIGHTENED_TLB + && npt_enabled) { +pr_info ("kvm: Hyper-V enlightened NPT TLB flush enabled\n" ); + svm_x86_ops.tlb_remote_flush = kvm_hv_remote_flush_tlb; + svm_x86_ops.tlb_remote_flush_with_range = + kvm_hv_remote_flush_tlb_with_range; + } +#endif +if (nrips) {if (!boot_cpu_has (X86_FEATURE_NRIPS )) nrips = false;
@@ -1120,6 +1136,21 @@ static void svm_check_invpcid(struct vcpu_svm *svm) } } +#if IS_ENABLED (CONFIG_HYPERV ) +static inline void hv_init_vmcb (struct vmcb *vmcb) +{ +struct hv_enlightenments *hve = &vmcb->hv_enlightenments; + +if (npt_enabled && + ms_hyperv.nested_features &HV_X64_NESTED_ENLIGHTENED_TLB ) + hve->hv_enlightenments_control.enlightened_npt_tlb =1 ; +} +#else +static inline void hv_init_vmcb (struct vmcb *vmcb) +{ +} +#endif +static void init_vmcb (struct vcpu_svm *svm) {struct vmcb_control_area *control = &svm->vmcb->control;
@@ -1282,6 +1313,8 @@ static void init_vmcb(struct vcpu_svm *svm) } } +hv_init_vmcb (svm->vmcb); +vmcb_mark_all_dirty (svm->vmcb);enable_gif (svm);
@@ -3975,6 +4008,11 @@ static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root, svm->vmcb->control.nested_cr3 = cr3;vmcb_mark_dirty (svm->vmcb,VMCB_NPT ); +#if IS_ENABLED (CONFIG_HYPERV ) +if (kvm_x86_ops.tlb_remote_flush) +kvm_update_arch_tdp_pointer (vcpu->kvm, vcpu, cr3); +#endif +/* Loading L2's CR3 is handled by enter_svm_guest_mode. */ if (!test_bit (VCPU_EXREG_CR3 , (ulong *)&vcpu->arch.regs_avail))return ;
Signature · 1 line
2.25.1
PATCH v3 6/7 KVM: SVM: hyper-v: Enlightened MSR-Bitmap support
In reply to Vineeth PillaiEnlightened MSR-Bitmap as per TLFS:
"The L1 hypervisor may collaborate with the L0 hypervisor to make MSR
accesses more efficient. It can enable enlightened MSR bitmaps by setting the corresponding field in the enlightened VMCS to 1. When enabled, L0 hypervisor does not monitor the MSR bitmaps for changes. Instead, the L1 hypervisor must invalidate the corresponding clean field after making changes to one of the MSR bitmaps."
Enable this for SVM.
Related VMX changes:
commit ceef7d10dfb6 ("KVM: x86: VMX: hyper-v: Enlightened MSR-Bitmap support")
--- arch/x86/kvm/svm/svm.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
arch/x86/kvm/svm/svm.c +27 -0
@@ -650,6 +650,27 @@ static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)return !!test_bit (bit_write, &tmp); } +#if IS_ENABLED (CONFIG_HYPERV ) +static inline void hv_vmcb_dirty_nested_enlightenments (struct kvm_vcpu *vcpu) +{ +struct vmcb *vmcb =to_svm (vcpu)->vmcb; + +/* +* vmcb can be NULL if called during early vcpu init. +* And its okay not to mark vmcb dirty during vcpu init +* as we mark it dirty unconditionally towards end of vcpu +* init phase. +*/ +if (vmcb &&vmcb_is_clean (vmcb,VMCB_HV_NESTED_ENLIGHTENMENTS ) && + vmcb->hv_enlightenments.hv_enlightenments_control.msr_bitmap) +vmcb_mark_dirty (vmcb,VMCB_HV_NESTED_ENLIGHTENMENTS ); +} +#else +static inline void hv_vmcb_dirty_nested_enlightenments (struct kvm_vcpu *vcpu) +{ +} +#endif +static void set_msr_interception_bitmap (struct kvm_vcpu *vcpu,u32 *msrpm,u32 msr,int read,int write) {
@@ -681,6 +702,9 @@ static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm, write ?clear_bit (bit_write, &tmp) :set_bit (bit_write, &tmp); msrpm[offset] = tmp; + +hv_vmcb_dirty_nested_enlightenments (vcpu); + } void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
@@ -1144,6 +1168,9 @@ static inline void hv_init_vmcb(struct vmcb *vmcb)if (npt_enabled && ms_hyperv.nested_features &HV_X64_NESTED_ENLIGHTENED_TLB ) hve->hv_enlightenments_control.enlightened_npt_tlb =1 ; + +if (ms_hyperv.nested_features &HV_X64_NESTED_MSR_BITMAP ) + hve->hv_enlightenments_control.msr_bitmap = 1; }#else static inline void hv_init_vmcb (struct vmcb *vmcb)
Signature · 1 line
2.25.1
PATCH v3 7/7 KVM: SVM: hyper-v: Direct Virtual Flush support
In reply to Vineeth PillaiFrom Hyper-V TLFS:
"The hypervisor exposes hypercalls (HvFlushVirtualAddressSpace,
HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressList, and HvFlushVirtualAddressListEx) that allow operating systems to more efficiently manage the virtual TLB. The L1 hypervisor can choose to allow its guest to use those hypercalls and delegate the responsibility to handle them to the L0 hypervisor. This requires the use of a partition assist page."
Add the Direct Virtual Flush support for SVM.
Related VMX changes:
commit 6f6a657c9998 ("KVM/Hyper-V/VMX: Add direct tlb flush support")
--- arch/x86/kvm/svm/svm.c | 48 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
arch/x86/kvm/svm/svm.c +48 -0
@@ -444,6 +444,32 @@ static void svm_init_osvw(struct kvm_vcpu *vcpu) vcpu->arch.osvw.status |=1 ; } +#if IS_ENABLED (CONFIG_HYPERV ) +static int hv_enable_direct_tlbflush (struct kvm_vcpu *vcpu) +{ +struct hv_enlightenments *hve; +struct hv_partition_assist_pg **p_hv_pa_pg = + &to_kvm_hv (vcpu->kvm)->hv_pa_pg; + +if (!*p_hv_pa_pg) + *p_hv_pa_pg =kzalloc (PAGE_SIZE ,GFP_KERNEL ); + +if (!*p_hv_pa_pg) +return -ENOMEM ; + + hve = (struct hv_enlightenments *)&to_svm (vcpu)->vmcb->hv_enlightenments; + + hve->partition_assist_page =__pa (*p_hv_pa_pg); + hve->hv_vm_id = (unsigned long )vcpu->kvm; +if (!hve->hv_enlightenments_control.nested_flush_hypercall) { + hve->hv_enlightenments_control.nested_flush_hypercall =1 ; +vmcb_mark_dirty (to_svm (vcpu)->vmcb,VMCB_HV_NESTED_ENLIGHTENMENTS ); + } + +return 0 ; +} +#endif +static int has_svm (void ) {const char *msg;
@@ -1038,6 +1064,21 @@ static __init int svm_hardware_setup(void) svm_x86_ops.tlb_remote_flush_with_range = kvm_hv_remote_flush_tlb_with_range; } + +if (ms_hyperv.nested_features &HV_X64_NESTED_DIRECT_FLUSH ) { +pr_info ("kvm: Hyper-V Direct TLB Flush enabled\n" ); +for_each_online_cpu (cpu) { +struct hv_vp_assist_page *vp_ap = +hv_get_vp_assist_page (cpu); + +if (!vp_ap) +continue ; + + vp_ap->nested_control.features.directhypercall =1 ; + } + svm_x86_ops.enable_direct_tlbflush = + hv_enable_direct_tlbflush; + }#endif if (nrips) {
@@ -3922,6 +3963,13 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu) } svm->vmcb->save.cr2 = vcpu->arch.cr2; +#if IS_ENABLED (CONFIG_HYPERV ) +if (svm->vmcb->hv_enlightenments.hv_vp_id !=to_hv_vcpu (vcpu)->vp_index) { + svm->vmcb->hv_enlightenments.hv_vp_id =to_hv_vcpu (vcpu)->vp_index; +vmcb_mark_dirty (svm->vmcb,VMCB_HV_NESTED_ENLIGHTENMENTS ); + } +#endif +/* * Run with all-zero DR6 unless needed, so that we can get the exact cause * of a #DB.
Signature · 1 line
2.25.1