Add Synopsys DesignWare HDMI RX Controller and PHY drivers

RFC New Nelson Costa 2 participants 11 messages May 20, 2021 – May 22, 2021

Subsystems (4)

Device tree bindings Media (V4L/DVB) Generic PHY framework Synopsys DesignWare HDMI rx controller driver

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Nelson Costa

author

2021-05-20 15:48 UTC #3 lore raw

RFC v2 3/9 MAINTAINERS: Add entry for Synopsys DesignWare HDMI drivers

In reply to Nelson Costa

Add an entry for Synopsys DesignWare HDMI Receivers drivers and PHYs.

Signed-off-by Jose Abreu <[email protected]>

Signed-off-by Nelson Costa <[email protected]>

---
 MAINTAINERS | 11 +++++++++++
 1 file changed, 11 insertions(+)

MAINTAINERS +11 -0

index 04e6df9..e0e7b41 100644
@@ -17304,6 +17304,17 @@ S:	Supported
 F:	drivers/net/pcs/pcs-xpcs.c
 F:	include/linux/pcs/pcs-xpcs.h
 
+SYNOPSYS DESIGNWARE HDMI RECEIVERS AND PHY DRIVERS
+M:	Jose Abreu <[email protected]>
+M:	Nelson Costa <[email protected]>
+L:	[email protected]
+S:	Odd Fixes
+F:	Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml
+F:	drivers/media/platform/dwc/*
+F:	drivers/phy/dwc/*
+F:	include/linux/phy/dwc/*
+F:	include/media/dwc/*
+
 SYNOPSYS DESIGNWARE I2C DRIVER
 M:	Jarkko Nikula <[email protected]>
 R:	Andy Shevchenko <[email protected]>

Signature · 1 line

2.7.4

Nelson Costa

author

2021-05-20 15:48 UTC #9 lore raw

RFC v2 8/9 media: dwc: dw-hdmi-rx: Add support for Aspect Ratio

In reply to Nelson Costa

This adds support to get aspect ratio for the current video being received and provide the info through v4l2 API query_dv_timings.

Signed-off-by Nelson Costa <[email protected]>

---
 drivers/media/platform/dwc/dw-hdmi-rx.c | 54 +++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

drivers/media/platform/dwc/dw-hdmi-rx.c +52 -2

index b20eccc..a468a93 100644
@@ -2250,13 +2250,31 @@ static u32 dw_hdmi_get_width(struct dw_hdmi_dev *dw_dev)
 	return width;
 }
 
+static int dw_hdmi_vic_to_cea861(u8 hdmi_vic)
+{
+	switch (hdmi_vic) {
+	case 1:
+		return 95;
+	case 2:
+		return 94;
+	case 3:
+		return 93;
+	case 4:
+		return 98;
+	default:
+		return 0;
+	}
+}
+
 static int dw_hdmi_query_dv_timings(struct v4l2_subdev *sd,
 				    struct v4l2_dv_timings *timings)
 {
 	struct dw_hdmi_dev *dw_dev = to_dw_dev(sd);
 	struct v4l2_bt_timings *bt = &timings->bt;
+	struct v4l2_dv_timings t = {0};
 	bool is_hdmi_vic;
 	u32 htot, hofs;
+	u8 cea861_vic;
 	u32 vtot;
 	u8 vic;

@@ -2351,8 +2369,40 @@ static int dw_hdmi_query_dv_timings(struct v4l2_subdev *sd,
 		}
 	}
 
-	dev_dbg(dw_dev->dev, "%s: width=%u, height=%u, mbuscode=%u\n", __func__,
-		bt->width, bt->height, dw_hdmi_get_mbus_code(dw_dev));
+	if (is_hdmi_vic)
+		cea861_vic = dw_hdmi_vic_to_cea861(bt->hdmi_vic);
+	else
+		cea861_vic = vic;
+
+	/* picture aspect ratio based on v4l2 dv timings array */
+	if (v4l2_find_dv_timings_cea861_vic(&t, cea861_vic)) {
+		/* when the numerator/denominator are zero means that the
+		 * picture aspect ratio is the same of the active measures ratio
+		 */
+		if (!t.bt.picture_aspect.numerator) {
+			unsigned long n, d;
+
+			rational_best_approximation(t.bt.width, t.bt.height,
+						    t.bt.width, t.bt.height,
+						    &n, &d);
+			t.bt.picture_aspect.numerator = n;
+			t.bt.picture_aspect.denominator = d;
+		}
+
+		bt->picture_aspect = t.bt.picture_aspect;
+	} else {
+		bt->picture_aspect.numerator = 0;
+		bt->picture_aspect.denominator = 0;
+		dev_dbg(dw_dev->dev,
+			"%s: cea861_vic=%d was not found in v4l2 dv timings",
+			__func__, cea861_vic);
+	}
+
+	dev_dbg(dw_dev->dev,
+		"%s: width=%u, height=%u, mbuscode=%u, cea861_vic=%d, ar={%d,%d}\n",
+		__func__, bt->width, bt->height, dw_hdmi_get_mbus_code(dw_dev),
+		cea861_vic, bt->picture_aspect.numerator,
+		bt->picture_aspect.denominator);
 
 	return 0;
 }

Signature · 1 line

2.7.4

Nelson Costa

author

2021-05-20 15:48 UTC #1 lore raw

RFC v2 1/9 dt-bindings: phy: Document Synopsys DesignWare HDMI RX PHYs e405 and e406

In reply to Nelson Costa

Document the device tree bindings for the Synopsys DesignWare HDMI RX PHYs e405 and e406.

Signed-off-by Nelson Costa <[email protected]>

---
 .../bindings/phy/snps,phy-dw-hdmi-e40x.yaml        | 93 ++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/snps,phy-dw-hdmi-e40x.yaml

Documentation/devicetree/bindings/phy/snps,phy-dw-hdmi-e40x.yaml new file +93 -0

new file mode 100644
index 0000000..25bece5
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/snps,phy-dw-hdmi-e40x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare HDMI PHYs e405/e406 Device Tree Bindings
+
+maintainers:
+  - Jose Abreu <[email protected]>
+  - Nelson Costa <[email protected]>
+
+description: |
+  The Synopsys DesignWare HDMI PHYs e405/e406 are HDMI 2.0 PHY Receivers that
+  receive video and audio, and send to the HDMI RX Controller.
+
+properties:
+  compatible:
+    oneOf:
+      - const: snps,dw-hdmi-phy-e405
+      - const: snps,dw-hdmi-phy-e406
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: |
+      phandle to the configuration clock
+
+  clock-names:
+    const: cfg
+
+  "#phy-cells":
+    const: 0
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description: |
+      Output port node, multiple endpoints describing the PHY HDMI inputs data
+      connected to the HDMI RX Controller.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+    parent {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+        hdmi_e406_phy: hdmi-phy@fc {
+            compatible = "snps,dw-hdmi-phy-e406";
+            reg = <0xfc>;
+
+            clocks = <&dw_hdmi_refclk>;
+            clock-names = "cfg";
+
+            #phy-cells = <0>;
+
+            port {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                hdmi_e406_phy_0: endpoint@0 {
+                    reg = <0>;
+                    remote-endpoint = <&hdmi_rx_0>;
+                };
+
+                hdmi_e406_phy_1: endpoint@1 {
+                    reg = <1>;
+                    remote-endpoint = <&hdmi_rx_1>;
+                };
+
+                hdmi_e406_phy_2: endpoint@2 {
+                    reg = <2>;
+                    remote-endpoint = <&hdmi_rx_2>;
+                };
+
+                hdmi_e406_phy_3: endpoint@3 {
+                    reg = <3>;
+                    remote-endpoint = <&hdmi_rx_3>;
+                };
+            };
+        };
+    };

Signature · 1 line

2.7.4

Nelson Costa

author

2021-05-20 15:48 UTC #2 lore raw

RFC v2 2/9 dt-bindings: media: Document Synopsys DesignWare HDMI RX

In reply to Nelson Costa

Document the device tree bindings for the Synopsys DesignWare HDMI RX Controller.

Signed-off-by Jose Abreu <[email protected]>

Signed-off-by Nelson Costa <[email protected]>

---
 .../devicetree/bindings/media/snps,dw-hdmi-rx.yaml | 98 ++++++++++++++++++++++
 1 file changed, 98 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml

Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml new file +98 -0

new file mode 100644
index 0000000..4f2169e
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare HDMI RX Controller Device Tree Bindings
+
+maintainers:
+  - Jose Abreu <[email protected]>
+  - Nelson Costa <[email protected]>
+
+description: |
+  The Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 is an HDMI 2.0
+  Receiver solution that is able to decode video and audio.
+
+properties:
+  compatible:
+    const: snps,dw-hdmi-rx
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: |
+      phandle to the configuration clock
+
+  clock-names:
+    const: cfg
+
+  phys:
+    maxItems: 1
+    description: |
+      phandle for the HDMI RX PHY
+
+  phy-names:
+    const: hdmi-phy
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description: |
+      Input port node, multiple endpoints describing the HDMI RX data connected
+      to the HDMI PHY receiver.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+    hdmi_rx: hdmi-rx@0 {
+        compatible = "snps,dw-hdmi-rx";
+        reg = <0x0 0x10000>;
+        interrupts = <1 2>;
+
+        clocks = <&dw_hdmi_refclk>;
+        clock-names = "cfg";
+
+        phys = <&hdmi_e406_phy>;
+        phy-names = "hdmi-phy";
+
+        port {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            hdmi_rx_0: endpoint@0 {
+                reg = <0>;
+                remote-endpoint = <&hdmi_e406_phy_0>;
+            };
+
+            hdmi_rx_1: endpoint@1 {
+                reg = <1>;
+                remote-endpoint = <&hdmi_e406_phy_1>;
+            };
+
+            hdmi_rx_2: endpoint@2 {
+                reg = <2>;
+                remote-endpoint = <&hdmi_e406_phy_2>;
+            };
+
+            hdmi_rx_3: endpoint@3 {
+                reg = <3>;
+                remote-endpoint = <&hdmi_e406_phy_3>;
+            };
+        };
+    };

Signature · 1 line

2.7.4

Nelson Costa

author

2021-05-20 15:48 UTC #0 lore raw

v2 cover Add Synopsys DesignWare HDMI RX Controller and PHY drivers

This series implements support for the Synopsys DesignWare HDMI RX Controller and PHYs e405/e406 drivers, being compliant with standard HDMI 1.4 and HDMI 2.0.

The Controller + PHY pipeline can be integrated into a fully featured system that can be able to receive video up to 4k@60Hz with basic audio.

This solution is mainly composed by two modules: phy-dw-hdmi-e40x and dw-hdmi-rx.

phy-dw-hdmi-e40x: it's the PHY (Physical Layer) driver that implements support for Synopsys DesignWare e405 and e406 PHYs. It is responsible to configure the PHY and equalize it for the best settings, in order to receive and decode video to be delivered to the Controller. This driver is integrated in the PHY subsystem.
The main features of this module are:
- Equalizer algorithm that chooses the phy best settings according to the detected HDMI cable characteristics
- Support for scrambling
- Support for color depth up to 48bpp
- Support for HDMI 2.0 modes up to 6G (HDMI 4k@60Hz).

dw-hdmi-rx: it's the Controller driver that implements support for Synopsys DesignWare HDMI RX Controller. It is responsible to manage and handle the PHY (through the PHY API) and the Controller configurations in order to configure the video and audio pipeline.
This driver is implemented as a standard V4L2 subdevice.
The main features of this module are:
- Support for scrambling
- Support for color depth up to 48bpp
- Support for HDMI 2.0 modes up to 6G (HDMI 4k@60Hz)
- Support for RGB, YCC444, YCC422 and YCC420
- Support for basic audio (LPCM 2ch, 32KHz/44.1KHz/48KHz, 16bit)
- Support for Aspect Ratio
- Support for CEC
- Internal state machine that reconfigures phy and controller
- JTAG communication with phy
- Inter-module communication with phy driver:
* through the PHY API using the phy reference "hdmi-phy"
* through the callbacks that phy dwc driver needs.
- Debug write/read ioctls

NOTES: This patch series has two specific patches (Patch [4/8] and [7/8]) one for the PHY API and the other for v4l2-dv-timings.

Patch [4/8] adds phy standard HDMI opts to the phy API that contributes for the PHY subsystem, which allows to integrate the PHY driver in the PHY subsystem using this new HDMI opts structure, because there are hdmi options that are needed to pass between the Controller and PHY drivers using the standard API.

Patch [7/8] adds more CEA/CTA-861 video format timings that contributes to the v4l2 media subsystem, which in our case is needed to provide information about the Aspect Ratio.

version 2:
- The original media Device Tree bindings was divided in two independent Device Trees:
* Device tree for PHYs e405/e406 in PHY dt bindings
* Device tree for HDMI RX Controller in media dt bindings
- Add OF graph ports connection model in the Device Trees (Thanks to Laurent Pinchart <[email protected]>)
- The HDMI RX Controller was adjusted in order to work with the new Device Trees Model:
* the "input-count" field was removed from original Device Tree and now the count is done based on port child count.
* Changed the way to get the phy node, removing the dependency as child node of Controller node
- Fix reported kernel test robot issues:
* Fix "warning: no previous prototype for 'dw_phy_eq_settings'"
* Fix "warning: integer literal is too large to be represented in type 'long', interpreting as 'unsigned long' per C89; this literal will have type 'long long' in C99 onwards [-Wc99-compat]"

Reported-by kernel test robot <[email protected]>

- Fix phy power off/on issue when the system startups without the cable connected.
- Fix "CHECK: Comparison to NULL could be written "of_device_get_match_data""

Nelson Costa (9):
dt-bindings: phy: Document Synopsys DesignWare HDMI RX PHYs e405 and

    e406

dt-bindings: media: Document Synopsys DesignWare HDMI RX
MAINTAINERS: Add entry for Synopsys DesignWare HDMI drivers
phy: Add PHY standard HDMI opts to the PHY API
phy: dwc: Add Synopsys DesignWare HDMI RX PHYs e405 and e406 Driver
media: platform: Add Synopsys DesignWare HDMI RX Controller Driver
media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings
media: dwc: dw-hdmi-rx: Add support for Aspect Ratio
media: dwc: dw-hdmi-rx: Add support for CEC

 .../devicetree/bindings/media/snps,dw-hdmi-rx.yaml |   98 +
 .../bindings/phy/snps,phy-dw-hdmi-e40x.yaml        |   93 +
 MAINTAINERS                                        |   11 +
 drivers/media/platform/Kconfig                     |    2 +
 drivers/media/platform/Makefile                    |    1 +
 drivers/media/platform/dwc/Kconfig                 |   20 +
 drivers/media/platform/dwc/Makefile                |    3 +
 drivers/media/platform/dwc/dw-hdmi-rx.c            | 3542 ++++++++++++++++++++
 drivers/media/platform/dwc/dw-hdmi-rx.h            |  533 +++
 drivers/media/v4l2-core/v4l2-dv-timings.c          |  139 +
 drivers/phy/Kconfig                                |    1 +
 drivers/phy/Makefile                               |    1 +
 drivers/phy/dwc/Kconfig                            |   20 +
 drivers/phy/dwc/Makefile                           |    9 +
 drivers/phy/dwc/phy-dw-hdmi-e405.c                 |  497 +++
 drivers/phy/dwc/phy-dw-hdmi-e406.c                 |  475 +++
 drivers/phy/dwc/phy-dw-hdmi-e40x-core.c            |  514 +++
 drivers/phy/dwc/phy-dw-hdmi-e40x.h                 |  219 ++
 include/linux/phy/dwc/dw-hdmi-phy-pdata.h          |   73 +
 include/linux/phy/phy-hdmi.h                       |  102 +
 include/linux/phy/phy.h                            |    7 +-
 include/media/dwc/dw-hdmi-rx-pdata.h               |  126 +
 include/uapi/linux/v4l2-dv-timings.h               | 1595 ++++++++-
 23 files changed, 8079 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/snps,phy-dw-hdmi-e40x.yaml
 create mode 100644 drivers/media/platform/dwc/Kconfig
 create mode 100644 drivers/media/platform/dwc/Makefile
 create mode 100644 drivers/media/platform/dwc/dw-hdmi-rx.c
 create mode 100644 drivers/media/platform/dwc/dw-hdmi-rx.h
 create mode 100644 drivers/phy/dwc/Kconfig
 create mode 100644 drivers/phy/dwc/Makefile
 create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e405.c
 create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e406.c
 create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e40x-core.c
 create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e40x.h
 create mode 100644 include/linux/phy/dwc/dw-hdmi-phy-pdata.h
 create mode 100644 include/linux/phy/phy-hdmi.h
 create mode 100644 include/media/dwc/dw-hdmi-rx-pdata.h

Signature · 1 line

2.7.4

Nelson Costa

author

2021-05-20 15:48 UTC #4 lore raw

RFC v2 4/9 phy: Add PHY standard HDMI opts to the PHY API

This adds the new options to give support for HDMI PHYs in a standard way. This is mainly useful when the HDMI PHY requires parameters to be passed by "phy_configure" function.

For this, the new struct phy_configure_opts_hdmi
was added with the required generic and standard
parameters.

Signed-off-by Nelson Costa <[email protected]>

---
 include/linux/phy/phy-hdmi.h | 102 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/phy/phy.h      |   7 ++-
 2 files changed, 108 insertions(+), 1 deletion(-)
 create mode 100644 include/linux/phy/phy-hdmi.h

include/linux/phy/phy-hdmi.h new file +102 -0

new file mode 100644
index 0000000..62334f4
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 - present Synopsys, Inc. and/or its affiliates.
+ * HDMI generic PHY options.
+ *
+ * Author: Nelson Costa <[email protected]>
+ */
+#ifndef __PHY_HDMI_H_
+#define __PHY_HDMI_H_
+
+#include <linux/types.h>
+
+/**
+ * struct phy_configure_opts_hdmi - HDMI PHY configuration set
+ *
+ * This structure is used to represent the configuration state of an
+ * HDMI PHY.
+ */
+struct phy_configure_opts_hdmi {
+	/**
+	 * @color_depth:
+	 *
+	 * Color depth, as specified by HDMI specification, represents the
+	 * number of bits per pixel.
+	 *
+	 * Allowed values: 24, 30, 36, 48
+	 *
+	 */
+	u8 color_depth;
+
+	/**
+	 * @tmds_bit_clock_ratio:
+	 *
+	 * Flag indicating, as specified by HDMI specification, the relation
+	 * between TMDS Clock Rate and TMDS Character Rate.
+	 *
+	 * As specified by HDMI specification:
+	 *
+	 * tmds_bit_clock_ratio = 0, for TMDS Character Rates <= 340 Mcsc
+	 * (TMDS Clock Rate = TMDS Character Rate)
+	 *
+	 * tmds_bit_clock_ratio = 1, for TMDS Character Rates > 340 Mcsc
+	 * (TMDS Clock Rate = TMDS Character Rate / 4)
+	 *
+	 */
+	u8 tmds_bit_clock_ratio;
+
+	/**
+	 * @scrambling:
+	 *
+	 * Scrambling, as specified by HDMI specification, enables the technique
+	 * to reduce the EMI/RFI.
+	 *
+	 */
+	u8 scrambling;
+
+	/**
+	 * @calibration_acq:
+	 *
+	 * Calibration acquisitions number for the calibration algorithm.
+	 *
+	 */
+	unsigned int calibration_acq;
+
+	/**
+	 * @calibration_force:
+	 *
+	 * Flag indicating, to force calibration algorithm even if the MPLL
+	 * status didn't change from previous run calibration.
+	 *
+	 */
+	u8 calibration_force;
+
+	/**
+	 * @set_color_depth:
+	 *
+	 * Flag indicating, whether or not reconfigure deep_color
+	 * to requested values.
+	 *
+	 */
+	u8 set_color_depth : 1;
+
+	/**
+	 * @set_tmds_bit_clock_ratio:
+	 *
+	 * Flag indicating, whether or not reconfigure tmds_bit_clock_ratio
+	 * to requested values.
+	 *
+	 */
+	u8 set_tmds_bit_clock_ratio : 1;
+
+	/**
+	 * @set_scrambling:
+	 *
+	 * Flag indicating, whether or not reconfigure scrambling
+	 * to requested values.
+	 *
+	 */
+	u8 set_scrambling : 1;
+};
+
+#endif /* __PHY_HDMI_H_ */

include/linux/phy/phy.h +6 -1

index e435bdb..8b1aaa4 100644
@@ -18,6 +18,7 @@
 
 #include <linux/phy/phy-dp.h>
 #include <linux/phy/phy-mipi-dphy.h>
+#include <linux/phy/phy-hdmi.h>
 
 struct phy;

@@ -41,7 +42,8 @@ enum phy_mode {
 	PHY_MODE_MIPI_DPHY,
 	PHY_MODE_SATA,
 	PHY_MODE_LVDS,
-	PHY_MODE_DP
+	PHY_MODE_DP,
+	PHY_MODE_HDMI
 };
 
 /**

@@ -51,10 +53,13 @@ enum phy_mode {
  *		the MIPI_DPHY phy mode.
  * @dp:		Configuration set applicable for phys supporting
  *		the DisplayPort protocol.
+ * @hdmi	Configuration set applicable for phys supporting
+ *		the HDMI protocol.
  */
 union phy_configure_opts {
 	struct phy_configure_opts_mipi_dphy	mipi_dphy;
 	struct phy_configure_opts_dp		dp;
+	struct phy_configure_opts_hdmi		hdmi;
 };
 
 /**

Signature · 1 line

2.7.4

Nelson Costa

author

2021-05-20 15:48 UTC #10 lore raw

RFC v2 9/9 media: dwc: dw-hdmi-rx: Add support for CEC

In reply to Nelson Costa

This adds support for the optional HDMI CEC feature for the Synopsys DesignWare HDMI RX Controller.

It uses the generic CEC framework interface.

Signed-off-by Jose Abreu <[email protected]>

Signed-off-by Nelson Costa <[email protected]>

---
 drivers/media/platform/dwc/Kconfig      |  10 ++
 drivers/media/platform/dwc/dw-hdmi-rx.c | 259 +++++++++++++++++++++++++++++++-
 drivers/media/platform/dwc/dw-hdmi-rx.h |  57 +++++++
 3 files changed, 324 insertions(+), 2 deletions(-)

drivers/media/platform/dwc/Kconfig +10 -0

index ef2a6435..4d39be7 100644
@@ -8,3 +8,13 @@ config VIDEO_DWC_HDMI_RX
 
 	  To compile this driver as a module, choose M here. The module
 	  will be called dw-hdmi-rx.
+
+config VIDEO_DWC_HDMI_RX_CEC
+	bool "Synopsys DesignWare HDMI Receiver CEC support"
+	depends on VIDEO_DWC_HDMI_RX
+	select CEC_CORE
+	help
+	  When selected the Synopsys DesignWare HDMI RX controller
+	  will support the optional HDMI CEC feature.
+
+	  It uses the generic CEC framework interface.

drivers/media/platform/dwc/dw-hdmi-rx.c +257 -2

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drivers/media/platform/dwc/dw-hdmi-rx.h +57 -0

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Signature · 1 line

2.7.4

Nelson Costa

author

2021-05-20 15:48 UTC #5 lore raw

RFC v2 5/9 phy: dwc: Add Synopsys DesignWare HDMI RX PHYs e405 and e406 Driver

In reply to Nelson Costa

This adds support for the Synopsys DesignWare HDMI RX PHYs e405 and e406. The PHY receives and decodes HDMI video that is delivered to a controller.

Main features included in this driver are:
- Equalizer algorithm that chooses the PHY best settings according to the detected HDMI cable characteristics.
- Support for scrambling
- Support for color depth up to 48bpp
- Support for HDMI 2.0 modes up to 6G (HDMI 4k@60Hz).

The driver was implemented using the standard PHY API in order to provide a standard access to the required callbacks to be handled by the controller through the phy_ops.

There is a bidirectional communication between controller and PHY:
- controller -> PHY : communication is done using the PHY API
- controller <- PHY : communication is done using the callbacks, provided by the controller, which are required to handle the PHY such as: read/write, pddq, reset, etc.
This callback functions are specified in struct dw_phy_pdata from 'include/linux/phy/dwc/dw-hdmi-phy-pdata.h'.

Signed-off-by Jose Abreu <[email protected]>

Signed-off-by Nelson Costa <[email protected]>

---
 drivers/phy/Kconfig                       |   1 +
 drivers/phy/Makefile                      |   1 +
 drivers/phy/dwc/Kconfig                   |  20 ++
 drivers/phy/dwc/Makefile                  |   9 +
 drivers/phy/dwc/phy-dw-hdmi-e405.c        | 497 +++++++++++++++++++++++++++++
 drivers/phy/dwc/phy-dw-hdmi-e406.c        | 475 +++++++++++++++++++++++++++
 drivers/phy/dwc/phy-dw-hdmi-e40x-core.c   | 514 ++++++++++++++++++++++++++++++
 drivers/phy/dwc/phy-dw-hdmi-e40x.h        | 219 +++++++++++++
 include/linux/phy/dwc/dw-hdmi-phy-pdata.h |  73 +++++
 9 files changed, 1809 insertions(+)
 create mode 100644 drivers/phy/dwc/Kconfig
 create mode 100644 drivers/phy/dwc/Makefile
 create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e405.c
 create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e406.c
 create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e40x-core.c
 create mode 100644 drivers/phy/dwc/phy-dw-hdmi-e40x.h
 create mode 100644 include/linux/phy/dwc/dw-hdmi-phy-pdata.h

drivers/phy/Kconfig +1 -0

index 68d9c2f..db7c4b1 100644
@@ -65,6 +65,7 @@ source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
 source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/dwc/Kconfig"
 source "drivers/phy/freescale/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
 source "drivers/phy/ingenic/Kconfig"

drivers/phy/Makefile +1 -0

index 32261e1..ac63979 100644
@@ -13,6 +13,7 @@ obj-y					+= allwinner/	\
 					   amlogic/	\
 					   broadcom/	\
 					   cadence/	\
+					   dwc/		\
 					   freescale/	\
 					   hisilicon/	\
 					   ingenic/	\

drivers/phy/dwc/Kconfig new file +20 -0

new file mode 100644
index 0000000..ab451d8
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0
+config VIDEO_DWC_HDMI_PHY_E40X
+	tristate "Synopsys DesignWare HDMI RX PHYs e405 and e406 driver"
+	select GENERIC_PHY
+	help
+	  Support for Synopsys DesignWare HDMI RX PHYs versions
+	  e405 and e406.
+
+	  To compile this driver as a module, choose M here. The module
+	  will be called phy-dw-hdmi-e40x.
+
+config VIDEO_DWC_HDMI_PHY_E40X_SUPPORT_TESTCHIP
+	bool "Synopsys DesignWare HDMI RX PHYs e405/e406 Test Chip Support"
+	depends on VIDEO_DWC_HDMI_PHY_E40X
+	help
+	  Support for Synopsys DesignWare HDMI RX PHYs e405/e406 with Test Chip.
+
+	  To have support for HDMI RX PHYs e405/e406 Test Chip, choose Y here.
+	  It will enable Test Chip additional requirements, for example enable
+	  the z calibration requirement during the PHY configuration.

drivers/phy/dwc/Makefile new file +9 -0

new file mode 100644
index 0000000..52a5b6b
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the PHY drivers.
+#
+
+phy-dw-hdmi-e40x-y			:= phy-dw-hdmi-e40x-core.o
+phy-dw-hdmi-e40x-y			+= phy-dw-hdmi-e405.o
+phy-dw-hdmi-e40x-y			+= phy-dw-hdmi-e406.o
+obj-$(CONFIG_VIDEO_DWC_HDMI_PHY_E40X)	+= phy-dw-hdmi-e40x.o

drivers/phy/dwc/phy-dw-hdmi-e405.c new file +497 -0

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drivers/phy/dwc/phy-dw-hdmi-e406.c new file +475 -0

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drivers/phy/dwc/phy-dw-hdmi-e40x-core.c new file +514 -0

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drivers/phy/dwc/phy-dw-hdmi-e40x.h new file +219 -0

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include/linux/phy/dwc/dw-hdmi-phy-pdata.h new file +73 -0

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Signature · 1 line

2.7.4

Nelson Costa

author

2021-05-20 15:48 UTC #6 lore raw

RFC v2 6/9 media: platform: Add Synopsys DesignWare HDMI RX Controller Driver

In reply to Nelson Costa

This is an initial submission for the Synopsys DesignWare HDMI RX Controller Driver. It is responsible to manage and handle the PHY (through the PHY API) and the Controller configurations in order to configure the video and audio pipeline.

This driver is implemented as a standard V4L2 subdevice. The main features of this module are:
- Support for scrambling
- Support for color depth up to 48bpp
- Support for HDMI 2.0 modes up to 6G (HDMI 4k@60Hz)
- Support for RGB, YCC444, YCC422 and YCC420
- Support for basic audio (LPCM 2ch, 32KHz/44.1KHz/48KHz, 16bit)
- Support for Aspect Ratio
- Support for CEC
- Internal state machine that reconfigures PHY and controller
- JTAG communication with PHY
- Inter-module communication with PHY driver:
* through the PHY API using the PHY reference "hdmi-phy"
* through the callbacks that PHY DWC driver needs.
- Debug write/read ioctls.

Signed-off-by Jose Abreu <[email protected]>

Signed-off-by Nelson Costa <[email protected]>

---
 drivers/media/platform/Kconfig          |    2 +
 drivers/media/platform/Makefile         |    1 +
 drivers/media/platform/dwc/Kconfig      |   10 +
 drivers/media/platform/dwc/Makefile     |    3 +
 drivers/media/platform/dwc/dw-hdmi-rx.c | 3237 +++++++++++++++++++++++++++++++
 drivers/media/platform/dwc/dw-hdmi-rx.h |  476 +++++
 include/media/dwc/dw-hdmi-rx-pdata.h    |  126 ++
 7 files changed, 3855 insertions(+)
 create mode 100644 drivers/media/platform/dwc/Kconfig
 create mode 100644 drivers/media/platform/dwc/Makefile
 create mode 100644 drivers/media/platform/dwc/dw-hdmi-rx.c
 create mode 100644 drivers/media/platform/dwc/dw-hdmi-rx.h
 create mode 100644 include/media/dwc/dw-hdmi-rx-pdata.h

drivers/media/platform/Kconfig +2 -0

index b238a92..20db68d 100644
@@ -29,6 +29,8 @@ source "drivers/media/platform/cadence/Kconfig"
 
 source "drivers/media/platform/davinci/Kconfig"
 
+source "drivers/media/platform/dwc/Kconfig"
+
 source "drivers/media/platform/omap/Kconfig"
 
 config VIDEO_ASPEED

drivers/media/platform/Makefile +1 -0

index eedc14a..955aae6 100644
@@ -6,6 +6,7 @@
 obj-$(CONFIG_VIDEO_ALLEGRO_DVT)		+= allegro-dvt/
 obj-$(CONFIG_VIDEO_ASPEED)		+= aspeed-video.o
 obj-$(CONFIG_VIDEO_CADENCE)		+= cadence/
+obj-y					+= dwc/
 obj-$(CONFIG_VIDEO_VIA_CAMERA) += via-camera.o
 obj-$(CONFIG_VIDEO_CAFE_CCIC) += marvell-ccic/
 obj-$(CONFIG_VIDEO_MMP_CAMERA) += marvell-ccic/

drivers/media/platform/dwc/Kconfig new file +10 -0

new file mode 100644
index 0000000..ef2a6435
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+config VIDEO_DWC_HDMI_RX
+	tristate "Synopsys DesignWare HDMI Receiver driver"
+	depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
+	help
+	  Support for Synopsys DesignWare HDMI RX Controller.
+	  This driver supports HDMI 2.0 version.
+
+	  To compile this driver as a module, choose M here. The module
+	  will be called dw-hdmi-rx.

drivers/media/platform/dwc/Makefile new file +3 -0

new file mode 100644
index 0000000..fddd30c
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_VIDEO_DWC_HDMI_RX) += dw-hdmi-rx.o

drivers/media/platform/dwc/dw-hdmi-rx.c new file +3237 -0

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drivers/media/platform/dwc/dw-hdmi-rx.h new file +476 -0

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include/media/dwc/dw-hdmi-rx-pdata.h new file +126 -0

126 lines not on this page · raw message

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Signature · 1 line

2.7.4

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Nelson Costa

author

2021-05-20 15:48 UTC #8 lore raw

RFC v2 7/9 media: v4l2-dv-timings: Add more CEA/CTA-861 video format timings

In reply to Nelson Costa

This extends the support for more video format timings based on SPECs CEA-861-F and CTA-861-G.

NOTE: For the newer SPECs the CEA was unified to the CTA. The CTA-861-G then includes the CEA-861-F timings besides the new timings that are specified.

CEA-861-F: Specifies the Video timings for VICs 1-107.
CTA-861-G: Specifies the Video timings for VICs 1-107, 108-127, 193-219.

With this patch, the array v4l2_dv_timings_presets has support for all video timings specified in CTA-861-G.

Signed-off-by Nelson Costa <[email protected]>

---
 drivers/media/v4l2-core/v4l2-dv-timings.c |  139 +++
 include/uapi/linux/v4l2-dv-timings.h      | 1595 ++++++++++++++++++++++++++++-
 2 files changed, 1733 insertions(+), 1 deletion(-)

drivers/media/v4l2-core/v4l2-dv-timings.c +139 -0

index 230d65a..0766e0c 100644
@@ -133,6 +133,145 @@ const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {
 	V4L2_DV_BT_CEA_4096X2160P50,
 	V4L2_DV_BT_DMT_4096X2160P59_94_RB,
 	V4L2_DV_BT_CEA_4096X2160P60,
+	V4L2_DV_BT_CEA_720X480P60_PA16_9,
+	V4L2_DV_BT_CEA_720X480I60_PA16_9,
+	V4L2_DV_BT_CEA_720X240P60_VTOT262_PA4_3,
+	V4L2_DV_BT_CEA_720X240P60_VTOT263_PA4_3,
+	V4L2_DV_BT_CEA_720X240P60_VTOT262_PA16_9,
+	V4L2_DV_BT_CEA_720X240P60_VTOT263_PA16_9,
+	V4L2_DV_BT_CEA_2880X480I60_PA4_3,
+	V4L2_DV_BT_CEA_2880X480I60_PA16_9,
+	V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA4_3,
+	V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA4_3,
+	V4L2_DV_BT_CEA_2880X240P60_VTOT262_PA16_9,
+	V4L2_DV_BT_CEA_2880X240P60_VTOT263_PA16_9,
+	V4L2_DV_BT_CEA_1440X480P60_PA4_3,
+	V4L2_DV_BT_CEA_1440X480P60_PA16_9,
+	V4L2_DV_BT_CEA_720X576P50_PA16_9,
+	V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
+	V4L2_DV_BT_CEA_720X576I50_PA16_9,
+	V4L2_DV_BT_CEA_720X288P50_VTOT312_PA4_3,
+	V4L2_DV_BT_CEA_720X288P50_VTOT313_PA4_3,
+	V4L2_DV_BT_CEA_720X288P50_VTOT314_PA4_3,
+	V4L2_DV_BT_CEA_720X288P50_VTOT312_PA16_9,
+	V4L2_DV_BT_CEA_720X288P50_VTOT313_PA16_9,
+	V4L2_DV_BT_CEA_720X288P50_VTOT314_PA16_9,
+	V4L2_DV_BT_CEA_2880X576I50_PA4_3,
+	V4L2_DV_BT_CEA_2880X576I50_PA16_9,
+	V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA4_3,
+	V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA4_3,
+	V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA4_3,
+	V4L2_DV_BT_CEA_2880X288P50_VTOT312_PA16_9,
+	V4L2_DV_BT_CEA_2880X288P50_VTOT313_PA16_9,
+	V4L2_DV_BT_CEA_2880X288P50_VTOT314_PA16_9,
+	V4L2_DV_BT_CEA_1440X576P50_PA4_3,
+	V4L2_DV_BT_CEA_1440X576P50_PA16_9,
+	V4L2_DV_BT_CEA_2880X480P60_PA4_3,
+	V4L2_DV_BT_CEA_2880X480P60_PA16_9,
+	V4L2_DV_BT_CEA_2880X576P50_PA4_3,
+	V4L2_DV_BT_CEA_2880X576P50_PA16_9,
+	V4L2_DV_BT_CEA_1920X1080I50_PA16_9,
+	V4L2_DV_BT_CEA_1920X1080I100_PA16_9,
+	V4L2_DV_BT_CEA_1280X720P100_PA16_9,
+	V4L2_DV_BT_CEA_720X576P100_PA4_3,
+	V4L2_DV_BT_CEA_720X576P100_PA16_9,
+	V4L2_DV_BT_CEA_1440X576I100_PA4_3,
+	V4L2_DV_BT_CEA_1440X576I100_PA16_9,
+	V4L2_DV_BT_CEA_1920X1080I120_PA16_9,
+	V4L2_DV_BT_CEA_1280X720P120_PA16_9,
+	V4L2_DV_BT_CEA_720X480P120_PA4_3,
+	V4L2_DV_BT_CEA_720X480P120_PA16_9,
+	V4L2_DV_BT_CEA_1440X480I120_PA4_3,
+	V4L2_DV_BT_CEA_1440X480I120_PA16_9,
+	V4L2_DV_BT_CEA_720X576P200_PA4_3,
+	V4L2_DV_BT_CEA_720X576P200_PA16_9,
+	V4L2_DV_BT_CEA_1440X576I200_PA4_3,
+	V4L2_DV_BT_CEA_1440X576I200_PA16_9,
+	V4L2_DV_BT_CEA_720X480P240_PA4_3,
+	V4L2_DV_BT_CEA_720X480P240_PA16_9,
+	V4L2_DV_BT_CEA_1440X480I240_PA4_3,
+	V4L2_DV_BT_CEA_1440X480I240_PA16_9,
+	V4L2_DV_BT_CEA_1920X1080P120_PA16_9,
+	V4L2_DV_BT_CEA_1920X1080P100_PA16_9,
+	V4L2_DV_BT_CEA_1280X720P24_PA64_27,
+	V4L2_DV_BT_CEA_1280X720P25_PA64_27,
+	V4L2_DV_BT_CEA_1280X720P30_PA64_27,
+	V4L2_DV_BT_CEA_1280X720P50_PA64_27,
+	V4L2_DV_BT_CEA_1280X720P60_PA64_27,
+	V4L2_DV_BT_CEA_1280X720P100_PA64_27,
+	V4L2_DV_BT_CEA_1280X720P120_PA64_27,
+	V4L2_DV_BT_CEA_1920X1080P24_PA64_27,
+	V4L2_DV_BT_CEA_1920X1080P25_PA64_27,
+	V4L2_DV_BT_CEA_1920X1080P30_PA64_27,
+	V4L2_DV_BT_CEA_1920X1080P50_PA64_27,
+	V4L2_DV_BT_CEA_1920X1080P60_PA64_27,
+	V4L2_DV_BT_CEA_1920X1080P100_PA64_27,
+	V4L2_DV_BT_CEA_1920X1080P120_PA64_27,
+	V4L2_DV_BT_CEA_1680X720P24_PA64_27,
+	V4L2_DV_BT_CEA_1680X720P25_PA64_27,
+	V4L2_DV_BT_CEA_1680X720P30_PA64_27,
+	V4L2_DV_BT_CEA_1680X720P50_PA64_27,
+	V4L2_DV_BT_CEA_1680X720P60_PA64_27,
+	V4L2_DV_BT_CEA_1680X720P100_PA64_27,
+	V4L2_DV_BT_CEA_1680X720P120_PA64_27,
+	V4L2_DV_BT_CEA_2560X1080P24_PA64_27,
+	V4L2_DV_BT_CEA_2560X1080P25_PA64_27,
+	V4L2_DV_BT_CEA_2560X1080P30_PA64_27,
+	V4L2_DV_BT_CEA_2560X1080P50_PA64_27,
+	V4L2_DV_BT_CEA_2560X1080P60_PA64_27,
+	V4L2_DV_BT_CEA_2560X1080P100_PA64_27,
+	V4L2_DV_BT_CEA_2560X1080P120_PA64_27,
+	V4L2_DV_BT_CEA_3840X2160P24_PA64_27,
+	V4L2_DV_BT_CEA_3840X2160P25_PA64_27,
+	V4L2_DV_BT_CEA_3840X2160P30_PA64_27,
+	V4L2_DV_BT_CEA_3840X2160P50_PA64_27,
+	V4L2_DV_BT_CEA_3840X2160P60_PA64_27,
+	V4L2_DV_BT_CEA_1280X720P48_PA16_9,
+	V4L2_DV_BT_CEA_1280X720P48_PA64_27,
+	V4L2_DV_BT_CEA_1680X720P48_PA64_27,
+	V4L2_DV_BT_CEA_1920X1080P48_PA16_9,
+	V4L2_DV_BT_CEA_1920X1080P48_PA64_27,
+	V4L2_DV_BT_CEA_3840X2160P48_PA16_9,
+	V4L2_DV_BT_CEA_4096X2160P48_PA256_135,
+	V4L2_DV_BT_CEA_3840X2160P48_PA64_27,
+	V4L2_DV_BT_CEA_3840X2160P100_PA16_9,
+	V4L2_DV_BT_CEA_3840X2160P120_PA16_9,
+	V4L2_DV_BT_CEA_3840X2160P100_PA64_27,
+	V4L2_DV_BT_CEA_3840X2160P120_PA64_27,
+	V4L2_DV_BT_CEA_5120X2160P24_PA64_27,
+	V4L2_DV_BT_CEA_5120X2160P25_PA64_27,
+	V4L2_DV_BT_CEA_5120X2160P30_PA64_27,
+	V4L2_DV_BT_CEA_5120X2160P48_PA64_27,
+	V4L2_DV_BT_CEA_5120X2160P50_PA64_27,
+	V4L2_DV_BT_CEA_5120X2160P60_PA64_27,
+	V4L2_DV_BT_CEA_5120X2160P100_PA64_27,
+	V4L2_DV_BT_CEA_5120X2160P120_PA64_27,
+	V4L2_DV_BT_CEA_7680X4320P24_PA16_9,
+	V4L2_DV_BT_CEA_7680X4320P25_PA16_9,
+	V4L2_DV_BT_CEA_7680X4320P30_PA16_9,
+	V4L2_DV_BT_CEA_7680X4320P48_PA16_9,
+	V4L2_DV_BT_CEA_7680X4320P50_PA16_9,
+	V4L2_DV_BT_CEA_7680X4320P60_PA16_9,
+	V4L2_DV_BT_CEA_7680X4320P100_PA16_9,
+	V4L2_DV_BT_CEA_7680X4320P120_PA16_9,
+	V4L2_DV_BT_CEA_7680X4320P24_PA64_27,
+	V4L2_DV_BT_CEA_7680X4320P25_PA64_27,
+	V4L2_DV_BT_CEA_7680X4320P30_PA64_27,
+	V4L2_DV_BT_CEA_7680X4320P48_PA64_27,
+	V4L2_DV_BT_CEA_7680X4320P50_PA64_27,
+	V4L2_DV_BT_CEA_7680X4320P60_PA64_27,
+	V4L2_DV_BT_CEA_7680X4320P100_PA64_27,
+	V4L2_DV_BT_CEA_7680X4320P120_PA64_27,
+	V4L2_DV_BT_CEA_10240X4320P24_PA64_27,
+	V4L2_DV_BT_CEA_10240X4320P25_PA64_27,
+	V4L2_DV_BT_CEA_10240X4320P30_PA64_27,
+	V4L2_DV_BT_CEA_10240X4320P48_PA64_27,
+	V4L2_DV_BT_CEA_10240X4320P50_PA64_27,
+	V4L2_DV_BT_CEA_10240X4320P60_PA64_27,
+	V4L2_DV_BT_CEA_10240X4320P100_PA64_27,
+	V4L2_DV_BT_CEA_10240X4320P120_PA64_27,
+	V4L2_DV_BT_CEA_4096X2160P100_PA256_135,
+	V4L2_DV_BT_CEA_4096X2160P120_PA256_135,
 	{ }
 };
 EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets);

include/uapi/linux/v4l2-dv-timings.h +1594 -1

1,607 lines not on this page · raw message

Signature · 1 line

2.7.4

kernel test robot

build bot

2021-05-22 15:41 UTC #7 lore raw

Re: [RFC v2 6/9] media: platform: Add Synopsys DesignWare HDMI RX Controller Driver

In reply to Nelson Costa

[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]

Hi Nelson,

[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on v5.12]
[also build test ERROR on next-20210521]
[cannot apply to linuxtv-media/master linux/master robh/for-next linus/master v5.13-rc2 v5.13-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210522-202538
base:    9f4ad9e425a1d3b6a34617b8ea226d56a119a717
config: nios2-randconfig-r005-20210522 (attached as .config)
compiler: nios2-linux-gcc (GCC) 9.3.0

reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/2e7f186187a4684f1eb4fa04bd253670e077e5fc
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Nelson-Costa/Add-Synopsys-DesignWare-HDMI-RX-Controller-and-PHY-drivers/20210522-202538 git checkout 2e7f186187a4684f1eb4fa04bd253670e077e5fc
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=nios2

If you fix the issue, kindly add following tag as appropriate

Reported-by kernel test robot <[email protected]>

All errors (new ones prefixed by >>):

nios2-linux-ld: drivers/media/platform/dwc/dw-hdmi-rx.o: in function `dw_hdmi_get_raw_infoframe_avi':

>> dw-hdmi-rx.c:(.text+0x162c): undefined reference to `hdmi_infoframe_unpack'

dw-hdmi-rx.c:(.text+0x162c): relocation truncated to fit: R_NIOS2_CALL26 against `hdmi_infoframe_unpack'
nios2-linux-ld: drivers/media/platform/dwc/dw-hdmi-rx.o: in function `dw_hdmi_get_raw_infoframe_aud':
dw-hdmi-rx.c:(.text+0x17b0): undefined reference to hdmi_infoframe_unpack' dw-hdmi-rx.c:(.text+0x17b0): relocation truncated to fit: R_NIOS2_CALL26 against hdmi_infoframe_unpack'
nios2-linux-ld: drivers/media/platform/dwc/dw-hdmi-rx.o: in function `dw_hdmi_get_raw_infoframe_vs':
dw-hdmi-rx.c:(.text+0x1950): undefined reference to hdmi_infoframe_unpack' dw-hdmi-rx.c:(.text+0x1950): relocation truncated to fit: R_NIOS2_CALL26 against hdmi_infoframe_unpack'

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0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org