Add Realtek Otto WDT support

Add a binding description for Realtek's watchdog timer as found on several of their MIPS-based SoCs (codenamed Otto), such as the RTL838x and RTL839x series of switch SoCs.

Signed-off-by Sander Vanheule <[email protected]>

---
 .../bindings/watchdog/realtek,otto-wdt.yaml   | 89 +++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml

Realtek MIPS SoCs (platform name Otto) have a watchdog timer with pretimeout notifitication support. The WDT can (partially) hard reset, or soft reset the SoC.

This driver implements all features as described in the devicetree binding, and also functions as a restart handler. The cpu reset mode is considered to be a "warm" restart, since this mode does not reset all peripherals. Being an embedded system though, the "cpu" and "software" modes will still cause the bootloader to run on restart.

Signed-off-by Sander Vanheule <[email protected]>

---
 MAINTAINERS                         |   7 +
 drivers/watchdog/Kconfig            |  13 +
 drivers/watchdog/Makefile           |   1 +
 drivers/watchdog/realtek_otto_wdt.c | 411 ++++++++++++++++++++++++++++
 4 files changed, 432 insertions(+)
 create mode 100644 drivers/watchdog/realtek_otto_wdt.c

MAINTAINERS +7 -0

index 62257ffca56a..e2a036c1a64b 100644
@@ -15858,6 +15858,13 @@ S:	Maintained
 F:	include/sound/rt*.h
 F:	sound/soc/codecs/rt*
 
+REALTEK OTTO WATCHDOG
+M:	Sander Vanheule <[email protected]>
+L:	[email protected]
+S:	Maintained
+F:	Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml
+F:	driver/watchdog/realtek_otto_wdt.c
+
 REALTEK RTL83xx SMI DSA ROUTER CHIPS
 M:	Linus Walleij <[email protected]>
 S:	Maintained

drivers/watchdog/Kconfig +13 -0

index bf59faeb3de1..799dbc14b347 100644
@@ -954,6 +954,19 @@ config RTD119X_WATCHDOG
 	  Say Y here to include support for the watchdog timer in
 	  Realtek RTD1295 SoCs.
 
+config REALTEK_OTTO_WDT
+	tristate "Realtek Otto MIPS watchdog support"
+	depends on MACH_REALTEK_RTL || COMPILE_TEST
+	select COMMON_CLK
+	select WATCHDOG_CORE
+	default MACH_REALTEK_RTL
+	help
+	  Say Y here to include support for the watchdog timer on
+	  Realtek RTL838x, RTL839x SoCs. On timeout this watchdog
+	  will restart the system.
+
+	  When built as a module this will be called realtek_otto_wdt.
+
 config SPRD_WATCHDOG
 	tristate "Spreadtrum watchdog support"
 	depends on ARCH_SPRD || COMPILE_TEST

drivers/watchdog/Makefile +1 -0

index 1bd2d6f37c53..a8dccf819163 100644
@@ -171,6 +171,7 @@ obj-$(CONFIG_IMGPDC_WDT) += imgpdc_wdt.o
 obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o
 obj-$(CONFIG_PIC32_WDT) += pic32-wdt.o
 obj-$(CONFIG_PIC32_DMT) += pic32-dmt.o
+obj-$(CONFIG_REALTEK_OTTO_WDT) += realtek_otto_wdt.o
 
 # PARISC Architecture
 

drivers/watchdog/realtek_otto_wdt.c new file +5 -0

new file mode 100644
index 000000000000..64c9cba6b0b1
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Realtek Otto MIPS platform watchdog
+ *

drivers/watchdog/realtek_otto_wdt.c new file +61 -0

+ */
+
+#include <linux/bits.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/math.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/reboot.h>
+#include <linux/watchdog.h>
+
+#define OTTO_WDT_REG_CNTR		0x0
+#define OTTO_WDT_CNTR_PING		BIT(31)
+
+#define OTTO_WDT_REG_INTR		0x4
+#define OTTO_WDT_INTR_PHASE_1		BIT(31)
+#define OTTO_WDT_INTR_PHASE_2		BIT(30)
+
+#define OTTO_WDT_REG_CTRL		0x8
+#define OTTO_WDT_CTRL_ENABLE		BIT(31)
+#define OTTO_WDT_CTRL_PRESCALE		GENMASK(30, 29)
+#define OTTO_WDT_CTRL_PHASE1		GENMASK(26, 22)
+#define OTTO_WDT_CTRL_PHASE2		GENMASK(19, 15)
+#define OTTO_WDT_CTRL_RST_MODE		GENMASK(1, 0)
+#define OTTO_WDT_MODE_SOC		0
+#define OTTO_WDT_MODE_CPU		1
+#define OTTO_WDT_MODE_SOFTWARE		2
+#define OTTO_WDT_CTRL_DEFAULT		OTTO_WDT_MODE_CPU
+
+#define OTTO_WDT_PRESCALE_MAX		3
+
+/*
+ * One higher than the max values contained in PHASE{1,2}, since a value of 0
+ * corresponds to one tick.
+ */
+#define OTTO_WDT_PHASE_TICKS_MAX	32
+
+/*
+ * The maximum reset delay is actually 2×32 ticks, but that would require large
+ * pretimout values for timeouts longer than 32 ticks. Limit the maximum timeout
+ * to 32 + 1 to ensure small pretimeout values can be configured as expected.
+ */
+#define OTTO_WDT_TIMEOUT_TICKS_MAX	(OTTO_WDT_PHASE_TICKS_MAX + 1)
+
+struct otto_wdt_ctrl {
+	struct watchdog_device wdev;
+	struct device *dev;
+	raw_spinlock_t lock;
+	void __iomem *base;
+	struct clk *clk;
+	int irq_phase1;
+	int irq_phase2;
+};
+
+static int otto_wdt_start(struct watchdog_device *wdev)

drivers/watchdog/realtek_otto_wdt.c new file +37 -0

+
+	return 0;
+}
+
+static int otto_wdt_stop(struct watchdog_device *wdev)
+{
+	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
+	unsigned long flags;
+	u32 v;
+
+	raw_spin_lock_irqsave(&ctrl->lock, flags);
+	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
+	v &= ~OTTO_WDT_CTRL_ENABLE;
+	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
+	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
+
+	return 0;
+}
+
+static int otto_wdt_ping(struct watchdog_device *wdev)
+{
+	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
+
+	iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR);
+
+	return 0;
+}
+
+static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)
+{
+	unsigned int rate_khz = clk_get_rate(ctrl->clk) / 1000;
+
+	if (!rate_khz)
+		return 0;
+
+	return DIV_ROUND_CLOSEST(1 << (25 + prescale), rate_khz);
+}

drivers/watchdog/realtek_otto_wdt.c new file +31 -0

+}
+
+static int otto_wdt_determine_timeouts(struct otto_wdt_ctrl *ctrl, unsigned int timeout,
+		unsigned int pretimeout)
+{
+	unsigned int pretimeout_ms = pretimeout * 1000;
+	unsigned int timeout_ms = timeout * 1000;
+	unsigned int prescale_next = 0;
+	unsigned int phase1_ticks;
+	unsigned int phase2_ticks;
+	unsigned int total_ticks;
+	unsigned int prescale;
+	unsigned int tick_ms;
+	u32 v;
+
+	do {
+		prescale = prescale_next;
+		if (prescale > OTTO_WDT_PRESCALE_MAX)
+			return -EINVAL;
+
+		tick_ms = otto_wdt_tick_ms(ctrl, prescale);
+		total_ticks = div_round_ticks(timeout_ms, tick_ms, 2);
+		phase2_ticks = div_round_ticks(pretimeout_ms, tick_ms, 1);
+		phase1_ticks = total_ticks - phase2_ticks;
+
+		prescale_next++;
+	} while (phase1_ticks > OTTO_WDT_PHASE_TICKS_MAX
+		|| phase2_ticks > OTTO_WDT_PHASE_TICKS_MAX);
+
+	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
+

drivers/watchdog/realtek_otto_wdt.c new file +4 -0

+	pretimeout_ms = phase2_ticks * tick_ms;
+	ctrl->wdev.pretimeout = DIV_ROUND_CLOSEST(pretimeout_ms, 1000);
+
+	return 0;

drivers/watchdog/realtek_otto_wdt.c new file +23 -0

+
+	raw_spin_lock_irqsave(&ctrl->lock, flags);
+	ret = otto_wdt_determine_timeouts(ctrl, val, min(wdev->pretimeout, val - 1));
+	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
+
+	return ret;
+}
+
+static int otto_wdt_set_pretimeout(struct watchdog_device *wdev, unsigned int val)
+{
+	struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
+	unsigned long flags;
+	unsigned int ret;
+
+	if (watchdog_pretimeout_invalid(wdev, val))
+		return -EINVAL;
+
+	raw_spin_lock_irqsave(&ctrl->lock, flags);
+	ret = otto_wdt_determine_timeouts(ctrl, wdev->timeout, val);
+	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
+
+	return ret;
+}

drivers/watchdog/realtek_otto_wdt.c new file +148 -0

+	switch (reboot_mode) {
+	case REBOOT_SOFT:
+		reset_mode = OTTO_WDT_MODE_SOFTWARE;
+		break;
+	case REBOOT_WARM:
+		reset_mode = OTTO_WDT_MODE_CPU;
+		break;
+	default:
+		reset_mode = OTTO_WDT_MODE_SOC;
+		break;
+	}
+
+	/* Configure for shortest timeout and wait for reset to occur */
+	v = FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, reset_mode) | OTTO_WDT_CTRL_ENABLE;
+	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
+
+	mdelay(3 * otto_wdt_tick_ms(ctrl, 0));
+
+	return 0;
+}
+
+static irqreturn_t otto_wdt_phase1_isr(int irq, void *dev_id)
+{
+	struct otto_wdt_ctrl *ctrl = dev_id;
+
+	iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR);
+	dev_crit(ctrl->dev, "phase 1 timeout\n");
+	watchdog_notify_pretimeout(&ctrl->wdev);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t otto_wdt_phase2_isr(int irq, void *dev_id)
+{
+	struct otto_wdt_ctrl *ctrl = dev_id;
+
+	iowrite32(OTTO_WDT_INTR_PHASE_2, ctrl->base + OTTO_WDT_REG_INTR);
+	dev_crit(ctrl->dev, "phase 2 timeout\n");
+	emergency_restart();
+
+	return IRQ_HANDLED;
+}
+
+static const struct watchdog_ops otto_wdt_ops = {
+	.owner = THIS_MODULE,
+	.start = otto_wdt_start,
+	.stop = otto_wdt_stop,
+	.ping = otto_wdt_ping,
+	.set_timeout = otto_wdt_set_timeout,
+	.set_pretimeout = otto_wdt_set_pretimeout,
+	.restart = otto_wdt_restart,
+};
+
+static const struct watchdog_info otto_wdt_info = {
+	.identity = "Realtek Otto watchdog timer",
+	.options = WDIOF_KEEPALIVEPING |
+		WDIOF_MAGICCLOSE |
+		WDIOF_SETTIMEOUT |
+		WDIOF_PRETIMEOUT,
+};
+
+static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)
+{
+	static const char *mode_property = "realtek,reset-mode";
+	const struct fwnode_handle *node = ctrl->dev->fwnode;
+	int mode_count;
+	u32 mode;
+	u32 v;
+
+	if (!node)
+		return -ENXIO;
+
+	mode_count = fwnode_property_string_array_count(node, mode_property);
+	if (mode_count < 0)
+		return mode_count;
+	else if (mode_count == 0)
+		return 0;
+	else if (mode_count != 1)
+		return -EINVAL;
+
+	if (fwnode_property_match_string(node, mode_property, "soc") == 0)
+		mode = OTTO_WDT_MODE_SOC;
+	else if (fwnode_property_match_string(node, mode_property, "cpu") == 0)
+		mode = OTTO_WDT_MODE_CPU;
+	else if (fwnode_property_match_string(node, mode_property, "software") == 0)
+		mode = OTTO_WDT_MODE_SOFTWARE;
+	else
+		return -EINVAL;
+
+	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);
+	v &= ~OTTO_WDT_CTRL_RST_MODE;
+	v |= FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, mode);
+	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);
+
+	return 0;
+}
+
+static int otto_wdt_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct otto_wdt_ctrl *ctrl;
+	unsigned int max_tick_ms;
+	int ret;
+
+	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
+	if (!ctrl)
+		return -ENOMEM;
+
+	ctrl->dev = dev;
+	ctrl->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(ctrl->base))
+		return PTR_ERR(ctrl->base);
+
+	raw_spin_lock_init(&ctrl->lock);
+
+	/* Clear any old interrupts and reset initial state */
+	iowrite32(OTTO_WDT_INTR_PHASE_1 | OTTO_WDT_INTR_PHASE_2,
+			ctrl->base + OTTO_WDT_REG_INTR);
+	iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);
+
+	ctrl->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(ctrl->clk))
+		return dev_err_probe(dev, PTR_ERR(ctrl->clk), "Failed to get clock\n");
+
+	ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
+	if (ctrl->irq_phase1 < 0)
+		return dev_err_probe(dev, ctrl->irq_phase1, "phase1 IRQ not found\n");
+
+	ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,
+			"realtek-otto-wdt", ctrl);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to get IRQ for phase1\n");
+
+	ctrl->irq_phase2 = platform_get_irq_byname(pdev, "phase2");
+	if (ctrl->irq_phase2 < 0)
+		return dev_err_probe(dev, ctrl->irq_phase2, "phase2 IRQ not found\n");
+
+	ret = devm_request_irq(dev, ctrl->irq_phase2, otto_wdt_phase2_isr, 0,
+			"realtek-otto-wdt", ctrl);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to get IRQ for phase2\n");
+
+	ret = otto_wdt_probe_reset_mode(ctrl);
+	if (ret)
+		return dev_err_probe(dev, ret, "Invalid reset mode specified\n");
+
+	ctrl->wdev.parent = dev;
+	ctrl->wdev.info = &otto_wdt_info;

drivers/watchdog/realtek_otto_wdt.c new file +32 -0

+	ctrl->wdev.timeout = min(30U, ctrl->wdev.max_timeout);
+
+	watchdog_set_drvdata(&ctrl->wdev, ctrl);
+	watchdog_init_timeout(&ctrl->wdev, 0, dev);
+	watchdog_stop_on_reboot(&ctrl->wdev);
+	watchdog_set_restart_priority(&ctrl->wdev, 128);
+
+	ret = otto_wdt_determine_timeouts(ctrl, ctrl->wdev.timeout, 1);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to set timeout\n");
+
+	return devm_watchdog_register_device(dev, &ctrl->wdev);
+}
+
+static const struct of_device_id otto_wdt_ids[] = {
+	{ .compatible = "realtek,rtl8380-wdt" },
+	{ .compatible = "realtek,rtl8390-wdt" },
+	{ }
+};
+
+static struct platform_driver otto_wdt_driver = {
+	.probe = otto_wdt_probe,
+	.driver = {
+		.name = "realtek-otto-watchdog",
+		.of_match_table	= otto_wdt_ids,
+	},
+};
+module_platform_driver(otto_wdt_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Sander Vanheule <[email protected]>");
+MODULE_DESCRIPTION("Realtek Otto watchdog timer driver");

Signature · 1 line

2.31.1

On Wed, Oct 13, 2021 at 03:29:00PM +0200, Sander Vanheule wrote:

Quoted 16 lines

drivers/watchdog/realtek_otto_wdt.c new file +9 -0

new file mode 100644
index 000000000000..64c9cba6b0b1
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Realtek Otto MIPS platform watchdog
+ *
+ * Watchdog timer that will reset the system after timeout, using the selected
+ * reset mode.
+ *
+ * Counter scaling and timeouts:

drivers/watchdog/realtek_otto_wdt.c line 15

Quoted 6 lines

drivers/watchdog/realtek_otto_wdt.c new file +6 -0

+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
+ *   Generates an interrupt, WDT cannot be stopped after phase 1
+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
+ *   Resets the system according to RST_MODE

Why is there a phase2 interrupt if phase2 resets the chip ?

Quoted 6 lines

+
+       raw_spin_lock_irqsave(&ctrl->lock, flags); +       v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); +       v |= OTTO_WDT_CTRL_ENABLE;
+       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); +       raw_spin_unlock_irqrestore(&ctrl->lock, flags);

Is it really necessary to disable interrupts for those operations ?

Quoted 10 lines

drivers/watchdog/realtek_otto_wdt.c new file +6 -0

+/*
+ * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds
+ * the value stored in those fields. This means the timer will run for at least
+ * one tick, so small values need to be clamped to correctly reflect the timeout.
+ */
+static inline unsigned int div_round_ticks(unsigned int val, unsigned int

tick_duration,
+               unsigned int min_ticks)
+{
+       return max(min_ticks, DIV_ROUND_CLOSEST(val, tick_duration));

Are you sure that DIV_ROUND_CLOSEST is appropriate in those calculations (instead of DIV_ROUND_UP or DIV_ROUND_DOWN) ?

drivers/watchdog/realtek_otto_wdt.c line 174

Quoted 4 lines

drivers/watchdog/realtek_otto_wdt.c new file +4 -0

+
+       timeout_ms = total_ticks * tick_ms;
+       ctrl->wdev.timeout = DIV_ROUND_CLOSEST(timeout_ms, 1000);
+

That means the actual timeout (and pretimeout) can be slightly larger than the real timeout. Is this really what you want ?

Quoted 10 lines

+       pretimeout_ms = phase2_ticks * tick_ms;
+       ctrl->wdev.pretimeout = DIV_ROUND_CLOSEST(pretimeout_ms, 1000);

drivers/watchdog/realtek_otto_wdt.c new file +7 -0

+
+       return 0;
+}
+
+static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val)
+{
+       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);

Quoted 5 lines

+       unsigned long flags;
+       unsigned int ret;
+
+       if (watchdog_timeout_invalid(wdev, val))
+               return -EINVAL;

This is not supposed to happen because the calling code already performs range checks.

drivers/watchdog/realtek_otto_wdt.c line 221

Quoted 9 lines

drivers/watchdog/realtek_otto_wdt.c new file +9 -0

+static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,
+               void *data)
+{
+       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
+       u32 reset_mode;
+       u32 v;
+
+       devm_free_irq(ctrl->dev, ctrl->irq_phase1, ctrl);
+

Why is this needed (instead of, say, disabling the interrupt) ?

Quoted 9 lines

+
+       /*
+        * Since pretimeout cannot be disabled, min_timeout is twice the +        * subsystem resolution. max_timeout is 44s at a bus clock of 200MHz. +        */
+       ctrl->wdev.min_timeout = 2;
+       max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX); +       ctrl->wdev.max_timeout =
+               DIV_ROUND_CLOSEST(max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX, 1000);

Any reason for using max_timeout instead of max_hw_heartbeat_ms ?

Quoted 1 line · Guenter Roeck

On Wed, Oct 13, 2021 at 03:29:00PM +0200, Sander Vanheule wrote:

[...]

Quoted 16 lines

Quoted 16 lines

drivers/watchdog/realtek_otto_wdt.c new file +9 -0

new file mode 100644
index 000000000000..64c9cba6b0b1
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Realtek Otto MIPS platform watchdog
+ *
+ * Watchdog timer that will reset the system after timeout, using the selected
+ * reset mode.
+ *
+ * Counter scaling and timeouts:

Quoted 9 lines

drivers/watchdog/realtek_otto_wdt.c line 15

Quoted 6 lines

drivers/watchdog/realtek_otto_wdt.c new file +6 -0

+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
+ *   Generates an interrupt, WDT cannot be stopped after phase 1
+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
+ *   Resets the system according to RST_MODE

Why is there a phase2 interrupt if phase2 resets the chip ?

The SoC's reset controller has an interrupt line for phase2, even though then it then the WDT also resets the system. I don't have any documentation about this peripheral; just some vendor code and there the phase2 interrupt isn't enabled. I mainly added it here for completeness.

One thing to note is that after CPU or software reset (not SoC reset) the phase2 flag in OTTO_WDT_REG_INTR will be set. That's why I always clear it in otto_wdt_probe(), because otherwise enabling the interrupt line would trigger otto_wdt_phase2_isr(). On warm restarts this bit could be used to determine if there was a WDT timeout, but not if the WDT is configured for cold restarts (i.e. full SoC reset).

Quoted 1 line

[...]

Quoted 7 lines

Quoted 6 lines

+
+       raw_spin_lock_irqsave(&ctrl->lock, flags); +       v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); +       v |= OTTO_WDT_CTRL_ENABLE;
+       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); +       raw_spin_unlock_irqrestore(&ctrl->lock, flags);

Quoted 1 line

Is it really necessary to disable interrupts for those operations ?

The ISR routines only use REG_INTR, which isn't modified anywhere else (outside of probing the device). I will replace these with raw_spin_{lock,unlock} throughout.

[...]

Quoted 14 lines

Quoted 10 lines

drivers/watchdog/realtek_otto_wdt.c new file +6 -0

+/*
+ * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds
+ * the value stored in those fields. This means the timer will run for at least
+ * one tick, so small values need to be clamped to correctly reflect the timeout.
+ */
+static inline unsigned int div_round_ticks(unsigned int val, unsigned int

tick_duration,
+               unsigned int min_ticks)
+{
+       return max(min_ticks, DIV_ROUND_CLOSEST(val, tick_duration));

Are you sure that DIV_ROUND_CLOSEST is appropriate in those calculations (instead of DIV_ROUND_UP or DIV_ROUND_DOWN) ?

[...]

Quoted 7 lines

drivers/watchdog/realtek_otto_wdt.c line 174

Quoted 4 lines

drivers/watchdog/realtek_otto_wdt.c new file +4 -0

+
+       timeout_ms = total_ticks * tick_ms;
+       ctrl->wdev.timeout = DIV_ROUND_CLOSEST(timeout_ms, 1000);
+

That means the actual timeout (and pretimeout) can be slightly larger than the real timeout. Is this really what you want ?

Is it a problem if the WDT times out later than specified by watchdog_device.(pre)timeout? I can see that premature timeouts would be an issue, but I don't suppose it's problematic if the WDT is pinged (slightly) sooner than actually required?

The coarsest ticks are 1342 ms, so it is not always possible to provide the requested (pre)timeout value, independent of the rounding scheme. Although I think it should be possible to replace timeout rounding by DIV_ROUND_UP (of total_ticks_ms), and pretimeout rounding by DIV_ROUND_DOWN (of phase2_ticks_ms), and keep stable timeouts when alternating between set_timeout/set_pretimeout.

Quoted 10 lines

Quoted 10 lines

+       pretimeout_ms = phase2_ticks * tick_ms;
+       ctrl->wdev.pretimeout = DIV_ROUND_CLOSEST(pretimeout_ms, 1000);

drivers/watchdog/realtek_otto_wdt.c new file +7 -0

+
+       return 0;
+}
+
+static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val)
+{
+       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);

Quoted 8 lines

Quoted 5 lines

+       unsigned long flags;
+       unsigned int ret;
+
+       if (watchdog_timeout_invalid(wdev, val))
+               return -EINVAL;

This is not supposed to happen because the calling code already performs range checks.

Right, I will drop the redundant check here and in set_pretimeout.

Quoted 1 line

[...]

Quoted 11 lines

drivers/watchdog/realtek_otto_wdt.c line 221

Quoted 9 lines

drivers/watchdog/realtek_otto_wdt.c new file +9 -0

+static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,
+               void *data)
+{
+       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);
+       u32 reset_mode;
+       u32 v;
+
+       devm_free_irq(ctrl->dev, ctrl->irq_phase1, ctrl);
+

Why is this needed (instead of, say, disabling the interrupt) ?

Disabling the interrupt should actually be enough. I'll replace the devm_free_irq() with disable_irq(). Somehow I didn't find disable_irq(), even though that was what I was looking for...

[...]

Quoted 11 lines

Quoted 9 lines

+
+       /*
+        * Since pretimeout cannot be disabled, min_timeout is twice the +        * subsystem resolution. max_timeout is 44s at a bus clock of 200MHz. +        */
+       ctrl->wdev.min_timeout = 2;
+       max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX); +       ctrl->wdev.max_timeout =
+               DIV_ROUND_CLOSEST(max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX, 1000);

Any reason for using max_timeout instead of max_hw_heartbeat_ms ?

I must have missed this when I was looking at watchdog_device. Makes sense to use max_hw_heartbeat_ms since that reflects the actual value more accurately.

Quoted 1 line

Thanks for the feedback!

Best,
Sander

Quoted 34 lines · Sander Vanheule

Quoted 1 line · Guenter Roeck

On Wed, Oct 13, 2021 at 03:29:00PM +0200, Sander Vanheule wrote:

[...]

Quoted 20 lines

Quoted 20 lines

drivers/watchdog/realtek_otto_wdt.c new file +6 -0

new file mode 100644
index 000000000000..64c9cba6b0b1
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Realtek Otto MIPS platform watchdog
+ *
+ * Watchdog timer that will reset the system after timeout, using the

selected
+ * reset mode.
+ *
+ * Counter scaling and timeouts:
+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz

Quoted 9 lines

Quoted 6 lines

+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
+ *   Generates an interrupt, WDT cannot be stopped after phase 1
+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
+ *   Resets the system according to RST_MODE

Why is there a phase2 interrupt if phase2 resets the chip ?

Quoted 8 lines

The SoC's reset controller has an interrupt line for phase2, even though then it then the
WDT also resets the system. I don't have any documentation about this peripheral; just
some vendor code and there the phase2 interrupt isn't enabled. I mainly added it here for
completeness.

It seems pointless to mandate an interrupt just for completeness.

Quoted 20 lines

One thing to note is that after CPU or software reset (not SoC reset) the phase2 flag in
OTTO_WDT_REG_INTR will be set. That's why I always clear it in otto_wdt_probe(), because
otherwise enabling the interrupt line would trigger otto_wdt_phase2_isr(). On warm
restarts this bit could be used to determine if there was a WDT timeout, but not if the
WDT is configured for cold restarts (i.e. full SoC reset).

Quoted 1 line

[...]

Quoted 7 lines

Quoted 6 lines

+
+       raw_spin_lock_irqsave(&ctrl->lock, flags); +       v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); +       v |= OTTO_WDT_CTRL_ENABLE;
+       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); +       raw_spin_unlock_irqrestore(&ctrl->lock, flags);

Quoted 6 lines

Quoted 1 line

Is it really necessary to disable interrupts for those operations ?

The ISR routines only use REG_INTR, which isn't modified anywhere else (outside of probing
the device). I will replace these with raw_spin_{lock,unlock} throughout.

In that case you should not need any locks at all since the watchdog core ensures
that the device is opened only once (and thus only one entity can enable or disable
the watchdog).

Quoted 30 lines

[...]

Quoted 18 lines

Quoted 6 lines

+/*
+ * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds
+ * the value stored in those fields. This means the timer will run for at least
+ * one tick, so small values need to be clamped to correctly reflect

Quoted 8 lines

the timeout.
+ */
+static inline unsigned int div_round_ticks(unsigned int val, unsigned int
tick_duration,
+               unsigned int min_ticks)
+{
+       return max(min_ticks, DIV_ROUND_CLOSEST(val, tick_duration));

Are you sure that DIV_ROUND_CLOSEST is appropriate in those calculations (instead of DIV_ROUND_UP or DIV_ROUND_DOWN) ?

[...]

Quoted 7 lines

drivers/watchdog/realtek_otto_wdt.c line 174

Quoted 4 lines

drivers/watchdog/realtek_otto_wdt.c new file +4 -0

+
+       timeout_ms = total_ticks * tick_ms;
+       ctrl->wdev.timeout = DIV_ROUND_CLOSEST(timeout_ms, 1000);
+

That means the actual timeout (and pretimeout) can be slightly larger than the real timeout. Is this really what you want ?

Quoted 6 lines

Is it a problem if the WDT times out later than specified by watchdog_device.(pre)timeout?
I can see that premature timeouts would be an issue, but I don't suppose it's problematic
if the WDT is pinged (slightly) sooner than actually required?

I am not concerned with early pings. However, if the timeout limit is set to a value
lardger than the real timeout (eg the real timeout is 25.6 seconds and the timeout
value is set to 26 seconds), the reset may occur a bit early. Granted, it doesn't
matter much, but most driver authors would ensure that the timeout is set to 25 seconds
(ie rounded down) in that situation.

Quoted 80 lines

The coarsest ticks are 1342 ms, so it is not always possible to provide the requested
(pre)timeout value, independent of the rounding scheme. Although I think it should be
possible to replace timeout rounding by DIV_ROUND_UP (of total_ticks_ms), and pretimeout
rounding by DIV_ROUND_DOWN (of phase2_ticks_ms), and keep stable timeouts when alternating
between set_timeout/set_pretimeout.

Quoted 11 lines

Quoted 11 lines

+       pretimeout_ms = phase2_ticks * tick_ms;
+       ctrl->wdev.pretimeout = DIV_ROUND_CLOSEST(pretimeout_ms, 1000);

drivers/watchdog/realtek_otto_wdt.c new file +5 -0

+
+       return 0;
+}
+
+static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned

int val)
+{
+       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);

Quoted 8 lines

Quoted 5 lines

+       unsigned long flags;
+       unsigned int ret;
+
+       if (watchdog_timeout_invalid(wdev, val))
+               return -EINVAL;

This is not supposed to happen because the calling code already performs range checks.

Right, I will drop the redundant check here and in set_pretimeout.

Quoted 1 line

[...]

Quoted 4 lines

Quoted 4 lines

+static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,
+               void *data)
+{

Quoted 8 lines

drivers/watchdog/realtek_otto_wdt.c line 221

Quoted 6 lines

+       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); +       u32 reset_mode;
+       u32 v;

drivers/watchdog/realtek_otto_wdt.c new file +3 -0

+
+       devm_free_irq(ctrl->dev, ctrl->irq_phase1, ctrl);
+

Why is this needed (instead of, say, disabling the interrupt) ?

Disabling the interrupt should actually be enough. I'll replace the devm_free_irq() with
disable_irq(). Somehow I didn't find disable_irq(), even though that was what I was
looking for...

[...]

Quoted 12 lines

Quoted 11 lines

+
+       /*
+        * Since pretimeout cannot be disabled, min_timeout is twice the +        * subsystem resolution. max_timeout is 44s at a bus clock of 200MHz.
+        */
+       ctrl->wdev.min_timeout = 2;
+       max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX); +       ctrl->wdev.max_timeout =
+               DIV_ROUND_CLOSEST(max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX, 1000);

Quoted 1 line

Any reason for using max_timeout instead of max_hw_heartbeat_ms ?

I must have missed this when I was looking at watchdog_device. Makes sense to use
max_hw_heartbeat_ms since that reflects the actual value more accurately.

Quoted 1 line

Thanks for the feedback!

Best,
Sander

Quoted 44 lines · Guenter Roeck

Quoted 42 lines · Sander Vanheule

Quoted 1 line · Guenter Roeck

On Wed, Oct 13, 2021 at 03:29:00PM +0200, Sander Vanheule wrote:

[...]

Quoted 20 lines

Quoted 20 lines

drivers/watchdog/realtek_otto_wdt.c new file +6 -0

new file mode 100644
index 000000000000..64c9cba6b0b1
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Realtek Otto MIPS platform watchdog
+ *
+ * Watchdog timer that will reset the system after timeout, using the

selected
+ * reset mode.
+ *
+ * Counter scaling and timeouts:
+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz

Quoted 9 lines

Quoted 6 lines

+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
+ *   Generates an interrupt, WDT cannot be stopped after phase 1
+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
+ *   Resets the system according to RST_MODE

Why is there a phase2 interrupt if phase2 resets the chip ?

The SoC's reset controller has an interrupt line for phase2, even though then it then the
WDT also resets the system. I don't have any documentation about this peripheral; just
some vendor code and there the phase2 interrupt isn't enabled. I mainly added it here for
completeness.

Quoted 1 line

It seems pointless to mandate an interrupt just for completeness.

Okay, then I will just drop it here. As I understand, the bindings should be as complete as possible, so I think the phase2 interrupt definition should remain there?

Quoted 27 lines

Quoted 20 lines

One thing to note is that after CPU or software reset (not SoC reset) the phase2 flag in
OTTO_WDT_REG_INTR will be set. That's why I always clear it in otto_wdt_probe(), because
otherwise enabling the interrupt line would trigger otto_wdt_phase2_isr(). On warm
restarts this bit could be used to determine if there was a WDT timeout, but not if the
WDT is configured for cold restarts (i.e. full SoC reset).

Quoted 1 line

[...]

Quoted 7 lines

Quoted 6 lines

+
+       raw_spin_lock_irqsave(&ctrl->lock, flags); +       v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); +       v |= OTTO_WDT_CTRL_ENABLE;
+       iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); +       raw_spin_unlock_irqrestore(&ctrl->lock, flags);

Quoted 6 lines

Quoted 1 line

Is it really necessary to disable interrupts for those operations ?

The ISR routines only use REG_INTR, which isn't modified anywhere else (outside of probing
the device). I will replace these with raw_spin_{lock,unlock} throughout.

Quoted 5 lines

In that case you should not need any locks at all since the watchdog core ensures
that the device is opened only once (and thus only one entity can enable or disable
the watchdog).

If there is an external guarantee that at most one of {set_timeout, set_pretimeout, enable, disable} will be called at a time, I can indeed drop the lock. I had added the lock initially because of the read-modify-write operations on the control register these ops perform.

Quoted 37 lines

Quoted 30 lines

[...]

Quoted 18 lines

Quoted 6 lines

+/*
+ * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds
+ * the value stored in those fields. This means the timer will run for at least
+ * one tick, so small values need to be clamped to correctly reflect

Quoted 8 lines

the timeout.
+ */
+static inline unsigned int div_round_ticks(unsigned int val, unsigned int
tick_duration,
+               unsigned int min_ticks)
+{
+       return max(min_ticks, DIV_ROUND_CLOSEST(val, tick_duration));

Are you sure that DIV_ROUND_CLOSEST is appropriate in those calculations (instead of DIV_ROUND_UP or DIV_ROUND_DOWN) ?

[...]

Quoted 7 lines

drivers/watchdog/realtek_otto_wdt.c line 174

Quoted 4 lines

drivers/watchdog/realtek_otto_wdt.c new file +4 -0

+
+       timeout_ms = total_ticks * tick_ms;
+       ctrl->wdev.timeout = DIV_ROUND_CLOSEST(timeout_ms, 1000);
+

That means the actual timeout (and pretimeout) can be slightly larger than the real timeout. Is this really what you want ?

Quoted 6 lines

Is it a problem if the WDT times out later than specified by watchdog_device.(pre)timeout?
I can see that premature timeouts would be an issue, but I don't suppose it's problematic
if the WDT is pinged (slightly) sooner than actually required?

Quoted 9 lines

I am not concerned with early pings. However, if the timeout limit is set to a value
lardger than the real timeout (eg the real timeout is 25.6 seconds and the timeout
value is set to 26 seconds), the reset may occur a bit early. Granted, it doesn't
matter much, but most driver authors would ensure that the timeout is set to 25 seconds
(ie rounded down) in that situation.

I'll replace tick rounding with DIV_ROUND_UP, and timeout rounding with regular flooring division. This results in a few timeout values being rounded up for the coarsest tick duration, but those are then stable values.

Best,
Sander

Quoted 81 lines

Quoted 80 lines

The coarsest ticks are 1342 ms, so it is not always possible to provide the requested
(pre)timeout value, independent of the rounding scheme. Although I think it should be
possible to replace timeout rounding by DIV_ROUND_UP (of total_ticks_ms), and pretimeout
rounding by DIV_ROUND_DOWN (of phase2_ticks_ms), and keep stable timeouts when alternating
between set_timeout/set_pretimeout.

Quoted 11 lines

Quoted 11 lines

+       pretimeout_ms = phase2_ticks * tick_ms;
+       ctrl->wdev.pretimeout = DIV_ROUND_CLOSEST(pretimeout_ms, 1000);

drivers/watchdog/realtek_otto_wdt.c new file +5 -0

+
+       return 0;
+}
+
+static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned

int val)
+{
+       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);

Quoted 8 lines

Quoted 5 lines

+       unsigned long flags;
+       unsigned int ret;
+
+       if (watchdog_timeout_invalid(wdev, val))
+               return -EINVAL;

This is not supposed to happen because the calling code already performs range checks.

Right, I will drop the redundant check here and in set_pretimeout.

Quoted 1 line

[...]

Quoted 4 lines

Quoted 4 lines

+static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,
+               void *data)
+{

Quoted 8 lines

drivers/watchdog/realtek_otto_wdt.c line 221

Quoted 6 lines

+       struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); +       u32 reset_mode;
+       u32 v;

drivers/watchdog/realtek_otto_wdt.c new file +3 -0

+
+       devm_free_irq(ctrl->dev, ctrl->irq_phase1, ctrl);
+

Why is this needed (instead of, say, disabling the interrupt) ?

Disabling the interrupt should actually be enough. I'll replace the devm_free_irq() with
disable_irq(). Somehow I didn't find disable_irq(), even though that was what I was
looking for...

[...]

Quoted 12 lines

Quoted 11 lines

+
+       /*
+        * Since pretimeout cannot be disabled, min_timeout is twice the +        * subsystem resolution. max_timeout is 44s at a bus clock of 200MHz.
+        */
+       ctrl->wdev.min_timeout = 2;
+       max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX); +       ctrl->wdev.max_timeout =
+               DIV_ROUND_CLOSEST(max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX, 1000);

Quoted 1 line

Any reason for using max_timeout instead of max_hw_heartbeat_ms ?

I must have missed this when I was looking at watchdog_device. Makes sense to use
max_hw_heartbeat_ms since that reflects the actual value more accurately.

Quoted 1 line

Thanks for the feedback!

Best,
Sander

Quoted 45 lines · Sander Vanheule

Quoted 44 lines · Guenter Roeck

Quoted 42 lines · Sander Vanheule

Quoted 1 line · Guenter Roeck

On Wed, Oct 13, 2021 at 03:29:00PM +0200, Sander Vanheule wrote:

[...]

Quoted 20 lines

Quoted 20 lines

drivers/watchdog/realtek_otto_wdt.c new file +6 -0

new file mode 100644
index 000000000000..64c9cba6b0b1
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Realtek Otto MIPS platform watchdog
+ *
+ * Watchdog timer that will reset the system after timeout, using the

selected
+ * reset mode.
+ *
+ * Counter scaling and timeouts:
+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz

Quoted 9 lines

Quoted 6 lines

+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
+ *   Generates an interrupt, WDT cannot be stopped after phase 1
+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
+ *   Resets the system according to RST_MODE

Why is there a phase2 interrupt if phase2 resets the chip ?

The SoC's reset controller has an interrupt line for phase2, even though then it then the
WDT also resets the system. I don't have any documentation about this peripheral; just
some vendor code and there the phase2 interrupt isn't enabled. I mainly added it here for
completeness.

Quoted 6 lines

Quoted 1 line

It seems pointless to mandate an interrupt just for completeness.

Okay, then I will just drop it here. As I understand, the bindings should be as complete as possible, so I think the phase2 interrupt definition should remain there?

I still don't see the point of it if there is no known use case. At the very least it will need to be optional, but even then I would expect a description of the use case.

FWIW, technically I suspect that there is a means for the watchdog to generate a second interrupt instead of resetting the hardware (otherwise the second interrupt would not really make sense), but without hardware and without datasheet it is impossible to confirm that.

Quoted 45 lines · Sander Vanheule

Quoted 44 lines · Guenter Roeck

Quoted 42 lines · Sander Vanheule

Quoted 1 line · Guenter Roeck

On Wed, Oct 13, 2021 at 03:29:00PM +0200, Sander Vanheule wrote:

[...]

Quoted 20 lines

Quoted 20 lines

drivers/watchdog/realtek_otto_wdt.c new file +6 -0

new file mode 100644
index 000000000000..64c9cba6b0b1
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Realtek Otto MIPS platform watchdog
+ *
+ * Watchdog timer that will reset the system after timeout, using the

selected
+ * reset mode.
+ *
+ * Counter scaling and timeouts:
+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz

Quoted 9 lines

Quoted 6 lines

+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
+ *   Generates an interrupt, WDT cannot be stopped after phase 1
+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
+ *   Resets the system according to RST_MODE

Why is there a phase2 interrupt if phase2 resets the chip ?

The SoC's reset controller has an interrupt line for phase2, even though then it then the
WDT also resets the system. I don't have any documentation about this peripheral; just
some vendor code and there the phase2 interrupt isn't enabled. I mainly added it here for
completeness.

Quoted 6 lines

Quoted 1 line

It seems pointless to mandate an interrupt just for completeness.

Okay, then I will just drop it here. As I understand, the bindings should be as complete as possible, so I think the phase2 interrupt definition should remain there?

I still don't see the point of it if there is no known use case. At the very least it will need to be optional, but even then I would expect a description of the use case.

FWIW, technically I suspect that there is a means for the watchdog to generate a second interrupt instead of resetting the hardware (otherwise the second interrupt would not really make sense), but without hardware and without datasheet it is impossible to confirm that.

Hi Sander,

I love your patch! Yet something to improve:

[auto build test ERROR on linus/master]
[also build test ERROR on v5.15-rc5 next-20211013]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Sander-Vanheule/Add-Realtek-Otto-WDT-support/20211013-213511
base:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git f4d0cc426f77df68
90aa868f96c2de89686aae8a
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
        chmod +x ~/bin/make.cross
        #
https://github.com/0day-ci/linux/commit/32b957f54703ffbffecc825fb8df3106b2aab6b5
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Sander-Vanheule/Add-Realtek-Otto-WDT- support/20211013-213511
        git checkout 32b957f54703ffbffecc825fb8df3106b2aab6b5

        # save the attached .config to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir
ARCH=sh SHELL=/bin/bash drivers/

If you fix the issue, kindly add following tag as appropriate

Reported-by kernel test robot <[email protected]>

All errors (new ones prefixed by >>):

Quoted 1 line

Quoted 1 line

drivers/clk/clk.c:855:6: error: redefinition of 'clk_unprepare'

     855 | void clk_unprepare(struct clk *clk)
         |      ^~~~~~~~~~~~~
   In file included from drivers/clk/clk.c:9:
   include/linux/clk.h:303:20: note: previous definition of 'clk_unprepare' with type 'void(struct clk *)'
     303 | static inline void clk_unprepare(struct clk *clk)
         |                    ^~~~~~~~~~~~~

Quoted 1 line

Quoted 1 line

drivers/clk/clk.c:936:5: error: redefinition of 'clk_prepare'

     936 | int clk_prepare(struct clk *clk)
         |     ^~~~~~~~~~~
   In file included from drivers/clk/clk.c:9:
   include/linux/clk.h:271:19: note: previous definition of 'clk_prepare' with type 'int(struct clk *)'
     271 | static inline int clk_prepare(struct clk *clk)
         |                   ^~~~~~~~~~~

Quoted 1 line

Quoted 1 line

drivers/clk/clk.c:1182:6: error: redefinition of 'clk_is_enabled_when_prepared'

    1182 | bool clk_is_enabled_when_prepared(struct clk *clk)
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
   In file included from drivers/clk/clk.c:9:
   include/linux/clk.h:284:20: note: previous definition of 'clk_is_enabled_when_prepared' with type 'bool(struct clk *)' {aka '_Bool(struct clk *)'}
     284 | static inline bool clk_is_enabled_when_prepared(struct clk *clk) |                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for COMMON_CLK Depends on !HAVE_LEGACY_CLK
   Selected by
   - REALTEK_OTTO_WDT && WATCHDOG && (MACH_REALTEK_RTL || COMPILE_TEST