Unify controller structure name
Subsystems (9)
cover Unify controller structure name
Controllrt structure name of some PCI drivers does not match the convention struct of other PCI driver, namely <driver>_pcie, e.g. xgene_pcie_port, intel_pcie_port, xilinx_pcie_port, uniphier_pcie_priv, tegra_pcie_dw, mk_pcie_dw. Unify them to the convetion. Some instantiation name of the struct name, e.g. port, priv, are also unified to 'pcie'.
Fan Fei (6):
PCI: xgene: Rename struct xgene_pcie_port to xgene_pcie
PCI: intel-gw: Rename struct intel_pcie_port to intel_pcie
PCI: uniphier: Rename struct uniphier_pcie_priv to uniphier_pcie
PCI: tegra194: Rename struct tegra_pcie_dw to tegra194_pcie
PCI: xilinx: Rename struct xilinx_pcie_port to xilinx_pcie
PCI: mediatek-gen3: Rename struct mtk_pcie_port to mtk_gen_pcie
drivers/pci/controller/dwc/pcie-intel-gw.c | 204 +++++------ drivers/pci/controller/dwc/pcie-tegra194.c | 120 +++---- drivers/pci/controller/dwc/pcie-uniphier.c | 159 +++++---- drivers/pci/controller/pci-xgene.c | 46 +-- drivers/pci/controller/pcie-mediatek-gen3.c | 370 ++++++++++---------- drivers/pci/controller/pcie-xilinx.c | 154 ++++---- 6 files changed, 534 insertions(+), 519 deletions(-)
Signature · 1 line
2.25.1
PATCH 1/6 PCI: xgene: Rename struct xgene_pcie_port to xgene_pcie
Rename struct xgene_pcie_port to xgene_pcie to match the convention of <driver>_pcie. No functional change intended.
Signed-off-by Fan Fei <[email protected]>
--- drivers/pci/controller/pci-xgene.c | 46 +++++++++++++++--------------- 1 file changed, 23 insertions(+), 23 deletions(-)
drivers/pci/controller/pci-xgene.c +23 -23
@@ -60,7 +60,7 @@#define XGENE_PCIE_IP_VER_2 2 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) -struct xgene_pcie_port { +struct xgene_pcie { struct device_node *node; struct device *dev; struct clk *clk;
@@ -71,12 +71,12 @@ struct xgene_pcie_port {u32 version; }; -static u32 xgene_pcie_readl (struct xgene_pcie_port *port,u32 reg) +static u32 xgene_pcie_readl (struct xgene_pcie *port,u32 reg) {return readl (port->csr_base + reg); } -static void xgene_pcie_writel (struct xgene_pcie_port *port,u32 reg,u32 val) +static void xgene_pcie_writel (struct xgene_pcie *port,u32 reg,u32 val) {writel (val, port->csr_base + reg); }
@@ -86,15 +86,15 @@ static inline u32 pcie_bar_low_val(u32 addr, u32 flags)return (addr &PCI_BASE_ADDRESS_MEM_MASK ) | flags; } -static inline struct xgene_pcie_port *pcie_bus_to_port (struct pci_bus *bus) +static inline struct xgene_pcie *pcie_bus_to_port (struct pci_bus *bus) {struct pci_config_window *cfg;if (acpi_disabled) -return (struct xgene_pcie_port *)(bus->sysdata); +return (struct xgene_pcie *)(bus->sysdata); cfg = bus->sysdata; -return (struct xgene_pcie_port *)(cfg->priv); +return (struct xgene_pcie *)(cfg->priv); }/*
@@ -103,7 +103,7 @@ static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)*/ static void __iomem *xgene_pcie_get_cfg_base (struct pci_bus *bus) { -struct xgene_pcie_port *port =pcie_bus_to_port (bus); +struct xgene_pcie *port =pcie_bus_to_port (bus);if (bus->number >= (bus->primary +1 ))return port->cfg_base +AXI_EP_CFG_ACCESS ;
@@ -117,7 +117,7 @@ static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)*/ static void xgene_pcie_set_rtdid_reg (struct pci_bus *bus,uint devfn) { -struct xgene_pcie_port *port =pcie_bus_to_port (bus); +struct xgene_pcie *port =pcie_bus_to_port (bus);unsigned int b, d, f;u32 rtdid_val =0 ;
@@ -164,7 +164,7 @@ static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,static int xgene_pcie_config_read32 (struct pci_bus *bus,unsigned int devfn,int where,int size,u32 *val) { -struct xgene_pcie_port *port =pcie_bus_to_port (bus); +struct xgene_pcie *port =pcie_bus_to_port (bus);if (pci_generic_config_read32 (bus, devfn, where & ~0x3 ,4 , val) !=PCIBIOS_SUCCESSFUL )
@@ -227,7 +227,7 @@ static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion) {struct device *dev = cfg->parent;struct acpi_device *adev =to_acpi_device (dev); -struct xgene_pcie_port *port; +struct xgene_pcie *port;struct resource csr;int ret;
@@ -281,7 +281,7 @@ const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {#endif #if defined(CONFIG_PCI_XGENE ) -static u64 xgene_pcie_set_ib_mask (struct xgene_pcie_port *port,u32 addr, +static u64 xgene_pcie_set_ib_mask (struct xgene_pcie *port,u32 addr,u32 flags,u64 size) {u64 mask = (~(size -1 ) &PCI_BASE_ADDRESS_MEM_MASK ) | flags;
@@ -307,7 +307,7 @@ static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,return mask; } -static void xgene_pcie_linkup (struct xgene_pcie_port *port, +static void xgene_pcie_linkup (struct xgene_pcie *port,u32 *lanes,u32 *speed) {u32 val32;
@@ -322,7 +322,7 @@ static void xgene_pcie_linkup(struct xgene_pcie_port *port, } } -static int xgene_pcie_init_port (struct xgene_pcie_port *port) +static int xgene_pcie_init_port (struct xgene_pcie *port) {struct device *dev = port->dev;int rc;
@@ -342,7 +342,7 @@ static int xgene_pcie_init_port(struct xgene_pcie_port *port)return 0 ; } -static int xgene_pcie_map_reg (struct xgene_pcie_port *port, +static int xgene_pcie_map_reg (struct xgene_pcie *port,struct platform_device *pdev) {struct device *dev = port->dev;
@@ -362,7 +362,7 @@ static int xgene_pcie_map_reg(struct xgene_pcie_port *port,return 0 ; } -static void xgene_pcie_setup_ob_reg (struct xgene_pcie_port *port, +static void xgene_pcie_setup_ob_reg (struct xgene_pcie *port,struct resource *res,u32 offset,u64 cpu_addr,u64 pci_addr) {
@@ -394,7 +394,7 @@ static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,xgene_pcie_writel (port, offset +0x14 ,upper_32_bits (pci_addr)); } -static void xgene_pcie_setup_cfg_reg (struct xgene_pcie_port *port) +static void xgene_pcie_setup_cfg_reg (struct xgene_pcie *port) {u64 addr = port->cfg_addr;
@@ -403,7 +403,7 @@ static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)xgene_pcie_writel (port,CFGCTL ,EN_REG ); } -static int xgene_pcie_map_ranges (struct xgene_pcie_port *port) +static int xgene_pcie_map_ranges (struct xgene_pcie *port) {struct pci_host_bridge *bridge =pci_host_bridge_from_priv (port);struct resource_entry *window;
@@ -444,7 +444,7 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)return 0 ; } -static void xgene_pcie_setup_pims (struct xgene_pcie_port *port,u32 pim_reg, +static void xgene_pcie_setup_pims (struct xgene_pcie *port,u32 pim_reg,u64 pim,u64 size) {xgene_pcie_writel (port, pim_reg,lower_32_bits (pim));
@@ -478,7 +478,7 @@ static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)return -EINVAL ; } -static void xgene_pcie_setup_ib_reg (struct xgene_pcie_port *port, +static void xgene_pcie_setup_ib_reg (struct xgene_pcie *port,struct resource_entry *entry,u8 *ib_reg_mask) {
@@ -529,7 +529,7 @@ static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,xgene_pcie_setup_pims (port, pim_reg, pci_addr, ~(size -1 )); } -static int xgene_pcie_parse_map_dma_ranges (struct xgene_pcie_port *port) +static int xgene_pcie_parse_map_dma_ranges (struct xgene_pcie *port) {struct pci_host_bridge *bridge =pci_host_bridge_from_priv (port);struct resource_entry *entry;
@@ -542,7 +542,7 @@ static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port) }/* clear BAR configuration which was done by firmware */ -static void xgene_pcie_clear_config (struct xgene_pcie_port *port) +static void xgene_pcie_clear_config (struct xgene_pcie *port) {int i;
@@ -550,7 +550,7 @@ static void xgene_pcie_clear_config(struct xgene_pcie_port *port)xgene_pcie_writel (port, i,0 ); } -static int xgene_pcie_setup (struct xgene_pcie_port *port) +static int xgene_pcie_setup (struct xgene_pcie *port) {struct device *dev = port->dev;u32 val, lanes =0 , speed =0 ;
@@ -588,7 +588,7 @@ static int xgene_pcie_probe(struct platform_device *pdev) {struct device *dev = &pdev->dev;struct device_node *dn = dev->of_node; -struct xgene_pcie_port *port; +struct xgene_pcie *port;struct pci_host_bridge *bridge;int ret;
Signature · 1 line
2.25.1
PATCH 2/6 PCI: intel-gw: Rename struct intel_pcie_port to intel_pcie
In reply to Fan FeiRename struct intel_pcie_port to intel_pcie to match the convention of <driver>_pcie. No functional change intended.
Signed-off-by Fan Fei <[email protected]>
--- drivers/pci/controller/dwc/pcie-intel-gw.c | 204 ++++++++++----------- 1 file changed, 102 insertions(+), 102 deletions(-)
drivers/pci/controller/dwc/pcie-intel-gw.c +102 -102
@@ -62,7 +62,7 @@ struct intel_pcie_soc {unsigned int pcie_ver; }; -struct intel_pcie_port { +struct intel_pcie {struct dw_pcie pci;void __iomem *app_base;struct gpio_desc *reset_gpio;
@@ -83,53 +83,53 @@ static void pcie_update_bits(void __iomem *base, u32 ofs, u32 mask, u32 val)writel (val, base + ofs); } -static inline void pcie_app_wr (struct intel_pcie_port *lpp,u32 ofs,u32 val) +static inline void pcie_app_wr (struct intel_pcie *pcie,u32 ofs,u32 val) { -writel (val, lpp->app_base + ofs); +writel (val, pcie->app_base + ofs); } -static void pcie_app_wr_mask (struct intel_pcie_port *lpp,u32 ofs, +static void pcie_app_wr_mask (struct intel_pcie *pcie,u32 ofs,u32 mask,u32 val) { -pcie_update_bits (lpp->app_base, ofs, mask, val); +pcie_update_bits (pcie->app_base, ofs, mask, val); } -static inline u32 pcie_rc_cfg_rd (struct intel_pcie_port *lpp,u32 ofs) +static inline u32 pcie_rc_cfg_rd (struct intel_pcie *pcie,u32 ofs) { -return dw_pcie_readl_dbi (&lpp->pci, ofs); +return dw_pcie_readl_dbi (&pcie->pci, ofs); } -static inline void pcie_rc_cfg_wr (struct intel_pcie_port *lpp,u32 ofs,u32 val) +static inline void pcie_rc_cfg_wr (struct intel_pcie *pcie,u32 ofs,u32 val) { -dw_pcie_writel_dbi (&lpp->pci, ofs, val); +dw_pcie_writel_dbi (&pcie->pci, ofs, val); } -static void pcie_rc_cfg_wr_mask (struct intel_pcie_port *lpp,u32 ofs, +static void pcie_rc_cfg_wr_mask (struct intel_pcie *pcie,u32 ofs,u32 mask,u32 val) { -pcie_update_bits (lpp->pci.dbi_base, ofs, mask, val); +pcie_update_bits (pcie->pci.dbi_base, ofs, mask, val); } -static void intel_pcie_ltssm_enable (struct intel_pcie_port *lpp) +static void intel_pcie_ltssm_enable (struct intel_pcie *pcie) { -pcie_app_wr_mask (lpp,PCIE_APP_CCR ,PCIE_APP_CCR_LTSSM_ENABLE , +pcie_app_wr_mask (pcie,PCIE_APP_CCR ,PCIE_APP_CCR_LTSSM_ENABLE ,PCIE_APP_CCR_LTSSM_ENABLE ); } -static void intel_pcie_ltssm_disable (struct intel_pcie_port *lpp) +static void intel_pcie_ltssm_disable (struct intel_pcie *pcie) { -pcie_app_wr_mask (lpp,PCIE_APP_CCR ,PCIE_APP_CCR_LTSSM_ENABLE ,0 ); +pcie_app_wr_mask (pcie,PCIE_APP_CCR ,PCIE_APP_CCR_LTSSM_ENABLE ,0 ); } -static void intel_pcie_link_setup (struct intel_pcie_port *lpp) +static void intel_pcie_link_setup (struct intel_pcie *pcie) {u32 val; -u8 offset =dw_pcie_find_capability (&lpp->pci,PCI_CAP_ID_EXP ); +u8 offset =dw_pcie_find_capability (&pcie->pci,PCI_CAP_ID_EXP ); - val =pcie_rc_cfg_rd (lpp, offset +PCI_EXP_LNKCTL ); + val =pcie_rc_cfg_rd (pcie, offset +PCI_EXP_LNKCTL ); val &= ~(PCI_EXP_LNKCTL_LD |PCI_EXP_LNKCTL_ASPMC ); -pcie_rc_cfg_wr (lpp, offset +PCI_EXP_LNKCTL , val); +pcie_rc_cfg_wr (pcie, offset +PCI_EXP_LNKCTL , val); }static void intel_pcie_init_n_fts (struct dw_pcie *pci)
@@ -148,14 +148,14 @@ static void intel_pcie_init_n_fts(struct dw_pcie *pci) pci->n_fts[0 ] =PORT_AFR_N_FTS_GEN12_DFT ; } -static int intel_pcie_ep_rst_init (struct intel_pcie_port *lpp) +static int intel_pcie_ep_rst_init (struct intel_pcie *pcie) { -struct device *dev = lpp->pci.dev; +struct device *dev = pcie->pci.dev;int ret; - lpp->reset_gpio =devm_gpiod_get (dev,"reset" ,GPIOD_OUT_LOW ); -if (IS_ERR (lpp->reset_gpio)) { - ret =PTR_ERR (lpp->reset_gpio); + pcie->reset_gpio =devm_gpiod_get (dev,"reset" ,GPIOD_OUT_LOW ); +if (IS_ERR (pcie->reset_gpio)) { + ret =PTR_ERR (pcie->reset_gpio);if (ret != -EPROBE_DEFER )dev_err (dev,"Failed to request PCIe GPIO: %d\n" , ret);return ret;
@@ -167,19 +167,19 @@ static int intel_pcie_ep_rst_init(struct intel_pcie_port *lpp)return 0 ; } -static void intel_pcie_core_rst_assert (struct intel_pcie_port *lpp) +static void intel_pcie_core_rst_assert (struct intel_pcie *pcie) { -reset_control_assert (lpp->core_rst); +reset_control_assert (pcie->core_rst); } -static void intel_pcie_core_rst_deassert (struct intel_pcie_port *lpp) +static void intel_pcie_core_rst_deassert (struct intel_pcie *pcie) {/* * One micro-second delay to make sure the reset pulse * wide enough so that core reset is clean. */ udelay (1 ); -reset_control_deassert (lpp->core_rst); +reset_control_deassert (pcie->core_rst);/* * Some SoC core reset also reset PHY, more delay needed
@@ -188,58 +188,58 @@ static void intel_pcie_core_rst_deassert(struct intel_pcie_port *lpp)usleep_range (1000 ,2000 ); } -static void intel_pcie_device_rst_assert (struct intel_pcie_port *lpp) +static void intel_pcie_device_rst_assert (struct intel_pcie *pcie) { -gpiod_set_value_cansleep (lpp->reset_gpio,1 ); +gpiod_set_value_cansleep (pcie->reset_gpio,1 ); } -static void intel_pcie_device_rst_deassert (struct intel_pcie_port *lpp) +static void intel_pcie_device_rst_deassert (struct intel_pcie *pcie) { -msleep (lpp->rst_intrvl); -gpiod_set_value_cansleep (lpp->reset_gpio,0 ); +msleep (pcie->rst_intrvl); +gpiod_set_value_cansleep (pcie->reset_gpio,0 ); } -static void intel_pcie_core_irq_disable (struct intel_pcie_port *lpp) +static void intel_pcie_core_irq_disable (struct intel_pcie *pcie) { -pcie_app_wr (lpp,PCIE_APP_IRNEN ,0 ); -pcie_app_wr (lpp,PCIE_APP_IRNCR ,PCIE_APP_IRN_INT ); +pcie_app_wr (pcie,PCIE_APP_IRNEN ,0 ); +pcie_app_wr (pcie,PCIE_APP_IRNCR ,PCIE_APP_IRN_INT ); }static int intel_pcie_get_resources (struct platform_device *pdev) { -struct intel_pcie_port *lpp =platform_get_drvdata (pdev); -struct dw_pcie *pci = &lpp->pci; +struct intel_pcie *pcie =platform_get_drvdata (pdev); +struct dw_pcie *pci = &pcie->pci;struct device *dev = pci->dev;int ret; - lpp->core_clk =devm_clk_get (dev,NULL ); -if (IS_ERR (lpp->core_clk)) { - ret =PTR_ERR (lpp->core_clk); + pcie->core_clk =devm_clk_get (dev,NULL ); +if (IS_ERR (pcie->core_clk)) { + ret =PTR_ERR (pcie->core_clk);if (ret != -EPROBE_DEFER )dev_err (dev,"Failed to get clks: %d\n" , ret);return ret; } - lpp->core_rst =devm_reset_control_get (dev,NULL ); -if (IS_ERR (lpp->core_rst)) { - ret =PTR_ERR (lpp->core_rst); + pcie->core_rst =devm_reset_control_get (dev,NULL ); +if (IS_ERR (pcie->core_rst)) { + ret =PTR_ERR (pcie->core_rst);if (ret != -EPROBE_DEFER )dev_err (dev,"Failed to get resets: %d\n" , ret);return ret; } ret =device_property_read_u32 (dev,"reset-assert-ms" , - &lpp->rst_intrvl); + &pcie->rst_intrvl);if (ret) - lpp->rst_intrvl =RESET_INTERVAL_MS ; + pcie->rst_intrvl =RESET_INTERVAL_MS ; - lpp->app_base =devm_platform_ioremap_resource_byname (pdev,"app" ); -if (IS_ERR (lpp->app_base)) -return PTR_ERR (lpp->app_base); + pcie->app_base =devm_platform_ioremap_resource_byname (pdev,"app" ); +if (IS_ERR (pcie->app_base)) +return PTR_ERR (pcie->app_base); - lpp->phy =devm_phy_get (dev,"pcie" ); -if (IS_ERR (lpp->phy)) { - ret =PTR_ERR (lpp->phy); + pcie->phy =devm_phy_get (dev,"pcie" ); +if (IS_ERR (pcie->phy)) { + ret =PTR_ERR (pcie->phy);if (ret != -EPROBE_DEFER )dev_err (dev,"Couldn't get pcie-phy: %d\n" , ret);return ret;
@@ -248,137 +248,137 @@ static int intel_pcie_get_resources(struct platform_device *pdev)return 0 ; } -static int intel_pcie_wait_l2 (struct intel_pcie_port *lpp) +static int intel_pcie_wait_l2 (struct intel_pcie *pcie) {u32 value;int ret; -struct dw_pcie *pci = &lpp->pci; +struct dw_pcie *pci = &pcie->pci;if (pci->link_gen <3 )return 0 ;/* Send PME_TURN_OFF message */ -pcie_app_wr_mask (lpp,PCIE_APP_MSG_CR ,PCIE_APP_MSG_XMT_PM_TURNOFF , +pcie_app_wr_mask (pcie,PCIE_APP_MSG_CR ,PCIE_APP_MSG_XMT_PM_TURNOFF ,PCIE_APP_MSG_XMT_PM_TURNOFF );/* Read PMC status and wait for falling into L2 link state */ - ret =readl_poll_timeout (lpp->app_base +PCIE_APP_PMC , value, + ret =readl_poll_timeout (pcie->app_base +PCIE_APP_PMC , value, value &PCIE_APP_PMC_IN_L2 ,20 ,jiffies_to_usecs (5 *HZ ));if (ret) -dev_err (lpp->pci.dev,"PCIe link enter L2 timeout!\n" ); +dev_err (pcie->pci.dev,"PCIe link enter L2 timeout!\n" );return ret; } -static void intel_pcie_turn_off (struct intel_pcie_port *lpp) +static void intel_pcie_turn_off (struct intel_pcie *pcie) { -if (dw_pcie_link_up (&lpp->pci)) -intel_pcie_wait_l2 (lpp); +if (dw_pcie_link_up (&pcie->pci)) +intel_pcie_wait_l2 (pcie);/* Put endpoint device in reset state */ -intel_pcie_device_rst_assert (lpp); -pcie_rc_cfg_wr_mask (lpp,PCI_COMMAND ,PCI_COMMAND_MEMORY ,0 ); +intel_pcie_device_rst_assert (pcie); +pcie_rc_cfg_wr_mask (pcie,PCI_COMMAND ,PCI_COMMAND_MEMORY ,0 ); } -static int intel_pcie_host_setup (struct intel_pcie_port *lpp) +static int intel_pcie_host_setup (struct intel_pcie *pcie) {int ret; -struct dw_pcie *pci = &lpp->pci; +struct dw_pcie *pci = &pcie->pci; -intel_pcie_core_rst_assert (lpp); -intel_pcie_device_rst_assert (lpp); +intel_pcie_core_rst_assert (pcie); +intel_pcie_device_rst_assert (pcie); - ret =phy_init (lpp->phy); + ret =phy_init (pcie->phy);if (ret)return ret; -intel_pcie_core_rst_deassert (lpp); +intel_pcie_core_rst_deassert (pcie); - ret =clk_prepare_enable (lpp->core_clk); + ret =clk_prepare_enable (pcie->core_clk);if (ret) { -dev_err (lpp->pci.dev,"Core clock enable failed: %d\n" , ret); +dev_err (pcie->pci.dev,"Core clock enable failed: %d\n" , ret); goto clk_err; } pci->atu_base = pci->dbi_base +0xC0000 ; -intel_pcie_ltssm_disable (lpp); -intel_pcie_link_setup (lpp); +intel_pcie_ltssm_disable (pcie); +intel_pcie_link_setup (pcie);intel_pcie_init_n_fts (pci);dw_pcie_setup_rc (&pci->pp);dw_pcie_upconfig_setup (pci); -intel_pcie_device_rst_deassert (lpp); -intel_pcie_ltssm_enable (lpp); +intel_pcie_device_rst_deassert (pcie); +intel_pcie_ltssm_enable (pcie); ret =dw_pcie_wait_for_link (pci);if (ret) goto app_init_err;/* Enable integrated interrupts */ -pcie_app_wr_mask (lpp,PCIE_APP_IRNEN ,PCIE_APP_IRN_INT , +pcie_app_wr_mask (pcie,PCIE_APP_IRNEN ,PCIE_APP_IRN_INT ,PCIE_APP_IRN_INT );return 0 ; app_init_err: -clk_disable_unprepare (lpp->core_clk); +clk_disable_unprepare (pcie->core_clk); clk_err: -intel_pcie_core_rst_assert (lpp); -phy_exit (lpp->phy); +intel_pcie_core_rst_assert (pcie); +phy_exit (pcie->phy);return ret; } -static void __intel_pcie_remove (struct intel_pcie_port *lpp) +static void __intel_pcie_remove (struct intel_pcie *pcie) { -intel_pcie_core_irq_disable (lpp); -intel_pcie_turn_off (lpp); -clk_disable_unprepare (lpp->core_clk); -intel_pcie_core_rst_assert (lpp); -phy_exit (lpp->phy); +intel_pcie_core_irq_disable (pcie); +intel_pcie_turn_off (pcie); +clk_disable_unprepare (pcie->core_clk); +intel_pcie_core_rst_assert (pcie); +phy_exit (pcie->phy); }static int intel_pcie_remove (struct platform_device *pdev) { -struct intel_pcie_port *lpp =platform_get_drvdata (pdev); -struct pcie_port *pp = &lpp->pci.pp; +struct intel_pcie *pcie =platform_get_drvdata (pdev); +struct pcie_port *pp = &pcie->pci.pp;dw_pcie_host_deinit (pp); -__intel_pcie_remove (lpp); +__intel_pcie_remove (pcie);return 0 ; }static int __maybe_unused intel_pcie_suspend_noirq (struct device *dev) { -struct intel_pcie_port *lpp =dev_get_drvdata (dev); +struct intel_pcie *pcie =dev_get_drvdata (dev);int ret; -intel_pcie_core_irq_disable (lpp); - ret =intel_pcie_wait_l2 (lpp); +intel_pcie_core_irq_disable (pcie); + ret =intel_pcie_wait_l2 (pcie);if (ret)return ret; -phy_exit (lpp->phy); -clk_disable_unprepare (lpp->core_clk); +phy_exit (pcie->phy); +clk_disable_unprepare (pcie->core_clk);return ret; }static int __maybe_unused intel_pcie_resume_noirq (struct device *dev) { -struct intel_pcie_port *lpp =dev_get_drvdata (dev); +struct intel_pcie *pcie =dev_get_drvdata (dev); -return intel_pcie_host_setup (lpp); +return intel_pcie_host_setup (pcie); }static int intel_pcie_rc_init (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct intel_pcie_port *lpp =dev_get_drvdata (pci->dev); +struct intel_pcie *pcie =dev_get_drvdata (pci->dev); -return intel_pcie_host_setup (lpp); +return intel_pcie_host_setup (pcie); }static u64 intel_pcie_cpu_addr (struct dw_pcie *pcie,u64 cpu_addr)
@@ -402,17 +402,17 @@ static int intel_pcie_probe(struct platform_device *pdev) {const struct intel_pcie_soc *data;struct device *dev = &pdev->dev; -struct intel_pcie_port *lpp; +struct intel_pcie *pcie;struct pcie_port *pp;struct dw_pcie *pci;int ret; - lpp =devm_kzalloc (dev,sizeof (*lpp),GFP_KERNEL ); -if (!lpp) + pcie =devm_kzalloc (dev,sizeof (*pcie),GFP_KERNEL ); +if (!pcie)return -ENOMEM ; -platform_set_drvdata (pdev, lpp); - pci = &lpp->pci; +platform_set_drvdata (pdev, pcie); + pci = &pcie->pci; pci->dev = dev; pp = &pci->pp;
@@ -420,7 +420,7 @@ static int intel_pcie_probe(struct platform_device *pdev)if (ret)return ret; - ret =intel_pcie_ep_rst_init (lpp); + ret =intel_pcie_ep_rst_init (pcie);if (ret)return ret;
Signature · 1 line
2.25.1
PATCH 3/6 PCI: uniphier: Rename struct uniphier_pcie_priv to uniphier_pcie
In reply to Fan FeiRename struct uniphier_pcie_priv to uniphier_pcie to match the convention of <driver>_pcie. No functional change intended.
Signed-off-by Fan Fei <[email protected]>
--- drivers/pci/controller/dwc/pcie-uniphier.c | 159 +++++++++++---------- 1 file changed, 87 insertions(+), 72 deletions(-)
drivers/pci/controller/dwc/pcie-uniphier.c +87 -72
@@ -61,7 +61,7 @@#define PCL_RDLH_LINK_UP BIT(1)#define PCL_XMLH_LINK_UP BIT(0) -struct uniphier_pcie_priv { +struct uniphier_pcie {void __iomem *base;struct dw_pcie pci;struct clk *clk;
@@ -72,62 +72,62 @@ struct uniphier_pcie_priv {#define to_uniphier_pcie (x) dev_get_drvdata((x)->dev) -static void uniphier_pcie_ltssm_enable (struct uniphier_pcie_priv *priv, +static void uniphier_pcie_ltssm_enable (struct uniphier_pcie *pcie,bool enable) {u32 val; - val =readl (priv->base +PCL_APP_READY_CTRL ); + val =readl (pcie->base +PCL_APP_READY_CTRL );if (enable) val |=PCL_APP_LTSSM_ENABLE ;else val &= ~PCL_APP_LTSSM_ENABLE ; -writel (val, priv->base +PCL_APP_READY_CTRL ); +writel (val, pcie->base +PCL_APP_READY_CTRL ); } -static void uniphier_pcie_init_rc (struct uniphier_pcie_priv *priv) +static void uniphier_pcie_init_rc (struct uniphier_pcie *pcie) {u32 val;/* set RC MODE */ - val =readl (priv->base +PCL_MODE ); + val =readl (pcie->base +PCL_MODE ); val |=PCL_MODE_REGEN ; val &= ~PCL_MODE_REGVAL ; -writel (val, priv->base +PCL_MODE ); +writel (val, pcie->base +PCL_MODE );/* use auxiliary power detection */ - val =readl (priv->base +PCL_APP_PM0 ); + val =readl (pcie->base +PCL_APP_PM0 ); val |=PCL_SYS_AUX_PWR_DET ; -writel (val, priv->base +PCL_APP_PM0 ); +writel (val, pcie->base +PCL_APP_PM0 );/* assert PERST# */ - val =readl (priv->base +PCL_PINCTRL0 ); + val =readl (pcie->base +PCL_PINCTRL0 ); val &= ~(PCL_PERST_NOE_REGVAL |PCL_PERST_OUT_REGVAL |PCL_PERST_PLDN_REGVAL ); val |=PCL_PERST_NOE_REGEN |PCL_PERST_OUT_REGEN |PCL_PERST_PLDN_REGEN ; -writel (val, priv->base +PCL_PINCTRL0 ); +writel (val, pcie->base +PCL_PINCTRL0 ); -uniphier_pcie_ltssm_enable (priv, false); +uniphier_pcie_ltssm_enable (pcie, false);usleep_range (100000 ,200000 );/* deassert PERST# */ - val =readl (priv->base +PCL_PINCTRL0 ); + val =readl (pcie->base +PCL_PINCTRL0 ); val |=PCL_PERST_OUT_REGVAL |PCL_PERST_OUT_REGEN ; -writel (val, priv->base +PCL_PINCTRL0 ); +writel (val, pcie->base +PCL_PINCTRL0 ); } -static int uniphier_pcie_wait_rc (struct uniphier_pcie_priv *priv) +static int uniphier_pcie_wait_rc (struct uniphier_pcie *pcie) {u32 status;int ret;/* wait PIPE clock */ - ret =readl_poll_timeout (priv->base +PCL_PIPEMON , status, + ret =readl_poll_timeout (pcie->base +PCL_PIPEMON , status, status &PCL_PCLK_ALIVE ,100000 ,1000000 );if (ret) { -dev_err (priv->pci.dev, +dev_err (pcie->pci.dev,"Failed to initialize controller in RC mode\n" );return ret; }
@@ -137,10 +137,10 @@ static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)static int uniphier_pcie_link_up (struct dw_pcie *pci) { -struct uniphier_pcie_priv *priv =to_uniphier_pcie (pci); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci);u32 val, mask; - val =readl (priv->base +PCL_STATUS_LINK ); + val =readl (pcie->base +PCL_STATUS_LINK ); mask =PCL_RDLH_LINK_UP |PCL_XMLH_LINK_UP ;return (val & mask) == mask;
@@ -148,39 +148,54 @@ static int uniphier_pcie_link_up(struct dw_pcie *pci)static int uniphier_pcie_start_link (struct dw_pcie *pci) { -struct uniphier_pcie_priv *priv =to_uniphier_pcie (pci); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci); -uniphier_pcie_ltssm_enable (priv, true); +uniphier_pcie_ltssm_enable (pcie, true);return 0 ; }static void uniphier_pcie_stop_link (struct dw_pcie *pci) { -struct uniphier_pcie_priv *priv =to_uniphier_pcie (pci); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci); -uniphier_pcie_ltssm_enable (priv, false); +uniphier_pcie_ltssm_enable (pcie, false); } -static void uniphier_pcie_irq_enable (struct uniphier_pcie_priv *priv) +static void uniphier_pcie_irq_enable (struct uniphier_pcie *pcie) { -writel (PCL_RCV_INT_ALL_ENABLE , priv->base +PCL_RCV_INT ); -writel (PCL_RCV_INTX_ALL_ENABLE , priv->base +PCL_RCV_INTX ); +writel (PCL_RCV_INT_ALL_ENABLE , pcie->base +PCL_RCV_INT ); +writel (PCL_RCV_INTX_ALL_ENABLE , pcie->base +PCL_RCV_INTX ); } + +static void uniphier_pcie_irq_ack (struct irq_data *d) +{ +struct pcie_port *pp =irq_data_get_irq_chip_data (d); +struct dw_pcie *pci =to_dw_pcie_from_pp (pp); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci); +u32 val; + + val =readl (pcie->base +PCL_RCV_INTX ); + val &= ~PCL_RCV_INTX_ALL_STATUS ; + val |=BIT (irqd_to_hwirq (d) +PCL_RCV_INTX_STATUS_SHIFT ); +writel (val, pcie->base +PCL_RCV_INTX ); +} + +static void uniphier_pcie_irq_mask (struct irq_data *d) {struct pcie_port *pp =irq_data_get_irq_chip_data (d);struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct uniphier_pcie_priv *priv =to_uniphier_pcie (pci); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci);unsigned long flags;u32 val;raw_spin_lock_irqsave (&pp->lock, flags); - val =readl (priv->base +PCL_RCV_INTX ); + val =readl (pcie->base +PCL_RCV_INTX ); val |=BIT (irqd_to_hwirq (d) +PCL_RCV_INTX_MASK_SHIFT ); -writel (val, priv->base +PCL_RCV_INTX ); +writel (val, pcie->base +PCL_RCV_INTX );raw_spin_unlock_irqrestore (&pp->lock, flags); }
@@ -189,15 +204,15 @@ static void uniphier_pcie_irq_unmask(struct irq_data *d) {struct pcie_port *pp =irq_data_get_irq_chip_data (d);struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct uniphier_pcie_priv *priv =to_uniphier_pcie (pci); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci);unsigned long flags;u32 val;raw_spin_lock_irqsave (&pp->lock, flags); - val =readl (priv->base +PCL_RCV_INTX ); + val =readl (pcie->base +PCL_RCV_INTX ); val &= ~BIT (irqd_to_hwirq (d) +PCL_RCV_INTX_MASK_SHIFT ); -writel (val, priv->base +PCL_RCV_INTX ); +writel (val, pcie->base +PCL_RCV_INTX );raw_spin_unlock_irqrestore (&pp->lock, flags); }
@@ -226,13 +241,13 @@ static void uniphier_pcie_irq_handler(struct irq_desc *desc) {struct pcie_port *pp =irq_desc_get_handler_data (desc);struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct uniphier_pcie_priv *priv =to_uniphier_pcie (pci); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci);struct irq_chip *chip =irq_desc_get_chip (desc);unsigned long reg;u32 val, bit;/* INT for debug */ - val =readl (priv->base +PCL_RCV_INT ); + val =readl (pcie->base +PCL_RCV_INT );if (val &PCL_CFG_BW_MGT_STATUS )dev_dbg (pci->dev,"Link Bandwidth Management Event\n" );
@@ -243,16 +258,16 @@ static void uniphier_pcie_irq_handler(struct irq_desc *desc)if (val &PCL_CFG_PME_MSI_STATUS )dev_dbg (pci->dev,"PME Interrupt\n" ); -writel (val, priv->base +PCL_RCV_INT ); +writel (val, pcie->base +PCL_RCV_INT );/* INTx */ chained_irq_enter (chip, desc); - val =readl (priv->base +PCL_RCV_INTX ); + val =readl (pcie->base +PCL_RCV_INTX ); reg =FIELD_GET (PCL_RCV_INTX_ALL_STATUS , val);for_each_set_bit (bit, ®,PCI_NUM_INTX ) -generic_handle_domain_irq (priv->legacy_irq_domain, bit); +generic_handle_domain_irq (pcie->legacy_irq_domain, bit);chained_irq_exit (chip, desc); }
@@ -260,7 +275,7 @@ static void uniphier_pcie_irq_handler(struct irq_desc *desc)static int uniphier_pcie_config_legacy_irq (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct uniphier_pcie_priv *priv =to_uniphier_pcie (pci); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci);struct device_node *np = pci->dev->of_node;struct device_node *np_intc;int ret =0 ;
@@ -278,9 +293,9 @@ static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp) goto out_put_node; } - priv->legacy_irq_domain =irq_domain_add_linear (np_intc,PCI_NUM_INTX , + pcie->legacy_irq_domain =irq_domain_add_linear (np_intc,PCI_NUM_INTX , &uniphier_intx_domain_ops, pp); -if (!priv->legacy_irq_domain) { +if (!pcie->legacy_irq_domain) {dev_err (pci->dev,"Failed to get INTx domain\n" ); ret = -ENODEV ; goto out_put_node;
@@ -297,14 +312,14 @@ static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)static int uniphier_pcie_host_init (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct uniphier_pcie_priv *priv =to_uniphier_pcie (pci); +struct uniphier_pcie *pcie =to_uniphier_pcie (pci);int ret; ret =uniphier_pcie_config_legacy_irq (pp);if (ret)return ret; -uniphier_pcie_irq_enable (priv); +uniphier_pcie_irq_enable (pcie);return 0 ; }
@@ -313,36 +328,36 @@ static const struct dw_pcie_host_ops uniphier_pcie_host_ops = { .host_init = uniphier_pcie_host_init, }; -static int uniphier_pcie_host_enable (struct uniphier_pcie_priv *priv) +static int uniphier_pcie_host_enable (struct uniphier_pcie *pcie) {int ret; - ret =clk_prepare_enable (priv->clk); + ret =clk_prepare_enable (pcie->clk);if (ret)return ret; - ret =reset_control_deassert (priv->rst); + ret =reset_control_deassert (pcie->rst);if (ret) goto out_clk_disable; -uniphier_pcie_init_rc (priv); +uniphier_pcie_init_rc (pcie); - ret =phy_init (priv->phy); + ret =phy_init (pcie->phy);if (ret) goto out_rst_assert; - ret =uniphier_pcie_wait_rc (priv); + ret =uniphier_pcie_wait_rc (pcie);if (ret) goto out_phy_exit;return 0 ; out_phy_exit: -phy_exit (priv->phy); +phy_exit (pcie->phy); out_rst_assert: -reset_control_assert (priv->rst); +reset_control_assert (pcie->rst); out_clk_disable: -clk_disable_unprepare (priv->clk); +clk_disable_unprepare (pcie->clk);return ret; }
@@ -356,41 +371,41 @@ static const struct dw_pcie_ops dw_pcie_ops = {static int uniphier_pcie_probe (struct platform_device *pdev) {struct device *dev = &pdev->dev; -struct uniphier_pcie_priv *priv; +struct uniphier_pcie *pcie;int ret; - priv =devm_kzalloc (dev,sizeof (*priv),GFP_KERNEL ); -if (!priv) + pcie =devm_kzalloc (dev,sizeof (*pcie),GFP_KERNEL ); +if (!pcie)return -ENOMEM ; - priv->pci.dev = dev; - priv->pci.ops = &dw_pcie_ops; + pcie->pci.dev = dev; + pcie->pci.ops = &dw_pcie_ops; - priv->base =devm_platform_ioremap_resource_byname (pdev,"link" ); -if (IS_ERR (priv->base)) -return PTR_ERR (priv->base); + pcie->base =devm_platform_ioremap_resource_byname (pdev,"link" ); +if (IS_ERR (pcie->base)) +return PTR_ERR (pcie->base); - priv->clk =devm_clk_get (dev,NULL ); -if (IS_ERR (priv->clk)) -return PTR_ERR (priv->clk); + pcie->clk =devm_clk_get (dev,NULL ); +if (IS_ERR (pcie->clk)) +return PTR_ERR (pcie->clk); - priv->rst =devm_reset_control_get_shared (dev,NULL ); -if (IS_ERR (priv->rst)) -return PTR_ERR (priv->rst); + pcie->rst =devm_reset_control_get_shared (dev,NULL ); +if (IS_ERR (pcie->rst)) +return PTR_ERR (pcie->rst); - priv->phy =devm_phy_optional_get (dev,"pcie-phy" ); -if (IS_ERR (priv->phy)) -return PTR_ERR (priv->phy); + pcie->phy =devm_phy_optional_get (dev,"pcie-phy" ); +if (IS_ERR (pcie->phy)) +return PTR_ERR (pcie->phy); -platform_set_drvdata (pdev, priv); +platform_set_drvdata (pdev, pcie); - ret =uniphier_pcie_host_enable (priv); + ret =uniphier_pcie_host_enable (pcie);if (ret)return ret; - priv->pci.pp.ops = &uniphier_pcie_host_ops; + pcie->pci.pp.ops = &uniphier_pcie_host_ops; -return dw_pcie_host_init (&priv->pci.pp); +return dw_pcie_host_init (&pcie->pci.pp); }static const struct of_device_id uniphier_pcie_match[] = {
Signature · 1 line
2.25.1
PATCH 4/6 PCI: tegra194: Rename struct tegra_pcie_dw to tegra194_pcie
In reply to Fan FeiRename struct tegra_pcie_dw to tegra194_pcie to match the convention of <driver>_pcie. No functional change intended.
Signed-off-by Fan Fei <[email protected]>
--- drivers/pci/controller/dwc/pcie-tegra194.c | 120 ++++++++++----------- 1 file changed, 60 insertions(+), 60 deletions(-)
drivers/pci/controller/dwc/pcie-tegra194.c +60 -60
@@ -245,7 +245,7 @@ static const unsigned int pcie_gen_freq[] = {GEN4_CORE_CLK_FREQ }; -struct tegra_pcie_dw { +struct tegra194_pcie {struct device *dev;struct resource *appl_res;struct resource *dbi_res;
@@ -293,18 +293,18 @@ struct tegra_pcie_dw_of_data {enum dw_pcie_device_mode mode; }; -static inline struct tegra_pcie_dw *to_tegra_pcie (struct dw_pcie *pci) +static inline struct tegra194_pcie *to_tegra_pcie (struct dw_pcie *pci) { - return container_of(pci, struct tegra_pcie_dw, pci); + return container_of(pci, struct tegra194_pcie, pci); } -static inline void appl_writel (struct tegra_pcie_dw *pcie,const u32 value, +static inline void appl_writel (struct tegra194_pcie *pcie,const u32 value,const u32 reg) {writel_relaxed (value, pcie->appl_base + reg); } -static inline u32 appl_readl (struct tegra_pcie_dw *pcie,const u32 reg) +static inline u32 appl_readl (struct tegra194_pcie *pcie,const u32 reg) {return readl_relaxed (pcie->appl_base + reg); }
@@ -316,7 +316,7 @@ struct tegra_pcie_soc {static void apply_bad_link_workaround (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);u32 current_link_width;u16 val;
@@ -349,7 +349,7 @@ static void apply_bad_link_workaround(struct pcie_port *pp)static irqreturn_t tegra_pcie_rp_irq_handler (int irq,void *arg) { -struct tegra_pcie_dw *pcie = arg; +struct tegra194_pcie *pcie = arg;struct dw_pcie *pci = &pcie->pci;struct pcie_port *pp = &pci->pp;u32 val, tmp;
@@ -420,7 +420,7 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)return IRQ_HANDLED ; } -static void pex_ep_event_hot_rst_done (struct tegra_pcie_dw *pcie) +static void pex_ep_event_hot_rst_done (struct tegra194_pcie *pcie) {u32 val;
@@ -448,7 +448,7 @@ static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie)static irqreturn_t tegra_pcie_ep_irq_thread (int irq,void *arg) { -struct tegra_pcie_dw *pcie = arg; +struct tegra194_pcie *pcie = arg;struct dw_pcie *pci = &pcie->pci;u32 val, speed;
@@ -494,7 +494,7 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)static irqreturn_t tegra_pcie_ep_hard_irq (int irq,void *arg) { -struct tegra_pcie_dw *pcie = arg; +struct tegra194_pcie *pcie = arg;struct dw_pcie_ep *ep = &pcie->pci.ep;int spurious =1 ;u32 status_l0, status_l1, link_status;
@@ -594,7 +594,7 @@ static const u32 event_cntr_data_offset[] = { 0x1dc }; -static void disable_aspm_l11 (struct tegra_pcie_dw *pcie) +static void disable_aspm_l11 (struct tegra194_pcie *pcie) {u32 val;
@@ -603,7 +603,7 @@ static void disable_aspm_l11(struct tegra_pcie_dw *pcie)dw_pcie_writel_dbi (&pcie->pci, pcie->cfg_link_cap_l1sub, val); } -static void disable_aspm_l12 (struct tegra_pcie_dw *pcie) +static void disable_aspm_l12 (struct tegra194_pcie *pcie) {u32 val;
@@ -612,7 +612,7 @@ static void disable_aspm_l12(struct tegra_pcie_dw *pcie)dw_pcie_writel_dbi (&pcie->pci, pcie->cfg_link_cap_l1sub, val); } -static inline u32 event_counter_prog (struct tegra_pcie_dw *pcie,u32 event) +static inline u32 event_counter_prog (struct tegra194_pcie *pcie,u32 event) {u32 val;
@@ -629,7 +629,7 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)static int aspm_state_cnt (struct seq_file *s,void *data) { -struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *) +struct tegra194_pcie *pcie = (struct tegra194_pcie *)dev_get_drvdata (s->private);u32 val;
@@ -660,7 +660,7 @@ static int aspm_state_cnt(struct seq_file *s, void *data)return 0 ; } -static void init_host_aspm (struct tegra_pcie_dw *pcie) +static void init_host_aspm (struct tegra194_pcie *pcie) {struct dw_pcie *pci = &pcie->pci;u32 val;
@@ -688,22 +688,22 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)dw_pcie_writel_dbi (pci,PCIE_PORT_AFR , val); } -static void init_debugfs (struct tegra_pcie_dw *pcie) +static void init_debugfs (struct tegra194_pcie *pcie) {debugfs_create_devm_seqfile (pcie->dev,"aspm_state_cnt" , pcie->debugfs, aspm_state_cnt); }#else -static inline void disable_aspm_l12 (struct tegra_pcie_dw *pcie) {return ; } -static inline void disable_aspm_l11 (struct tegra_pcie_dw *pcie) {return ; } -static inline void init_host_aspm (struct tegra_pcie_dw *pcie) {return ; } -static inline void init_debugfs (struct tegra_pcie_dw *pcie) {return ; } +static inline void disable_aspm_l12 (struct tegra194_pcie *pcie) {return ; } +static inline void disable_aspm_l11 (struct tegra194_pcie *pcie) {return ; } +static inline void init_host_aspm (struct tegra194_pcie *pcie) {return ; } +static inline void init_debugfs (struct tegra194_pcie *pcie) {return ; }#endif static void tegra_pcie_enable_system_interrupts (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);u32 val;u16 val_w;
@@ -741,7 +741,7 @@ static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)static void tegra_pcie_enable_legacy_interrupts (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);u32 val;/* Enable legacy interrupt generation */
@@ -762,7 +762,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)static void tegra_pcie_enable_msi_interrupts (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);u32 val;/* Enable MSI interrupt generation */
@@ -775,7 +775,7 @@ static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)static void tegra_pcie_enable_interrupts (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);/* Clear interrupt statuses before enabling interrupts */ appl_writel (pcie,0xFFFFFFFF ,APPL_INTR_STATUS_L0 );
@@ -800,7 +800,7 @@ static void tegra_pcie_enable_interrupts(struct pcie_port *pp)tegra_pcie_enable_msi_interrupts (pp); } -static void config_gen3_gen4_eq_presets (struct tegra_pcie_dw *pcie) +static void config_gen3_gen4_eq_presets (struct tegra194_pcie *pcie) {struct dw_pcie *pci = &pcie->pci;u32 val, offset, i;
@@ -856,7 +856,7 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)static int tegra_pcie_dw_host_init (struct pcie_port *pp) {struct dw_pcie *pci =to_dw_pcie_from_pp (pp); -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);u32 val; pp->bridge->ops = &tegra_pci_ops;
@@ -917,7 +917,7 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)static int tegra_pcie_dw_start_link (struct dw_pcie *pci) {u32 val, offset, speed, tmp; -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);struct pcie_port *pp = &pci->pp;bool retry = true;
@@ -1000,7 +1000,7 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)static int tegra_pcie_dw_link_up (struct dw_pcie *pci) { -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);u32 val =dw_pcie_readw_dbi (pci, pcie->pcie_cap_base +PCI_EXP_LNKSTA );return !!(val &PCI_EXP_LNKSTA_DLLLA );
@@ -1008,7 +1008,7 @@ static int tegra_pcie_dw_link_up(struct dw_pcie *pci)static void tegra_pcie_dw_stop_link (struct dw_pcie *pci) { -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);disable_irq (pcie->pex_rst_irq); }
@@ -1023,7 +1023,7 @@ static const struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { .host_init = tegra_pcie_dw_host_init, }; -static void tegra_pcie_disable_phy (struct tegra_pcie_dw *pcie) +static void tegra_pcie_disable_phy (struct tegra194_pcie *pcie) {unsigned int phy_count = pcie->phy_count;
@@ -1033,7 +1033,7 @@ static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) } } -static int tegra_pcie_enable_phy (struct tegra_pcie_dw *pcie) +static int tegra_pcie_enable_phy (struct tegra194_pcie *pcie) {unsigned int i;int ret;
@@ -1060,7 +1060,7 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)return ret; } -static int tegra_pcie_dw_parse_dt (struct tegra_pcie_dw *pcie) +static int tegra_pcie_dw_parse_dt (struct tegra194_pcie *pcie) {struct platform_device *pdev =to_platform_device (pcie->dev);struct device_node *np = pcie->dev->of_node;
@@ -1156,7 +1156,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)return 0 ; } -static int tegra_pcie_bpmp_set_ctrl_state (struct tegra_pcie_dw *pcie, +static int tegra_pcie_bpmp_set_ctrl_state (struct tegra194_pcie *pcie,bool enable) {struct mrq_uphy_response resp;
@@ -1184,7 +1184,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,return tegra_bpmp_transfer (pcie->bpmp, &msg); } -static int tegra_pcie_bpmp_set_pll_state (struct tegra_pcie_dw *pcie, +static int tegra_pcie_bpmp_set_pll_state (struct tegra194_pcie *pcie,bool enable) {struct mrq_uphy_response resp;
@@ -1212,7 +1212,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,return tegra_bpmp_transfer (pcie->bpmp, &msg); } -static void tegra_pcie_downstream_dev_to_D0 (struct tegra_pcie_dw *pcie) +static void tegra_pcie_downstream_dev_to_D0 (struct tegra194_pcie *pcie) {struct pcie_port *pp = &pcie->pci.pp;struct pci_bus *child, *root_bus =NULL ;
@@ -1250,7 +1250,7 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) } } -static int tegra_pcie_get_slot_regulators (struct tegra_pcie_dw *pcie) +static int tegra_pcie_get_slot_regulators (struct tegra194_pcie *pcie) { pcie->slot_ctl_3v3 =devm_regulator_get_optional (pcie->dev,"vpcie3v3" );if (IS_ERR (pcie->slot_ctl_3v3)) {
@@ -1271,7 +1271,7 @@ static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)return 0 ; } -static int tegra_pcie_enable_slot_regulators (struct tegra_pcie_dw *pcie) +static int tegra_pcie_enable_slot_regulators (struct tegra194_pcie *pcie) {int ret;
@@ -1309,7 +1309,7 @@ static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)return ret; } -static void tegra_pcie_disable_slot_regulators (struct tegra_pcie_dw *pcie) +static void tegra_pcie_disable_slot_regulators (struct tegra194_pcie *pcie) {if (pcie->slot_ctl_12v)regulator_disable (pcie->slot_ctl_12v);
@@ -1317,7 +1317,7 @@ static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)regulator_disable (pcie->slot_ctl_3v3); } -static int tegra_pcie_config_controller (struct tegra_pcie_dw *pcie, +static int tegra_pcie_config_controller (struct tegra194_pcie *pcie,bool en_hw_hot_rst) {int ret;
@@ -1414,7 +1414,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,return ret; } -static void tegra_pcie_unconfig_controller (struct tegra_pcie_dw *pcie) +static void tegra_pcie_unconfig_controller (struct tegra194_pcie *pcie) {int ret;
@@ -1442,7 +1442,7 @@ static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie) pcie->cid, ret); } -static int tegra_pcie_init_controller (struct tegra_pcie_dw *pcie) +static int tegra_pcie_init_controller (struct tegra194_pcie *pcie) {struct dw_pcie *pci = &pcie->pci;struct pcie_port *pp = &pci->pp;
@@ -1467,7 +1467,7 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)return ret; } -static int tegra_pcie_try_link_l2 (struct tegra_pcie_dw *pcie) +static int tegra_pcie_try_link_l2 (struct tegra194_pcie *pcie) {u32 val;
@@ -1483,7 +1483,7 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) 1, PME_ACK_TIMEOUT); } -static void tegra_pcie_dw_pme_turnoff (struct tegra_pcie_dw *pcie) +static void tegra_pcie_dw_pme_turnoff (struct tegra194_pcie *pcie) {u32 data;int err;
@@ -1545,7 +1545,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)appl_writel (pcie, data,APPL_PINMUX ); } -static void tegra_pcie_deinit_controller (struct tegra_pcie_dw *pcie) +static void tegra_pcie_deinit_controller (struct tegra194_pcie *pcie) {tegra_pcie_downstream_dev_to_D0 (pcie);dw_pcie_host_deinit (&pcie->pci.pp);
@@ -1553,7 +1553,7 @@ static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)tegra_pcie_unconfig_controller (pcie); } -static int tegra_pcie_config_rp (struct tegra_pcie_dw *pcie) +static int tegra_pcie_config_rp (struct tegra194_pcie *pcie) {struct device *dev = pcie->dev;char *name;
@@ -1605,7 +1605,7 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)return ret; } -static void pex_ep_event_pex_rst_assert (struct tegra_pcie_dw *pcie) +static void pex_ep_event_pex_rst_assert (struct tegra194_pcie *pcie) {u32 val;int ret;
@@ -1644,7 +1644,7 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)dev_dbg (pcie->dev,"Uninitialization of endpoint is completed\n" ); } -static void pex_ep_event_pex_rst_deassert (struct tegra_pcie_dw *pcie) +static void pex_ep_event_pex_rst_deassert (struct tegra194_pcie *pcie) {struct dw_pcie *pci = &pcie->pci;struct dw_pcie_ep *ep = &pci->ep;
@@ -1809,7 +1809,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)static irqreturn_t tegra_pcie_ep_pex_rst_irq (int irq,void *arg) { -struct tegra_pcie_dw *pcie = arg; +struct tegra194_pcie *pcie = arg;if (gpiod_get_value (pcie->pex_rst_gpiod))pex_ep_event_pex_rst_assert (pcie);
@@ -1819,7 +1819,7 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)return IRQ_HANDLED ; } -static int tegra_pcie_ep_raise_legacy_irq (struct tegra_pcie_dw *pcie,u16 irq) +static int tegra_pcie_ep_raise_legacy_irq (struct tegra194_pcie *pcie,u16 irq) {/* Tegra194 supports only INTA */ if (irq >1 )
@@ -1831,7 +1831,7 @@ static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq)return 0 ; } -static int tegra_pcie_ep_raise_msi_irq (struct tegra_pcie_dw *pcie,u16 irq) +static int tegra_pcie_ep_raise_msi_irq (struct tegra194_pcie *pcie,u16 irq) {if (unlikely (irq >31 ))return -EINVAL ;
@@ -1841,7 +1841,7 @@ static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)return 0 ; } -static int tegra_pcie_ep_raise_msix_irq (struct tegra_pcie_dw *pcie,u16 irq) +static int tegra_pcie_ep_raise_msix_irq (struct tegra194_pcie *pcie,u16 irq) {struct dw_pcie_ep *ep = &pcie->pci.ep;
@@ -1855,7 +1855,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, u16 interrupt_num) {struct dw_pcie *pci =to_dw_pcie_from_ep (ep); -struct tegra_pcie_dw *pcie =to_tegra_pcie (pci); +struct tegra194_pcie *pcie =to_tegra_pcie (pci);switch (type) {case PCI_EPC_IRQ_LEGACY :
@@ -1896,7 +1896,7 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = { .get_features = tegra_pcie_ep_get_features, }; -static int tegra_pcie_config_ep (struct tegra_pcie_dw *pcie, +static int tegra_pcie_config_ep (struct tegra194_pcie *pcie,struct platform_device *pdev) {struct dw_pcie *pci = &pcie->pci;
@@ -1962,7 +1962,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)const struct tegra_pcie_dw_of_data *data;struct device *dev = &pdev->dev;struct resource *atu_dma_res; -struct tegra_pcie_dw *pcie; +struct tegra194_pcie *pcie;struct pcie_port *pp;struct dw_pcie *pci;struct phy **phys;
@@ -2148,7 +2148,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)static int tegra_pcie_dw_remove (struct platform_device *pdev) { -struct tegra_pcie_dw *pcie =platform_get_drvdata (pdev); +struct tegra194_pcie *pcie =platform_get_drvdata (pdev);if (!pcie->link_state)return 0 ;
@@ -2166,7 +2166,7 @@ static int tegra_pcie_dw_remove(struct platform_device *pdev)static int tegra_pcie_dw_suspend_late (struct device *dev) { -struct tegra_pcie_dw *pcie =dev_get_drvdata (dev); +struct tegra194_pcie *pcie =dev_get_drvdata (dev);u32 val;if (!pcie->link_state)
@@ -2184,7 +2184,7 @@ static int tegra_pcie_dw_suspend_late(struct device *dev)static int tegra_pcie_dw_suspend_noirq (struct device *dev) { -struct tegra_pcie_dw *pcie =dev_get_drvdata (dev); +struct tegra194_pcie *pcie =dev_get_drvdata (dev);if (!pcie->link_state)return 0 ;
@@ -2201,7 +2201,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)static int tegra_pcie_dw_resume_noirq (struct device *dev) { -struct tegra_pcie_dw *pcie =dev_get_drvdata (dev); +struct tegra194_pcie *pcie =dev_get_drvdata (dev);int ret;if (!pcie->link_state)
@@ -2236,7 +2236,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)static int tegra_pcie_dw_resume_early (struct device *dev) { -struct tegra_pcie_dw *pcie =dev_get_drvdata (dev); +struct tegra194_pcie *pcie =dev_get_drvdata (dev);u32 val;if (pcie->mode ==DW_PCIE_EP_TYPE ) {
@@ -2261,7 +2261,7 @@ static int tegra_pcie_dw_resume_early(struct device *dev)static void tegra_pcie_dw_shutdown (struct platform_device *pdev) { -struct tegra_pcie_dw *pcie =platform_get_drvdata (pdev); +struct tegra194_pcie *pcie =platform_get_drvdata (pdev);if (!pcie->link_state)return ;
Signature · 1 line
2.25.1
PATCH 5/6 PCI: xilinx: Rename struct xilinx_pcie_port to xilinx_pcie
In reply to Fan FeiRename struct xilinx_pcie_port to xilinx_pcie to match the convention of <driver>_pcie. No functional change intended.
Signed-off-by Fan Fei <[email protected]>
--- drivers/pci/controller/pcie-xilinx.c | 154 +++++++++++++-------------- 1 file changed, 77 insertions(+), 77 deletions(-)
drivers/pci/controller/pcie-xilinx.c +77 -77
@@ -91,7 +91,7 @@#define XILINX_NUM_MSI_IRQS 128/** -* struct xilinx_pcie_port - PCIe port information +* struct xilinx_pcie - PCIe port information * @reg_base: IO Mapped Register Base * @dev: Device pointer * @msi_map: Bitmap of allocated MSIs
@@ -100,7 +100,7 @@* @leg_domain: Legacy IRQ domain pointer * @resources: Bus Resources */ -struct xilinx_pcie_port { +struct xilinx_pcie {void __iomem *reg_base;struct device *dev;unsigned long msi_map[BITS_TO_LONGS (XILINX_NUM_MSI_IRQS )];
@@ -110,35 +110,35 @@ struct xilinx_pcie_port {struct list_head resources; }; -static inline u32 pcie_read (struct xilinx_pcie_port *port,u32 reg) +static inline u32 pcie_read (struct xilinx_pcie *pcie,u32 reg) { -return readl (port->reg_base + reg); +return readl (pcie->reg_base + reg); } -static inline void pcie_write (struct xilinx_pcie_port *port,u32 val,u32 reg) +static inline void pcie_write (struct xilinx_pcie *pcie,u32 val,u32 reg) { -writel (val, port->reg_base + reg); +writel (val, pcie->reg_base + reg); } -static inline bool xilinx_pcie_link_up (struct xilinx_pcie_port *port) +static inline bool xilinx_pcie_link_up (struct xilinx_pcie *pcie) { -return (pcie_read (port,XILINX_PCIE_REG_PSCR ) & +return (pcie_read (pcie,XILINX_PCIE_REG_PSCR ) &XILINX_PCIE_REG_PSCR_LNKUP ) ?1 :0 ; }/** * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts -* @port: PCIe port information +* @pcie: PCIe port information */ -static void xilinx_pcie_clear_err_interrupts (struct xilinx_pcie_port *port) +static void xilinx_pcie_clear_err_interrupts (struct xilinx_pcie *pcie) { -struct device *dev = port->dev; -unsigned long val =pcie_read (port,XILINX_PCIE_REG_RPEFR ); +struct device *dev = pcie->dev; +unsigned long val =pcie_read (pcie,XILINX_PCIE_REG_RPEFR );if (val &XILINX_PCIE_RPEFR_ERR_VALID ) {dev_dbg (dev,"Requester ID %lu\n" , val &XILINX_PCIE_RPEFR_REQ_ID ); -pcie_write (port,XILINX_PCIE_RPEFR_ALL_MASK , +pcie_write (pcie,XILINX_PCIE_RPEFR_ALL_MASK ,XILINX_PCIE_REG_RPEFR ); } }
@@ -152,11 +152,11 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)*/ static bool xilinx_pcie_valid_device (struct pci_bus *bus,unsigned int devfn) { -struct xilinx_pcie_port *port = bus->sysdata; +struct xilinx_pcie *pcie = bus->sysdata; -/* Check if link is up when trying to access downstream ports */ +/* Check if link is up when trying to access downstream pcie ports */ if (!pci_is_root_bus (bus)) { -if (!xilinx_pcie_link_up (port)) +if (!xilinx_pcie_link_up (pcie))return false; }else if (devfn >0 ) {/* Only one device down on each root port */
@@ -177,12 +177,12 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)static void __iomem *xilinx_pcie_map_bus (struct pci_bus *bus,unsigned int devfn,int where) { -struct xilinx_pcie_port *port = bus->sysdata; +struct xilinx_pcie *pcie = bus->sysdata;if (!xilinx_pcie_valid_device (bus, devfn))return NULL ; -return port->reg_base +PCIE_ECAM_OFFSET (bus->number, devfn, where); +return pcie->reg_base +PCIE_ECAM_OFFSET (bus->number, devfn, where); }/* PCIe operations */
@@ -215,7 +215,7 @@ static int xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask *masstatic void xilinx_compose_msi_msg (struct irq_data *data,struct msi_msg *msg) { -struct xilinx_pcie_port *pcie =irq_data_get_irq_chip_data (data); +struct xilinx_pcie *pcie =irq_data_get_irq_chip_data (data);phys_addr_t pa =ALIGN_DOWN (virt_to_phys (pcie),SZ_4K ); msg->address_lo =lower_32_bits (pa);
@@ -232,14 +232,14 @@ static struct irq_chip xilinx_msi_bottom_chip = {static int xilinx_msi_domain_alloc (struct irq_domain *domain,unsigned int virq,unsigned int nr_irqs,void *args) { -struct xilinx_pcie_port *port = domain->host_data; +struct xilinx_pcie *pcie = domain->host_data;int hwirq, i; -mutex_lock (&port->map_lock); +mutex_lock (&pcie->map_lock); - hwirq =bitmap_find_free_region (port->msi_map,XILINX_NUM_MSI_IRQS ,order_base_2 (nr_irqs)); + hwirq =bitmap_find_free_region (pcie->msi_map,XILINX_NUM_MSI_IRQS ,order_base_2 (nr_irqs)); -mutex_unlock (&port->map_lock); +mutex_unlock (&pcie->map_lock);if (hwirq <0 )return -ENOSPC ;
@@ -256,13 +256,13 @@ static void xilinx_msi_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) {struct irq_data *d =irq_domain_get_irq_data (domain, virq); -struct xilinx_pcie_port *port = domain->host_data; +struct xilinx_pcie *pcie = domain->host_data; -mutex_lock (&port->map_lock); +mutex_lock (&pcie->map_lock); -bitmap_release_region (port->msi_map, d->hwirq,order_base_2 (nr_irqs)); +bitmap_release_region (pcie->msi_map, d->hwirq,order_base_2 (nr_irqs)); -mutex_unlock (&port->map_lock); +mutex_unlock (&pcie->map_lock); }static const struct irq_domain_ops xilinx_msi_domain_ops = {
@@ -275,7 +275,7 @@ static struct msi_domain_info xilinx_msi_info = { .chip = &xilinx_msi_top_chip, }; -static int xilinx_allocate_msi_domains (struct xilinx_pcie_port *pcie) +static int xilinx_allocate_msi_domains (struct xilinx_pcie *pcie) {struct fwnode_handle *fwnode =dev_fwnode (pcie->dev);struct irq_domain *parent;
@@ -298,7 +298,7 @@ static int xilinx_allocate_msi_domains(struct xilinx_pcie_port *pcie)return 0 ; } -static void xilinx_free_msi_domains (struct xilinx_pcie_port *pcie) +static void xilinx_free_msi_domains (struct xilinx_pcie *pcie) {struct irq_domain *parent = pcie->msi_domain->parent;
@@ -342,13 +342,13 @@ static const struct irq_domain_ops intx_domain_ops = {*/ static irqreturn_t xilinx_pcie_intr_handler (int irq,void *data) { -struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data; -struct device *dev = port->dev; +struct xilinx_pcie *pcie = (struct xilinx_pcie *)data; +struct device *dev = pcie->dev;u32 val, mask, status;/* Read interrupt decode and mask registers */ - val =pcie_read (port,XILINX_PCIE_REG_IDR ); - mask =pcie_read (port,XILINX_PCIE_REG_IMR ); + val =pcie_read (pcie,XILINX_PCIE_REG_IDR ); + mask =pcie_read (pcie,XILINX_PCIE_REG_IMR ); status = val & mask;if (!status)
@@ -371,23 +371,23 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)if (status &XILINX_PCIE_INTR_CORRECTABLE ) {dev_warn (dev,"Correctable error message\n" ); -xilinx_pcie_clear_err_interrupts (port); +xilinx_pcie_clear_err_interrupts (pcie); }if (status &XILINX_PCIE_INTR_NONFATAL ) {dev_warn (dev,"Non fatal error message\n" ); -xilinx_pcie_clear_err_interrupts (port); +xilinx_pcie_clear_err_interrupts (pcie); }if (status &XILINX_PCIE_INTR_FATAL ) {dev_warn (dev,"Fatal error message\n" ); -xilinx_pcie_clear_err_interrupts (port); +xilinx_pcie_clear_err_interrupts (pcie); }if (status & (XILINX_PCIE_INTR_INTX |XILINX_PCIE_INTR_MSI )) {struct irq_domain *domain; - val =pcie_read (port,XILINX_PCIE_REG_RPIFR1 ); + val =pcie_read (pcie,XILINX_PCIE_REG_RPIFR1 );/* Check whether interrupt valid */ if (!(val &XILINX_PCIE_RPIFR1_INTR_VALID )) {
@@ -397,17 +397,17 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)/* Decode the IRQ number */ if (val &XILINX_PCIE_RPIFR1_MSI_INTR ) { - val =pcie_read (port,XILINX_PCIE_REG_RPIFR2 ) & + val =pcie_read (pcie,XILINX_PCIE_REG_RPIFR2 ) &XILINX_PCIE_RPIFR2_MSG_DATA ; - domain = port->msi_domain->parent; + domain = pcie->msi_domain->parent; }else { val = (val &XILINX_PCIE_RPIFR1_INTR_MASK ) >>XILINX_PCIE_RPIFR1_INTR_SHIFT ; - domain = port->leg_domain; + domain = pcie->leg_domain; }/* Clear interrupt FIFO register 1 */ -pcie_write (port,XILINX_PCIE_RPIFR1_ALL_MASK , +pcie_write (pcie,XILINX_PCIE_RPIFR1_ALL_MASK ,XILINX_PCIE_REG_RPIFR1 );generic_handle_domain_irq (domain, val);
@@ -442,20 +442,20 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) error:/* Clear the Interrupt Decode register */ -pcie_write (port, status,XILINX_PCIE_REG_IDR ); +pcie_write (pcie, status,XILINX_PCIE_REG_IDR );return IRQ_HANDLED ; }/** * xilinx_pcie_init_irq_domain - Initialize IRQ domain -* @port: PCIe port information +* @pcie: PCIe port information * * Return: '0' on success and error value on failure */ -static int xilinx_pcie_init_irq_domain (struct xilinx_pcie_port *port) +static int xilinx_pcie_init_irq_domain (struct xilinx_pcie *pcie) { -struct device *dev = port->dev; +struct device *dev = pcie->dev;struct device_node *pcie_intc_node;int ret;
@@ -466,25 +466,25 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)return -ENODEV ; } - port->leg_domain =irq_domain_add_linear (pcie_intc_node,PCI_NUM_INTX , + pcie->leg_domain =irq_domain_add_linear (pcie_intc_node,PCI_NUM_INTX , &intx_domain_ops, - port); + pcie);of_node_put (pcie_intc_node); -if (!port->leg_domain) { +if (!pcie->leg_domain) {dev_err (dev,"Failed to get a INTx IRQ domain\n" );return -ENODEV ; }/* Setup MSI */ if (IS_ENABLED (CONFIG_PCI_MSI )) { -phys_addr_t pa =ALIGN_DOWN (virt_to_phys (port),SZ_4K ); +phys_addr_t pa =ALIGN_DOWN (virt_to_phys (pcie),SZ_4K ); - ret =xilinx_allocate_msi_domains (port); + ret =xilinx_allocate_msi_domains (pcie);if (ret)return ret; -pcie_write (port,upper_32_bits (pa),XILINX_PCIE_REG_MSIBASE1 ); -pcie_write (port,lower_32_bits (pa),XILINX_PCIE_REG_MSIBASE2 ); +pcie_write (pcie,upper_32_bits (pa),XILINX_PCIE_REG_MSIBASE1 ); +pcie_write (pcie,lower_32_bits (pa),XILINX_PCIE_REG_MSIBASE2 ); }return 0 ;
@@ -492,44 +492,44 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)/** * xilinx_pcie_init_port - Initialize hardware -* @port: PCIe port information +* @pcie: PCIe port information */ -static void xilinx_pcie_init_port (struct xilinx_pcie_port *port) +static void xilinx_pcie_init_port (struct xilinx_pcie *pcie) { -struct device *dev = port->dev; +struct device *dev = pcie->dev; -if (xilinx_pcie_link_up (port)) +if (xilinx_pcie_link_up (pcie))dev_info (dev,"PCIe Link is UP\n" );else dev_info (dev,"PCIe Link is DOWN\n" );/* Disable all interrupts */ -pcie_write (port, ~XILINX_PCIE_IDR_ALL_MASK , +pcie_write (pcie, ~XILINX_PCIE_IDR_ALL_MASK ,XILINX_PCIE_REG_IMR );/* Clear pending interrupts */ -pcie_write (port,pcie_read (port,XILINX_PCIE_REG_IDR ) & +pcie_write (pcie,pcie_read (pcie,XILINX_PCIE_REG_IDR ) &XILINX_PCIE_IMR_ALL_MASK ,XILINX_PCIE_REG_IDR );/* Enable all interrupts we handle */ -pcie_write (port,XILINX_PCIE_IMR_ENABLE_MASK ,XILINX_PCIE_REG_IMR ); +pcie_write (pcie,XILINX_PCIE_IMR_ENABLE_MASK ,XILINX_PCIE_REG_IMR );/* Enable the Bridge enable bit */ -pcie_write (port,pcie_read (port,XILINX_PCIE_REG_RPSC ) | +pcie_write (pcie,pcie_read (pcie,XILINX_PCIE_REG_RPSC ) |XILINX_PCIE_REG_RPSC_BEN ,XILINX_PCIE_REG_RPSC ); }/** * xilinx_pcie_parse_dt - Parse Device tree -* @port: PCIe port information +* @pcie: PCIe port information * * Return: '0' on success and error value on failure */ -static int xilinx_pcie_parse_dt (struct xilinx_pcie_port *port) +static int xilinx_pcie_parse_dt (struct xilinx_pcie *pcie) { -struct device *dev = port->dev; +struct device *dev = pcie->dev;struct device_node *node = dev->of_node;struct resource regs;unsigned int irq;
@@ -541,14 +541,14 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)return err; } - port->reg_base =devm_pci_remap_cfg_resource (dev, ®s); -if (IS_ERR (port->reg_base)) -return PTR_ERR (port->reg_base); + pcie->reg_base =devm_pci_remap_cfg_resource (dev, ®s); +if (IS_ERR (pcie->reg_base)) +return PTR_ERR (pcie->reg_base); irq =irq_of_parse_and_map (node,0 ); err =devm_request_irq (dev, irq, xilinx_pcie_intr_handler,IRQF_SHARED |IRQF_NO_THREAD , -"xilinx-pcie" , port); +"xilinx-pcie" , pcie);if (err) {dev_err (dev,"unable to request irq %d\n" , irq);return err;
@@ -566,41 +566,41 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)static int xilinx_pcie_probe (struct platform_device *pdev) {struct device *dev = &pdev->dev; -struct xilinx_pcie_port *port; +struct xilinx_pcie *pcie;struct pci_host_bridge *bridge;int err;if (!dev->of_node)return -ENODEV ; - bridge =devm_pci_alloc_host_bridge (dev,sizeof (*port)); + bridge =devm_pci_alloc_host_bridge (dev,sizeof (*pcie));if (!bridge)return -ENODEV ; - port =pci_host_bridge_priv (bridge); -mutex_init (&port->map_lock); - port->dev = dev; + pcie =pci_host_bridge_priv (bridge); +mutex_init (&pcie->map_lock); + pcie->dev = dev; - err =xilinx_pcie_parse_dt (port); + err =xilinx_pcie_parse_dt (pcie);if (err) {dev_err (dev,"Parsing DT failed\n" );return err; } -xilinx_pcie_init_port (port); +xilinx_pcie_init_port (pcie); - err =xilinx_pcie_init_irq_domain (port); + err =xilinx_pcie_init_irq_domain (pcie);if (err) {dev_err (dev,"Failed creating IRQ Domain\n" );return err; } - bridge->sysdata = port; + bridge->sysdata = pcie; bridge->ops = &xilinx_pcie_ops; err =pci_host_probe (bridge);if (err) -xilinx_free_msi_domains (port); +xilinx_free_msi_domains (pcie);return err; }
Signature · 1 line
2.25.1
PATCH 6/6 PCI: mediatek-gen3: Rename struct mtk_pcie_port to mtk_gen_pcie
In reply to Fan FeiRename struct mtk_pcie_port to mtk_gen3_pcie to match the convention of <driver>_pcie. No functional change intended.
Signed-off-by Fan Fei <[email protected]>
--- drivers/pci/controller/pcie-mediatek-gen3.c | 370 ++++++++++---------- 1 file changed, 185 insertions(+), 185 deletions(-)
drivers/pci/controller/pcie-mediatek-gen3.c +185 -185
@@ -129,7 +129,7 @@ struct mtk_msi_set {* @lock: lock protecting IRQ bit map * @msi_irq_in_use: bit map for assigned MSI IRQ */ -struct mtk_pcie_port { +struct mtk_gen3_pcie {struct device *dev;void __iomem *base;phys_addr_t reg_base;
@@ -162,7 +162,7 @@ struct mtk_pcie_port {static void mtk_pcie_config_tlp_header (struct pci_bus *bus,unsigned int devfn,int where,int size) { -struct mtk_pcie_port *port = bus->sysdata; +struct mtk_gen3_pcie *pcie = bus->sysdata;int bytes;u32 val;
@@ -171,15 +171,15 @@ static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn, val =PCIE_CFG_FORCE_BYTE_EN |PCIE_CFG_BYTE_EN (bytes) |PCIE_CFG_HEADER (bus->number, devfn); -writel_relaxed (val, port->base +PCIE_CFGNUM_REG ); +writel_relaxed (val, pcie->base +PCIE_CFGNUM_REG ); }static void __iomem *mtk_pcie_map_bus (struct pci_bus *bus,unsigned int devfn,int where) { -struct mtk_pcie_port *port = bus->sysdata; +struct mtk_gen3_pcie *pcie = bus->sysdata; -return port->base +PCIE_CFG_OFFSET_ADDR + where; +return pcie->base +PCIE_CFG_OFFSET_ADDR + where; } static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
@@ -207,7 +207,7 @@ static struct pci_ops mtk_pcie_ops = { .write = mtk_pcie_config_write, }; -static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port, +static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, resource_size_t cpu_addr, resource_size_t pci_addr, resource_size_t size,
@@ -217,12 +217,12 @@ static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port,u32 val;if (num >=PCIE_MAX_TRANS_TABLES ) { -dev_err (port->dev,"not enough translate table for addr: %#llx, limited to [%d]\n" , +dev_err (pcie->dev,"not enough translate table for addr: %#llx, limited to [%d]\n" , (unsigned long long )cpu_addr,PCIE_MAX_TRANS_TABLES );return -ENODEV ; } - table = port->base +PCIE_TRANS_TABLE_BASE_REG + + table = pcie->base +PCIE_TRANS_TABLE_BASE_REG + num *PCIE_ATR_TLB_SET_OFFSET ; writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1),
@@ -244,63 +244,63 @@ static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port,return 0 ; } -static void mtk_pcie_enable_msi (struct mtk_pcie_port *port) +static void mtk_pcie_enable_msi (struct mtk_gen3_pcie *pcie) {int i;u32 val;for (i =0 ; i <PCIE_MSI_SET_NUM ; i++) { -struct mtk_msi_set *msi_set = &port->msi_sets[i]; +struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; - msi_set->base = port->base +PCIE_MSI_SET_BASE_REG + + msi_set->base = pcie->base +PCIE_MSI_SET_BASE_REG + i *PCIE_MSI_SET_OFFSET ; - msi_set->msg_addr = port->reg_base +PCIE_MSI_SET_BASE_REG + + msi_set->msg_addr = pcie->reg_base +PCIE_MSI_SET_BASE_REG + i *PCIE_MSI_SET_OFFSET ;/* Configure the MSI capture address */ writel_relaxed (lower_32_bits (msi_set->msg_addr), msi_set->base);writel_relaxed (upper_32_bits (msi_set->msg_addr), - port->base +PCIE_MSI_SET_ADDR_HI_BASE + + pcie->base +PCIE_MSI_SET_ADDR_HI_BASE + i *PCIE_MSI_SET_ADDR_HI_OFFSET ); } - val =readl_relaxed (port->base +PCIE_MSI_SET_ENABLE_REG ); + val =readl_relaxed (pcie->base +PCIE_MSI_SET_ENABLE_REG ); val |=PCIE_MSI_SET_ENABLE ; -writel_relaxed (val, port->base +PCIE_MSI_SET_ENABLE_REG ); +writel_relaxed (val, pcie->base +PCIE_MSI_SET_ENABLE_REG ); - val =readl_relaxed (port->base +PCIE_INT_ENABLE_REG ); + val =readl_relaxed (pcie->base +PCIE_INT_ENABLE_REG ); val |=PCIE_MSI_ENABLE ; -writel_relaxed (val, port->base +PCIE_INT_ENABLE_REG ); +writel_relaxed (val, pcie->base +PCIE_INT_ENABLE_REG ); } -static int mtk_pcie_startup_port (struct mtk_pcie_port *port) +static int mtk_pcie_startup_port (struct mtk_gen3_pcie *pcie) {struct resource_entry *entry; -struct pci_host_bridge *host =pci_host_bridge_from_priv (port); +struct pci_host_bridge *host =pci_host_bridge_from_priv (pcie);unsigned int table_index =0 ;int err;u32 val;/* Set as RC mode */ - val =readl_relaxed (port->base +PCIE_SETTING_REG ); + val =readl_relaxed (pcie->base +PCIE_SETTING_REG ); val |=PCIE_RC_MODE ; -writel_relaxed (val, port->base +PCIE_SETTING_REG ); +writel_relaxed (val, pcie->base +PCIE_SETTING_REG );/* Set class code */ - val =readl_relaxed (port->base +PCIE_PCI_IDS_1 ); + val =readl_relaxed (pcie->base +PCIE_PCI_IDS_1 ); val &= ~GENMASK (31 ,8 ); val |=PCI_CLASS (PCI_CLASS_BRIDGE_PCI <<8 ); -writel_relaxed (val, port->base +PCIE_PCI_IDS_1 ); +writel_relaxed (val, pcie->base +PCIE_PCI_IDS_1 );/* Mask all INTx interrupts */ - val =readl_relaxed (port->base +PCIE_INT_ENABLE_REG ); + val =readl_relaxed (pcie->base +PCIE_INT_ENABLE_REG ); val &= ~PCIE_INTX_ENABLE ; -writel_relaxed (val, port->base +PCIE_INT_ENABLE_REG ); +writel_relaxed (val, pcie->base +PCIE_INT_ENABLE_REG );/* Assert all reset signals */ - val =readl_relaxed (port->base +PCIE_RST_CTRL_REG ); + val =readl_relaxed (pcie->base +PCIE_RST_CTRL_REG ); val |=PCIE_MAC_RSTB |PCIE_PHY_RSTB |PCIE_BRG_RSTB |PCIE_PE_RSTB ; -writel_relaxed (val, port->base +PCIE_RST_CTRL_REG ); +writel_relaxed (val, pcie->base +PCIE_RST_CTRL_REG );/* * Described in PCIe CEM specification setctions 2.2 (PERST# Signal)
@@ -312,19 +312,19 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)/* De-assert reset signals */ val &= ~(PCIE_MAC_RSTB |PCIE_PHY_RSTB |PCIE_BRG_RSTB |PCIE_PE_RSTB ); -writel_relaxed (val, port->base +PCIE_RST_CTRL_REG ); +writel_relaxed (val, pcie->base +PCIE_RST_CTRL_REG );/* Check if the link is up or not */ - err =readl_poll_timeout (port->base +PCIE_LINK_STATUS_REG , val, + err =readl_poll_timeout (pcie->base +PCIE_LINK_STATUS_REG , val, !!(val &PCIE_PORT_LINKUP ),20 ,PCI_PM_D3COLD_WAIT *USEC_PER_MSEC );if (err) { - val =readl_relaxed (port->base +PCIE_LTSSM_STATUS_REG ); -dev_err (port->dev,"PCIe link down, ltssm reg val: %#x\n" , val); + val =readl_relaxed (pcie->base +PCIE_LTSSM_STATUS_REG ); +dev_err (pcie->dev,"PCIe link down, ltssm reg val: %#x\n" , val);return err; } -mtk_pcie_enable_msi (port); +mtk_pcie_enable_msi (pcie);/* Set PCIe translation windows */ resource_list_for_each_entry (entry, &host->windows) {
@@ -347,12 +347,12 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port) pci_addr = res->start - entry->offset; size =resource_size (res); - err =mtk_pcie_set_trans_table (port, cpu_addr, pci_addr, size, + err =mtk_pcie_set_trans_table (pcie, cpu_addr, pci_addr, size, type, table_index);if (err)return err; -dev_dbg (port->dev,"set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n" , +dev_dbg (pcie->dev,"set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n" , range_type, table_index, (unsigned long long )cpu_addr, (unsigned long long )pci_addr, (unsigned long long )size);
@@ -396,7 +396,7 @@ static struct msi_domain_info mtk_msi_domain_info = {static void mtk_compose_msi_msg (struct irq_data *data,struct msi_msg *msg) {struct mtk_msi_set *msi_set =irq_data_get_irq_chip_data (data); -struct mtk_pcie_port *port = data->domain->host_data; +struct mtk_gen3_pcie *pcie = data->domain->host_data;unsigned long hwirq; hwirq = data->hwirq %PCIE_MSI_IRQS_PER_SET ;
@@ -404,7 +404,7 @@ static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) msg->address_hi =upper_32_bits (msi_set->msg_addr); msg->address_lo =lower_32_bits (msi_set->msg_addr); msg->data = hwirq; -dev_dbg (port->dev,"msi#%#lx address_hi %#x address_lo %#x data %d\n" , +dev_dbg (pcie->dev,"msi#%#lx address_hi %#x address_lo %#x data %d\n" , hwirq, msg->address_hi, msg->address_lo, msg->data); }
@@ -421,33 +421,33 @@ static void mtk_msi_bottom_irq_ack(struct irq_data *data)static void mtk_msi_bottom_irq_mask (struct irq_data *data) {struct mtk_msi_set *msi_set =irq_data_get_irq_chip_data (data); -struct mtk_pcie_port *port = data->domain->host_data; +struct mtk_gen3_pcie *pcie = data->domain->host_data;unsigned long hwirq, flags;u32 val; hwirq = data->hwirq %PCIE_MSI_IRQS_PER_SET ; -raw_spin_lock_irqsave (&port->irq_lock, flags); +raw_spin_lock_irqsave (&pcie->irq_lock, flags); val =readl_relaxed (msi_set->base +PCIE_MSI_SET_ENABLE_OFFSET ); val &= ~BIT (hwirq);writel_relaxed (val, msi_set->base +PCIE_MSI_SET_ENABLE_OFFSET ); -raw_spin_unlock_irqrestore (&port->irq_lock, flags); +raw_spin_unlock_irqrestore (&pcie->irq_lock, flags); }static void mtk_msi_bottom_irq_unmask (struct irq_data *data) {struct mtk_msi_set *msi_set =irq_data_get_irq_chip_data (data); -struct mtk_pcie_port *port = data->domain->host_data; +struct mtk_gen3_pcie *pcie = data->domain->host_data;unsigned long hwirq, flags;u32 val; hwirq = data->hwirq %PCIE_MSI_IRQS_PER_SET ; -raw_spin_lock_irqsave (&port->irq_lock, flags); +raw_spin_lock_irqsave (&pcie->irq_lock, flags); val =readl_relaxed (msi_set->base +PCIE_MSI_SET_ENABLE_OFFSET ); val |=BIT (hwirq);writel_relaxed (val, msi_set->base +PCIE_MSI_SET_ENABLE_OFFSET ); -raw_spin_unlock_irqrestore (&port->irq_lock, flags); +raw_spin_unlock_irqrestore (&pcie->irq_lock, flags); }static struct irq_chip mtk_msi_bottom_irq_chip = {
@@ -463,22 +463,22 @@ static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { - struct mtk_pcie_port *port = domain->host_data; + struct mtk_gen3_pcie *pcie = domain->host_data;struct mtk_msi_set *msi_set;int i, hwirq, set_idx; -mutex_lock (&port->lock); +mutex_lock (&pcie->lock); - hwirq =bitmap_find_free_region (port->msi_irq_in_use,PCIE_MSI_IRQS_NUM , + hwirq =bitmap_find_free_region (pcie->msi_irq_in_use,PCIE_MSI_IRQS_NUM ,order_base_2 (nr_irqs)); -mutex_unlock (&port->lock); +mutex_unlock (&pcie->lock);if (hwirq <0 )return -ENOSPC ; set_idx = hwirq /PCIE_MSI_IRQS_PER_SET ; - msi_set = &port->msi_sets[set_idx]; + msi_set = &pcie->msi_sets[set_idx]; for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, hwirq + i,
@@ -491,15 +491,15 @@ static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain,static void mtk_msi_bottom_domain_free (struct irq_domain *domain,unsigned int virq,unsigned int nr_irqs) { -struct mtk_pcie_port *port = domain->host_data; +struct mtk_gen3_pcie *pcie = domain->host_data;struct irq_data *data =irq_domain_get_irq_data (domain, virq); -mutex_lock (&port->lock); +mutex_lock (&pcie->lock); -bitmap_release_region (port->msi_irq_in_use, data->hwirq, +bitmap_release_region (pcie->msi_irq_in_use, data->hwirq,order_base_2 (nr_irqs)); -mutex_unlock (&port->lock); +mutex_unlock (&pcie->lock);irq_domain_free_irqs_common (domain, virq, nr_irqs); }
@@ -511,28 +511,28 @@ static const struct irq_domain_ops mtk_msi_bottom_domain_ops = {static void mtk_intx_mask (struct irq_data *data) { -struct mtk_pcie_port *port =irq_data_get_irq_chip_data (data); +struct mtk_gen3_pcie *pcie =irq_data_get_irq_chip_data (data);unsigned long flags;u32 val; -raw_spin_lock_irqsave (&port->irq_lock, flags); - val =readl_relaxed (port->base +PCIE_INT_ENABLE_REG ); +raw_spin_lock_irqsave (&pcie->irq_lock, flags); + val =readl_relaxed (pcie->base +PCIE_INT_ENABLE_REG ); val &= ~BIT (data->hwirq +PCIE_INTX_SHIFT ); -writel_relaxed (val, port->base +PCIE_INT_ENABLE_REG ); -raw_spin_unlock_irqrestore (&port->irq_lock, flags); +writel_relaxed (val, pcie->base +PCIE_INT_ENABLE_REG ); +raw_spin_unlock_irqrestore (&pcie->irq_lock, flags); }static void mtk_intx_unmask (struct irq_data *data) { -struct mtk_pcie_port *port =irq_data_get_irq_chip_data (data); +struct mtk_gen3_pcie *pcie =irq_data_get_irq_chip_data (data);unsigned long flags;u32 val; -raw_spin_lock_irqsave (&port->irq_lock, flags); - val =readl_relaxed (port->base +PCIE_INT_ENABLE_REG ); +raw_spin_lock_irqsave (&pcie->irq_lock, flags); + val =readl_relaxed (pcie->base +PCIE_INT_ENABLE_REG ); val |=BIT (data->hwirq +PCIE_INTX_SHIFT ); -writel_relaxed (val, port->base +PCIE_INT_ENABLE_REG ); -raw_spin_unlock_irqrestore (&port->irq_lock, flags); +writel_relaxed (val, pcie->base +PCIE_INT_ENABLE_REG ); +raw_spin_unlock_irqrestore (&pcie->irq_lock, flags); }/**
@@ -545,11 +545,11 @@ static void mtk_intx_unmask(struct irq_data *data)*/ static void mtk_intx_eoi (struct irq_data *data) { -struct mtk_pcie_port *port =irq_data_get_irq_chip_data (data); +struct mtk_gen3_pcie *pcie =irq_data_get_irq_chip_data (data);unsigned long hwirq; hwirq = data->hwirq +PCIE_INTX_SHIFT ; -writel_relaxed (BIT (hwirq), port->base +PCIE_INT_STATUS_REG ); +writel_relaxed (BIT (hwirq), pcie->base +PCIE_INT_STATUS_REG ); }static struct irq_chip mtk_intx_irq_chip = {
@@ -573,13 +573,13 @@ static const struct irq_domain_ops intx_domain_ops = { .map = mtk_pcie_intx_map, }; -static int mtk_pcie_init_irq_domains (struct mtk_pcie_port *port) +static int mtk_pcie_init_irq_domains (struct mtk_gen3_pcie *pcie) { -struct device *dev = port->dev; +struct device *dev = pcie->dev;struct device_node *intc_node, *node = dev->of_node;int ret; -raw_spin_lock_init (&port->irq_lock); +raw_spin_lock_init (&pcie->irq_lock);/* Setup INTx */ intc_node =of_get_child_by_name (node,"interrupt-controller" );
@@ -588,28 +588,28 @@ static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port)return -ENODEV ; } - port->intx_domain =irq_domain_add_linear (intc_node,PCI_NUM_INTX , - &intx_domain_ops, port); -if (!port->intx_domain) { + pcie->intx_domain =irq_domain_add_linear (intc_node,PCI_NUM_INTX , + &intx_domain_ops, pcie); +if (!pcie->intx_domain) {dev_err (dev,"failed to create INTx IRQ domain\n" );return -ENODEV ; }/* Setup MSI */ -mutex_init (&port->lock); +mutex_init (&pcie->lock); - port->msi_bottom_domain =irq_domain_add_linear (node,PCIE_MSI_IRQS_NUM , - &mtk_msi_bottom_domain_ops, port); -if (!port->msi_bottom_domain) { + pcie->msi_bottom_domain =irq_domain_add_linear (node,PCIE_MSI_IRQS_NUM , + &mtk_msi_bottom_domain_ops, pcie); +if (!pcie->msi_bottom_domain) {dev_err (dev,"failed to create MSI bottom domain\n" ); ret = -ENODEV ; goto err_msi_bottom_domain; } - port->msi_domain =pci_msi_create_irq_domain (dev->fwnode, + pcie->msi_domain =pci_msi_create_irq_domain (dev->fwnode, &mtk_msi_domain_info, - port->msi_bottom_domain); -if (!port->msi_domain) { + pcie->msi_bottom_domain); +if (!pcie->msi_domain) {dev_err (dev,"failed to create MSI domain\n" ); ret = -ENODEV ; goto err_msi_domain;
@@ -618,32 +618,32 @@ static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port)return 0 ; err_msi_domain: -irq_domain_remove (port->msi_bottom_domain); +irq_domain_remove (pcie->msi_bottom_domain); err_msi_bottom_domain: -irq_domain_remove (port->intx_domain); +irq_domain_remove (pcie->intx_domain);return ret; } -static void mtk_pcie_irq_teardown (struct mtk_pcie_port *port) +static void mtk_pcie_irq_teardown (struct mtk_gen3_pcie *pcie) { -irq_set_chained_handler_and_data (port->irq,NULL ,NULL ); +irq_set_chained_handler_and_data (pcie->irq,NULL ,NULL ); -if (port->intx_domain) -irq_domain_remove (port->intx_domain); +if (pcie->intx_domain) +irq_domain_remove (pcie->intx_domain); -if (port->msi_domain) -irq_domain_remove (port->msi_domain); +if (pcie->msi_domain) +irq_domain_remove (pcie->msi_domain); -if (port->msi_bottom_domain) -irq_domain_remove (port->msi_bottom_domain); +if (pcie->msi_bottom_domain) +irq_domain_remove (pcie->msi_bottom_domain); -irq_dispose_mapping (port->irq); +irq_dispose_mapping (pcie->irq); } -static void mtk_pcie_msi_handler (struct mtk_pcie_port *port,int set_idx) +static void mtk_pcie_msi_handler (struct mtk_gen3_pcie *pcie,int set_idx) { -struct mtk_msi_set *msi_set = &port->msi_sets[set_idx]; +struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx];unsigned long msi_enable, msi_status;irq_hw_number_t bit, hwirq;
@@ -658,59 +658,59 @@ static void mtk_pcie_msi_handler(struct mtk_pcie_port *port, int set_idx)for_each_set_bit (bit, &msi_status,PCIE_MSI_IRQS_PER_SET ) { hwirq = bit + set_idx *PCIE_MSI_IRQS_PER_SET ; -generic_handle_domain_irq (port->msi_bottom_domain, hwirq); +generic_handle_domain_irq (pcie->msi_bottom_domain, hwirq); } }while (true); }static void mtk_pcie_irq_handler (struct irq_desc *desc) { -struct mtk_pcie_port *port =irq_desc_get_handler_data (desc); +struct mtk_gen3_pcie *pcie =irq_desc_get_handler_data (desc);struct irq_chip *irqchip =irq_desc_get_chip (desc);unsigned long status;irq_hw_number_t irq_bit =PCIE_INTX_SHIFT ;chained_irq_enter (irqchip, desc); - status =readl_relaxed (port->base +PCIE_INT_STATUS_REG ); + status =readl_relaxed (pcie->base +PCIE_INT_STATUS_REG );for_each_set_bit_from (irq_bit, &status,PCI_NUM_INTX +PCIE_INTX_SHIFT ) -generic_handle_domain_irq (port->intx_domain, +generic_handle_domain_irq (pcie->intx_domain, irq_bit -PCIE_INTX_SHIFT ); irq_bit =PCIE_MSI_SHIFT ;for_each_set_bit_from (irq_bit, &status,PCIE_MSI_SET_NUM +PCIE_MSI_SHIFT ) { -mtk_pcie_msi_handler (port, irq_bit -PCIE_MSI_SHIFT ); +mtk_pcie_msi_handler (pcie, irq_bit -PCIE_MSI_SHIFT ); -writel_relaxed (BIT (irq_bit), port->base +PCIE_INT_STATUS_REG ); +writel_relaxed (BIT (irq_bit), pcie->base +PCIE_INT_STATUS_REG ); }chained_irq_exit (irqchip, desc); } -static int mtk_pcie_setup_irq (struct mtk_pcie_port *port) +static int mtk_pcie_setup_irq (struct mtk_gen3_pcie *pcie) { -struct device *dev = port->dev; +struct device *dev = pcie->dev;struct platform_device *pdev =to_platform_device (dev);int err; - err =mtk_pcie_init_irq_domains (port); + err =mtk_pcie_init_irq_domains (pcie);if (err)return err; - port->irq =platform_get_irq (pdev,0 ); -if (port->irq <0 ) -return port->irq; + pcie->irq =platform_get_irq (pdev,0 ); +if (pcie->irq <0 ) +return pcie->irq; -irq_set_chained_handler_and_data (port->irq, mtk_pcie_irq_handler, port); +irq_set_chained_handler_and_data (pcie->irq, mtk_pcie_irq_handler, pcie);return 0 ; } -static int mtk_pcie_parse_port (struct mtk_pcie_port *port) +static int mtk_pcie_parse_port (struct mtk_gen3_pcie *pcie) { -struct device *dev = port->dev; +struct device *dev = pcie->dev;struct platform_device *pdev =to_platform_device (dev);struct resource *regs;int ret;
@@ -718,77 +718,77 @@ static int mtk_pcie_parse_port(struct mtk_pcie_port *port) regs =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"pcie-mac" );if (!regs)return -EINVAL ; - port->base =devm_ioremap_resource (dev, regs); -if (IS_ERR (port->base)) { + pcie->base =devm_ioremap_resource (dev, regs); +if (IS_ERR (pcie->base)) {dev_err (dev,"failed to map register base\n" ); -return PTR_ERR (port->base); +return PTR_ERR (pcie->base); } - port->reg_base = regs->start; + pcie->reg_base = regs->start; - port->phy_reset =devm_reset_control_get_optional_exclusive (dev,"phy" ); -if (IS_ERR (port->phy_reset)) { - ret =PTR_ERR (port->phy_reset); + pcie->phy_reset =devm_reset_control_get_optional_exclusive (dev,"phy" ); +if (IS_ERR (pcie->phy_reset)) { + ret =PTR_ERR (pcie->phy_reset);if (ret != -EPROBE_DEFER )dev_err (dev,"failed to get PHY reset\n" );return ret; } - port->mac_reset =devm_reset_control_get_optional_exclusive (dev,"mac" ); -if (IS_ERR (port->mac_reset)) { - ret =PTR_ERR (port->mac_reset); + pcie->mac_reset =devm_reset_control_get_optional_exclusive (dev,"mac" ); +if (IS_ERR (pcie->mac_reset)) { + ret =PTR_ERR (pcie->mac_reset);if (ret != -EPROBE_DEFER )dev_err (dev,"failed to get MAC reset\n" );return ret; } - port->phy =devm_phy_optional_get (dev,"pcie-phy" ); -if (IS_ERR (port->phy)) { - ret =PTR_ERR (port->phy); + pcie->phy =devm_phy_optional_get (dev,"pcie-phy" ); +if (IS_ERR (pcie->phy)) { + ret =PTR_ERR (pcie->phy);if (ret != -EPROBE_DEFER )dev_err (dev,"failed to get PHY\n" );return ret; } - port->num_clks =devm_clk_bulk_get_all (dev, &port->clks); -if (port->num_clks <0 ) { + pcie->num_clks =devm_clk_bulk_get_all (dev, &pcie->clks); +if (pcie->num_clks <0 ) {dev_err (dev,"failed to get clocks\n" ); -return port->num_clks; +return pcie->num_clks; }return 0 ; } -static int mtk_pcie_power_up (struct mtk_pcie_port *port) +static int mtk_pcie_power_up (struct mtk_gen3_pcie *pcie) { -struct device *dev = port->dev; +struct device *dev = pcie->dev;int err;/* PHY power on and enable pipe clock */ -reset_control_deassert (port->phy_reset); +reset_control_deassert (pcie->phy_reset); - err =phy_init (port->phy); + err =phy_init (pcie->phy);if (err) {dev_err (dev,"failed to initialize PHY\n" ); goto err_phy_init; } - err =phy_power_on (port->phy); + err =phy_power_on (pcie->phy);if (err) {dev_err (dev,"failed to power on PHY\n" ); goto err_phy_on; }/* MAC power on and enable transaction layer clocks */ -reset_control_deassert (port->mac_reset); +reset_control_deassert (pcie->mac_reset);pm_runtime_enable (dev);pm_runtime_get_sync (dev); - err =clk_bulk_prepare_enable (port->num_clks, port->clks); + err =clk_bulk_prepare_enable (pcie->num_clks, pcie->clks);if (err) {dev_err (dev,"failed to enable clocks\n" ); goto err_clk_init;
@@ -799,55 +799,55 @@ static int mtk_pcie_power_up(struct mtk_pcie_port *port) err_clk_init:pm_runtime_put_sync (dev);pm_runtime_disable (dev); -reset_control_assert (port->mac_reset); -phy_power_off (port->phy); +reset_control_assert (pcie->mac_reset); +phy_power_off (pcie->phy); err_phy_on: -phy_exit (port->phy); +phy_exit (pcie->phy); err_phy_init: -reset_control_assert (port->phy_reset); +reset_control_assert (pcie->phy_reset);return err; } -static void mtk_pcie_power_down (struct mtk_pcie_port *port) +static void mtk_pcie_power_down (struct mtk_gen3_pcie *pcie) { -clk_bulk_disable_unprepare (port->num_clks, port->clks); +clk_bulk_disable_unprepare (pcie->num_clks, pcie->clks); -pm_runtime_put_sync (port->dev); -pm_runtime_disable (port->dev); -reset_control_assert (port->mac_reset); +pm_runtime_put_sync (pcie->dev); +pm_runtime_disable (pcie->dev); +reset_control_assert (pcie->mac_reset); -phy_power_off (port->phy); -phy_exit (port->phy); -reset_control_assert (port->phy_reset); +phy_power_off (pcie->phy); +phy_exit (pcie->phy); +reset_control_assert (pcie->phy_reset); } -static int mtk_pcie_setup (struct mtk_pcie_port *port) +static int mtk_pcie_setup (struct mtk_gen3_pcie *pcie) {int err; - err =mtk_pcie_parse_port (port); + err =mtk_pcie_parse_port (pcie);if (err)return err;/* Don't touch the hardware registers before power up */ - err =mtk_pcie_power_up (port); + err =mtk_pcie_power_up (pcie);if (err)return err;/* Try link up */ - err =mtk_pcie_startup_port (port); + err =mtk_pcie_startup_port (pcie);if (err) goto err_setup; - err =mtk_pcie_setup_irq (port); + err =mtk_pcie_setup_irq (pcie);if (err) goto err_setup;return 0 ; err_setup: -mtk_pcie_power_down (port); +mtk_pcie_power_down (pcie);return err; }
@@ -855,30 +855,30 @@ static int mtk_pcie_setup(struct mtk_pcie_port *port)static int mtk_pcie_probe (struct platform_device *pdev) {struct device *dev = &pdev->dev; -struct mtk_pcie_port *port; +struct mtk_gen3_pcie *pcie;struct pci_host_bridge *host;int err; - host =devm_pci_alloc_host_bridge (dev,sizeof (*port)); + host =devm_pci_alloc_host_bridge (dev,sizeof (*pcie));if (!host)return -ENOMEM ; - port =pci_host_bridge_priv (host); + pcie =pci_host_bridge_priv (host); - port->dev = dev; -platform_set_drvdata (pdev, port); + pcie->dev = dev; +platform_set_drvdata (pdev, pcie); - err =mtk_pcie_setup (port); + err =mtk_pcie_setup (pcie);if (err)return err; host->ops = &mtk_pcie_ops; - host->sysdata = port; + host->sysdata = pcie; err =pci_host_probe (host);if (err) { -mtk_pcie_irq_teardown (port); -mtk_pcie_power_down (port); +mtk_pcie_irq_teardown (pcie); +mtk_pcie_power_down (pcie);return err; }
@@ -887,66 +887,66 @@ static int mtk_pcie_probe(struct platform_device *pdev)static int mtk_pcie_remove (struct platform_device *pdev) { -struct mtk_pcie_port *port =platform_get_drvdata (pdev); -struct pci_host_bridge *host =pci_host_bridge_from_priv (port); +struct mtk_gen3_pcie *pcie =platform_get_drvdata (pdev); +struct pci_host_bridge *host =pci_host_bridge_from_priv (pcie);pci_lock_rescan_remove ();pci_stop_root_bus (host->bus);pci_remove_root_bus (host->bus);pci_unlock_rescan_remove (); -mtk_pcie_irq_teardown (port); -mtk_pcie_power_down (port); +mtk_pcie_irq_teardown (pcie); +mtk_pcie_power_down (pcie);return 0 ; } -static void __maybe_unused mtk_pcie_irq_save (struct mtk_pcie_port *port) +static void __maybe_unused mtk_pcie_irq_save (struct mtk_gen3_pcie *pcie) {int i; -raw_spin_lock (&port->irq_lock); +raw_spin_lock (&pcie->irq_lock); - port->saved_irq_state =readl_relaxed (port->base +PCIE_INT_ENABLE_REG ); + pcie->saved_irq_state =readl_relaxed (pcie->base +PCIE_INT_ENABLE_REG );for (i =0 ; i <PCIE_MSI_SET_NUM ; i++) { -struct mtk_msi_set *msi_set = &port->msi_sets[i]; +struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; msi_set->saved_irq_state =readl_relaxed (msi_set->base +PCIE_MSI_SET_ENABLE_OFFSET ); } -raw_spin_unlock (&port->irq_lock); +raw_spin_unlock (&pcie->irq_lock); } -static void __maybe_unused mtk_pcie_irq_restore (struct mtk_pcie_port *port) +static void __maybe_unused mtk_pcie_irq_restore (struct mtk_gen3_pcie *pcie) {int i; -raw_spin_lock (&port->irq_lock); +raw_spin_lock (&pcie->irq_lock); -writel_relaxed (port->saved_irq_state, port->base +PCIE_INT_ENABLE_REG ); +writel_relaxed (pcie->saved_irq_state, pcie->base +PCIE_INT_ENABLE_REG );for (i =0 ; i <PCIE_MSI_SET_NUM ; i++) { -struct mtk_msi_set *msi_set = &port->msi_sets[i]; +struct mtk_msi_set *msi_set = &pcie->msi_sets[i];writel_relaxed (msi_set->saved_irq_state, msi_set->base +PCIE_MSI_SET_ENABLE_OFFSET ); } -raw_spin_unlock (&port->irq_lock); +raw_spin_unlock (&pcie->irq_lock); } -static int __maybe_unused mtk_pcie_turn_off_link (struct mtk_pcie_port *port) +static int __maybe_unused mtk_pcie_turn_off_link (struct mtk_gen3_pcie *pcie) {u32 val; - val =readl_relaxed (port->base +PCIE_ICMD_PM_REG ); + val =readl_relaxed (pcie->base +PCIE_ICMD_PM_REG ); val |=PCIE_TURN_OFF_LINK ; -writel_relaxed (val, port->base +PCIE_ICMD_PM_REG ); +writel_relaxed (val, pcie->base +PCIE_ICMD_PM_REG );/* Check the link is L2 */ -return readl_poll_timeout (port->base +PCIE_LTSSM_STATUS_REG , val, +return readl_poll_timeout (pcie->base +PCIE_LTSSM_STATUS_REG , val, (PCIE_LTSSM_STATE (val) ==PCIE_LTSSM_STATE_L2_IDLE ),20 ,50 *USEC_PER_MSEC );
@@ -954,46 +954,46 @@ static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port)static int __maybe_unused mtk_pcie_suspend_noirq (struct device *dev) { -struct mtk_pcie_port *port =dev_get_drvdata (dev); +struct mtk_gen3_pcie *pcie =dev_get_drvdata (dev);int err;u32 val;/* Trigger link to L2 state */ - err =mtk_pcie_turn_off_link (port); + err =mtk_pcie_turn_off_link (pcie);if (err) { -dev_err (port->dev,"cannot enter L2 state\n" ); +dev_err (pcie->dev,"cannot enter L2 state\n" );return err; }/* Pull down the PERST# pin */ - val =readl_relaxed (port->base +PCIE_RST_CTRL_REG ); + val =readl_relaxed (pcie->base +PCIE_RST_CTRL_REG ); val |=PCIE_PE_RSTB ; -writel_relaxed (val, port->base +PCIE_RST_CTRL_REG ); +writel_relaxed (val, pcie->base +PCIE_RST_CTRL_REG ); -dev_dbg (port->dev,"entered L2 states successfully" ); +dev_dbg (pcie->dev,"entered L2 states successfully" ); -mtk_pcie_irq_save (port); -mtk_pcie_power_down (port); +mtk_pcie_irq_save (pcie); +mtk_pcie_power_down (pcie);return 0 ; }static int __maybe_unused mtk_pcie_resume_noirq (struct device *dev) { -struct mtk_pcie_port *port =dev_get_drvdata (dev); +struct mtk_gen3_pcie *pcie =dev_get_drvdata (dev);int err; - err =mtk_pcie_power_up (port); + err =mtk_pcie_power_up (pcie);if (err)return err; - err =mtk_pcie_startup_port (port); + err =mtk_pcie_startup_port (pcie);if (err) { -mtk_pcie_power_down (port); +mtk_pcie_power_down (pcie);return err; } -mtk_pcie_irq_restore (port); +mtk_pcie_irq_restore (pcie);return 0 ; }
Signature · 1 line
2.25.1