Add Sunplus SP7021 SoC Support

drivers/reset/reset-sunplus.c new file +14 -0

new file mode 100644
index 000000000..a1d88dbaf
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * SP7021 reset driver
+ *
+ * Copyright (C) Sunplus Technology Co., Ltd.
+ *       All rights reserved.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>

drivers/reset/reset-sunplus.c new file +33 -0

+	sp_reset_assert(&sp_reset->rcdev, 0);
+	sp_reset_deassert(&sp_reset->rcdev, 0);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block sp_restart_nb = {
+	.notifier_call = sp_restart,
+	.priority = 192,
+};
+
+static const struct reset_control_ops sp_reset_ops = {
+	.assert   = sp_reset_assert,
+	.deassert = sp_reset_deassert,
+	.status   = sp_reset_status,
+};
+
+static const struct of_device_id sp_reset_dt_ids[] = {
+	{.compatible = "sunplus,sp7021-reset",},
+	{ /* sentinel */ },
+};
+
+static int sp_reset_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *membase;
+	struct resource *res;
+
+	sp_reset = devm_kzalloc(&pdev->dev, sizeof(*sp_reset), GFP_KERNEL);
+	if (!sp_reset)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

Add documentation to describe Sunplus SP7021 clock driver bindings.

Reviewed-by Rob Herring <[email protected]>

Signed-off-by Qin Jian <[email protected]>

---
 .../bindings/clock/sunplus,sp7021-clkc.yaml   |  38 ++++++
 MAINTAINERS                                   |   2 +
 include/dt-bindings/clock/sp-sp7021.h         | 112 ++++++++++++++++++
 3 files changed, 152 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 create mode 100644 include/dt-bindings/clock/sp-sp7021.h

Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file +11 -0

new file mode 100644
index 000000000..1ce7e41d8
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 SoC Clock Controller Binding
+
+maintainers:
+  - Qin Jian <[email protected]>

Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file +6 -0

+      compatible = "sunplus,sp7021-clkc";
+      #clock-cells = <1>;
+      reg = <0x9c000000 0x280>;
+    };
+
+...

drivers/clk/clk-sp7021.c new file +30 -0

+
+#define REG(i)         (pll_regs + (i) * 4)
+
+#define PLLA_CTL       REG(7)
+#define PLLE_CTL       REG(12)
+#define PLLF_CTL       REG(13)
+#define PLLTV_CTL      REG(14)
+#define PLLSYS_CTL     REG(26)
+
+#define EXTCLK         "extclk"
+
+/* speical div_width values for PLLTV/PLLA */
+#define DIV_TV         33
+#define DIV_A          34
+
+/* PLLTV parameters */
+enum {
+       SEL_FRA,
+       SDM_MOD,
+       PH_SEL,
+       NFRA,
+       DIVR,
+       DIVN,
+       DIVM,
+       P_MAX
+};
+
+#define MASK_SEL_FRA   GENMASK(1, 1)
+#define MASK_SDM_MOD   GENMASK(2, 2)
+#define MASK_PH_SEL            GENMASK(4, 4)

drivers/clk/clk-sp7021.c new file +12 -0

+})
+
+struct sp_pll {
+       struct clk_hw hw;
+       void __iomem *reg;
+       spinlock_t *lock;       /* lock for reg */
+       int div_shift;
+       int div_width;
+       int pd_bit;             /* power down bit idx */
+       int bp_bit;             /* bypass bit idx */
+       unsigned long brate;    /* base rate, TODO: replace brate with muldiv */
+       u32 p[P_MAX];   /* for hold PLLTV/PLLA parameters */

drivers/clk/clk-sp7021.c new file +166 -0

+       "pllsys",
+       "extclk",
+};
+
+static const u32 gates[] = {
+       CLK_SYSTEM,
+       CLK_RTC,
+       CLK_IOCTL,
+       CLK_IOP,
+       CLK_OTPRX,
+       CLK_NOC,
+       CLK_BR,
+       CLK_RBUS_L00,
+       CLK_SPIFL,
+       CLK_SDCTRL0,
+       CLK_PERI0 | P_EXTCLK,
+       CLK_A926,
+       CLK_UMCTL2,
+       CLK_PERI1 | P_EXTCLK,
+
+       CLK_DDR_PHY0,
+       CLK_ACHIP,
+       CLK_STC0,
+       CLK_STC_AV0,
+       CLK_STC_AV1,
+       CLK_STC_AV2,
+       CLK_UA0 | P_EXTCLK,
+       CLK_UA1 | P_EXTCLK,
+       CLK_UA2 | P_EXTCLK,
+       CLK_UA3 | P_EXTCLK,
+       CLK_UA4 | P_EXTCLK,
+       CLK_HWUA | P_EXTCLK,
+       CLK_DDC0,
+       CLK_UADMA | P_EXTCLK,
+
+       CLK_CBDMA0,
+       CLK_CBDMA1,
+       CLK_SPI_COMBO_0,
+       CLK_SPI_COMBO_1,
+       CLK_SPI_COMBO_2,
+       CLK_SPI_COMBO_3,
+       CLK_AUD,
+       CLK_USBC0,
+       CLK_USBC1,
+       CLK_UPHY0,
+       CLK_UPHY1,
+
+       CLK_I2CM0,
+       CLK_I2CM1,
+       CLK_I2CM2,
+       CLK_I2CM3,
+       CLK_PMC,
+       CLK_CARD_CTL0,
+       CLK_CARD_CTL1,
+
+       CLK_CARD_CTL4,
+       CLK_BCH,
+       CLK_DDFCH,
+       CLK_CSIIW0,
+       CLK_CSIIW1,
+       CLK_MIPICSI0,
+       CLK_MIPICSI1,
+
+       CLK_HDMI_TX,
+       CLK_VPOST,
+
+       CLK_TGEN,
+       CLK_DMIX,
+       CLK_TCON,
+       CLK_INTERRUPT,
+
+       CLK_RGST,
+       CLK_GPIO,
+       CLK_RBUS_TOP,
+
+       CLK_MAILBOX,
+       CLK_SPIND,
+       CLK_I2C2CBUS,
+       CLK_SEC,
+       CLK_GPOST0,
+       CLK_DVE,
+
+       CLK_OSD0,
+       CLK_DISP_PWM,
+       CLK_UADBG,
+       CLK_DUMMY_MASTER,
+       CLK_FIO_CTL,
+       CLK_FPGA,
+       CLK_L2SW,
+       CLK_ICM,
+       CLK_AXI_GLOBAL,
+};
+
+static struct clk *clks[CLK_MAX];
+static struct clk_onecell_data clk_data;
+
+static DEFINE_SPINLOCK(plla_lock);
+static DEFINE_SPINLOCK(plle_lock);
+static DEFINE_SPINLOCK(pllf_lock);
+static DEFINE_SPINLOCK(pllsys_lock);
+static DEFINE_SPINLOCK(plltv_lock);
+
+#define _M                     1000000UL
+#define F_27M          (27 * _M)
+
+/******************************************** PLL_TV *******************************************/
+
+//#define PLLTV_STEP_DIR (?) /* Unit: HZ */
+
+/* TODO: set proper FVCO range */
+#define FVCO_MIN       (100 * _M)
+#define FVCO_MAX       (200 * _M)
+
+#define F_MIN          (FVCO_MIN / 8)
+#define F_MAX          (FVCO_MAX)
+
+static long plltv_integer_div(struct sp_pll *clk, unsigned long freq)
+{
+       /* valid m values: 27M must be divisible by m, 0 means end */
+       static const u32 m_table[] = {
+               1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, 30, 32, 0
+       };
+       u32 m, n, r;
+#ifdef PLLTV_STEP_DIR
+       u32 step = (PLLTV_STEP_DIR > 0) ? PLLTV_STEP_DIR : -PLLTV_STEP_DIR;
+       int calc_times = 1000000 / step;
+#endif
+       unsigned long fvco, nf;
+
+       /* check freq */
+       if (freq < F_MIN) {
+               pr_warn("%s: %s freq:%lu < F_MIN:%lu, round up\n",
+                       __func__, clk_hw_get_name(&clk->hw), freq, F_MIN);
+               freq = F_MIN;
+       } else if (freq > F_MAX) {
+               pr_warn("%s: %s freq:%lu > F_MAX:%lu, round down\n",
+                       __func__, clk_hw_get_name(&clk->hw), freq, F_MAX);
+               freq = F_MAX;
+       }
+
+#ifdef PLLTV_STEP_DIR
+       if ((freq % step) != 0)
+               freq += step - (freq % step) + ((PLLTV_STEP_DIR > 0) ? 0 : PLLTV_STEP_DIR);
+#endif
+
+#ifdef PLLTV_STEP_DIR
+CALC:
+       if (!calc_times) {
+               pr_err("%s: %s freq:%lu out of recalc times\n",
+                      __func__, clk_hw_get_name(&clk->hw), freq);
+               return -ETIMEOUT;
+       }
+#endif
+
+       /* DIVR 0~3 */
+       for (r = 0; r <= 3; r++) {
+               fvco = freq << r;
+               if (fvco <= FVCO_MAX)
+                       break;
+       }
+
+       /* DIVM */
+       for (m = 0; m_table[m]; m++) {
+               nf = fvco * m_table[m];
+               n = nf / F_27M;
+               if ((n * F_27M) == nf)

drivers/clk/clk-sp7021.c new file +159 -0

+               pr_err("%s: %s freq:%lu not found a valid setting\n",
+                      __func__, clk_hw_get_name(&clk->hw), freq);
+               return -EINVAL;
+#endif
+       }
+
+       /* save parameters */
+       clk->p[SEL_FRA] = 0;
+       clk->p[DIVR]    = r;
+       clk->p[DIVN]    = n;
+       clk->p[DIVM]    = m;
+
+       return freq;
+}
+
+/* parameters for PLLTV fractional divider */
+static const u32 pt[][5] = {
+       /* conventional fractional */
+       {
+               1,                      // factor
+               5,                      // 5 * p0 (nint)
+               1,                      // 1 * p0
+               F_27M,                  // F_27M / p0
+               1,                      // p0 / p2
+       },
+       /* phase rotation */
+       {
+               10,                     // factor
+               54,                     // 5.4 * p0 (nint)
+               2,                      // 0.2 * p0
+               F_27M / 10,             // F_27M / p0
+               5,                      // p0 / p2
+       },
+};
+
+static const u32 mods[] = { 91, 55 }; /* SDM_MOD mod values */
+
+static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq)
+{
+       u32 m, r;
+       u32 nint, nfra;
+       u32 diff_min_quotient = 210000000, diff_min_remainder = 0;
+       u32 diff_min_sign = 0;
+       unsigned long fvco, nf, f, fout = 0;
+       int sdm, ph;
+
+       /* check freq */
+       if (freq < F_MIN) {
+               pr_warn("%s: %s freq:%lu < F_MIN:%lu, round up\n",
+                       __func__, clk_hw_get_name(&clk->hw), freq, F_MIN);
+               freq = F_MIN;
+       } else if (freq > F_MAX) {
+               pr_warn("%s: %s freq:%lu > F_MAX:%lu, round down\n",
+                       __func__, clk_hw_get_name(&clk->hw), freq, F_MAX);
+               freq = F_MAX;
+       }
+
+       /* DIVR 0~3 */
+       for (r = 0; r <= 3; r++) {
+               fvco = freq << r;
+               if (fvco <= FVCO_MAX)
+                       break;
+       }
+       f = F_27M >> r;
+
+       /* PH_SEL 1/0 */
+       for (ph = 1; ph >= 0; ph--) {
+               const u32 *pp = pt[ph];
+               u32 ms = 1;
+
+               /* SDM_MOD 0/1 */
+               for (sdm = 0; sdm <= 1; sdm++) {
+                       u32 mod = mods[sdm];
+
+                       /* DIVM 1~32 */
+                       for (m = ms; m <= 32; m++) {
+                               u32 diff_freq;
+                               u32 diff_freq_quotient = 0, diff_freq_remainder = 0;
+                               u32 diff_freq_sign = 0; /* 0:Positive number, 1:Negative number */
+
+                               nf = fvco * m;
+                               nint = nf / pp[3];
+
+                               if (nint < pp[1])
+                                       continue;
+                               if (nint > pp[1])
+                                       break;
+
+                               nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M;
+                               if (nfra)
+                                       diff_freq = (f * (nint + pp[2]) / pp[0]) -
+                                                               (f * (mod - nfra) / mod / pp[4]);
+                               else
+                                       diff_freq = (f * (nint) / pp[0]);
+
+                               diff_freq_quotient  = diff_freq / m;
+                               diff_freq_remainder = ((diff_freq % m) * 1000) / m;
+
+                               if (freq > diff_freq_quotient) {
+                                       diff_freq_quotient  = freq - diff_freq_quotient - 1;
+                                       diff_freq_remainder = 1000 - diff_freq_remainder;
+                                       diff_freq_sign = 1;
+                               } else {
+                                       diff_freq_quotient = diff_freq_quotient - freq;
+                                       diff_freq_sign = 0;
+                               }
+
+                               if (diff_min_quotient > diff_freq_quotient ||
+                                   (diff_min_quotient == diff_freq_quotient &&
+                                   diff_min_remainder > diff_freq_remainder)) {
+                                       /* found a closer freq, save parameters */
+                                       clk->p[SEL_FRA] = 1;
+                                       clk->p[SDM_MOD] = sdm;
+                                       clk->p[PH_SEL]  = ph;
+                                       clk->p[NFRA]    = nfra;
+                                       clk->p[DIVR]    = r;
+                                       clk->p[DIVM]    = m;
+
+                                       fout = diff_freq / m;
+                                       diff_min_quotient = diff_freq_quotient;
+                                       diff_min_remainder = diff_freq_remainder;
+                                       diff_min_sign = diff_freq_sign;
+                               }
+                       }
+               }
+       }
+
+       if (!fout) {
+               pr_err("%s: %s freq:%lu not found a valid setting\n",
+                      __func__, clk_hw_get_name(&clk->hw), freq);
+               return -EINVAL;
+       }
+
+       return fout;
+}
+
+static long plltv_div(struct sp_pll *clk, unsigned long freq)
+{
+       if (freq % 100)
+               return plltv_fractional_div(clk, freq);
+       else
+               return plltv_integer_div(clk, freq);
+}
+
+static void plltv_set_rate(struct sp_pll *clk)
+{
+       u32 reg;
+
+       reg  = HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]);
+       reg |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]);
+       reg |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]);
+       reg |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]);
+       clk_writel(reg, clk->reg);
+
+       reg  = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]);
+       clk_writel(reg, clk->reg + 4);
+
+       reg  = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1);
+       reg |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1);

drivers/clk/clk-sp7021.c new file +210 -0

+       {
+               .rate = 135475200,
+               .regs = {
+                       0x4801,
+                       0x02df,
+                       0x248f,
+                       0x0211,
+                       0x33e9
+               }
+       },
+       {
+               .rate = 147456000,
+               .regs = {
+                       0x4801,
+                       0x1adf,
+                       0x2490,
+                       0x0349,
+                       0x33e9
+               }
+       },
+       {
+               .rate = 196608000,
+               .regs = {
+                       0x4801,
+                       0x42ef,
+                       0x2495,
+                       0x01c6,
+                       0x33e9
+               }
+       },
+};
+
+static void plla_set_rate(struct sp_pll *clk)
+{
+       const u32 *pp = pa[clk->p[0]].regs;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(pa->regs); i++)
+               clk_writel(0xffff0000 | pp[i], clk->reg + (i * 4));
+}
+
+static long plla_round_rate(struct sp_pll *clk, unsigned long rate)
+{
+       int i = ARRAY_SIZE(pa);
+
+       while (--i) {
+               if (rate >= pa[i].rate)
+                       break;
+       }
+       clk->p[0] = i;
+       return pa[i].rate;
+}
+
+/******************************************* SP_PLL ********************************************/
+
+static long sp_pll_calc_div(struct sp_pll *clk, unsigned long rate)
+{
+       u32 fbdiv;
+       u32 max = 1 << clk->div_width;
+
+       fbdiv = DIV_ROUND_CLOSEST(rate, clk->brate);
+       if (fbdiv > max)
+               fbdiv = max;
+       return fbdiv;
+}
+
+static long sp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                             unsigned long *prate)
+{
+       struct sp_pll *clk = to_sp_pll(hw);
+       long ret;
+
+       if (rate == *prate)
+               ret = *prate; /* bypass */
+       else if (clk->div_width == DIV_A) {
+               ret = plla_round_rate(clk, rate);
+       } else if (clk->div_width == DIV_TV) {
+               ret = plltv_div(clk, rate);
+               if (ret < 0)
+                       ret = *prate;
+       } else {
+               ret = sp_pll_calc_div(clk, rate) * clk->brate;
+       }
+
+       return ret;
+}
+
+static unsigned long sp_pll_recalc_rate(struct clk_hw *hw,
+                                       unsigned long prate)
+{
+       struct sp_pll *clk = to_sp_pll(hw);
+       u32 reg = clk_readl(clk->reg);
+       unsigned long ret;
+
+       if (reg & BIT(clk->bp_bit)) {
+               ret = prate; /* bypass */
+       } else if (clk->div_width == DIV_A) {
+               ret = pa[clk->p[0]].rate;
+       } else if (clk->div_width == DIV_TV) {
+               u32 m, r, reg2;
+
+               r = FIELD_GET(MASK_DIVR, clk_readl(clk->reg + 4));
+               reg2 = clk_readl(clk->reg + 8);
+               m = FIELD_GET(MASK_DIVM, reg2) + 1;
+
+               if (reg & BIT(1)) { /* SEL_FRA */
+                       /* fractional divider */
+                       u32 sdm  = FIELD_GET(MASK_SDM_MOD, reg);
+                       u32 ph   = FIELD_GET(MASK_PH_SEL, reg);
+                       u32 nfra = FIELD_GET(MASK_NFRA, reg);
+                       const u32 *pp = pt[ph];
+
+                       ret = prate >> r;
+                       ret = (ret * (pp[1] + pp[2]) / pp[0]) -
+                                 (ret * (mods[sdm] - nfra) / mods[sdm] / pp[4]);
+                       ret /= m;
+               } else {
+                       /* integer divider */
+                       u32 n = FIELD_GET(MASK_DIVN, reg2) + 1;
+
+                       ret = (prate / m * n) >> r;
+               }
+       } else {
+               u32 fbdiv = (reg >> clk->div_shift) & ((1 << clk->div_width) - 1);
+
+               ret = clk->brate * fbdiv;
+       }
+
+       return ret;
+}
+
+static int sp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+                          unsigned long prate)
+{
+       struct sp_pll *clk = to_sp_pll(hw);
+       unsigned long flags;
+       u32 reg;
+
+       spin_lock_irqsave(clk->lock, flags);
+
+       reg = BIT(clk->bp_bit + 16); /* HIWORD_MASK */
+
+       if (rate == prate)
+               reg |= BIT(clk->bp_bit); /* bypass */
+       else if (clk->div_width == DIV_A)
+               plla_set_rate(clk);
+       else if (clk->div_width == DIV_TV)
+               plltv_set_rate(clk);
+       else if (clk->div_width) {
+               u32 fbdiv = sp_pll_calc_div(clk, rate);
+               u32 mask = GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift);
+
+               reg |= (mask << 16) | (((fbdiv - 1) << clk->div_shift) & mask);
+       }
+
+       clk_writel(reg, clk->reg);
+
+       spin_unlock_irqrestore(clk->lock, flags);
+
+       return 0;
+}
+
+static int sp_pll_enable(struct clk_hw *hw)
+{
+       struct sp_pll *clk = to_sp_pll(hw);
+       unsigned long flags;
+
+       spin_lock_irqsave(clk->lock, flags);
+       clk_writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg); /* power up */
+       spin_unlock_irqrestore(clk->lock, flags);
+
+       return 0;
+}
+
+static void sp_pll_disable(struct clk_hw *hw)
+{
+       struct sp_pll *clk = to_sp_pll(hw);
+       unsigned long flags;
+
+       spin_lock_irqsave(clk->lock, flags);
+       clk_writel(BIT(clk->pd_bit + 16), clk->reg); /* power down */
+       spin_unlock_irqrestore(clk->lock, flags);
+}
+
+static int sp_pll_is_enabled(struct clk_hw *hw)
+{
+       struct sp_pll *clk = to_sp_pll(hw);
+
+       return clk_readl(clk->reg) & BIT(clk->pd_bit);
+}
+
+static const struct clk_ops sp_pll_ops = {
+       .enable = sp_pll_enable,
+       .disable = sp_pll_disable,
+       .is_enabled = sp_pll_is_enabled,
+       .round_rate = sp_pll_round_rate,
+       .recalc_rate = sp_pll_recalc_rate,
+       .set_rate = sp_pll_set_rate
+};
+
+static const struct clk_ops sp_pll_sub_ops = {
+       .enable = sp_pll_enable,
+       .disable = sp_pll_disable,
+       .is_enabled = sp_pll_is_enabled,
+       .recalc_rate = sp_pll_recalc_rate,
+};
+
+struct clk *clk_register_sp_pll(const char *name, const char *parent,
+                               void __iomem *reg, int pd_bit, int bp_bit,
+                               unsigned long brate, int shift, int width,

drivers/clk/clk-sp7021.c new file +5 -0

+       if (WARN_ON(IS_ERR(clk))) {
+               kfree(pll);
+       } else {
+               pr_info("%-20s%lu\n", name, clk_get_rate(clk));
+               clk_register_clkdev(clk, NULL, name);

drivers/clk/clk-sp7021.c new file +30 -0

+       if (WARN_ON(!moon_regs))
+               return; /* -ENXIO */
+
+       /* PLL_A */
+       clks[PLL_A] = clk_register_sp_pll("plla", EXTCLK,
+                                         PLLA_CTL, 11, 12, 27000000, 0, DIV_A, &plla_lock);
+
+       /* PLL_E */
+       clks[PLL_E] = clk_register_sp_pll("plle", EXTCLK,
+                                         PLLE_CTL, 6, 2, 50000000, 0, 0, &plle_lock);
+       clks[PLL_E_2P5] = clk_register_sp_pll("plle_2p5", "plle",
+                                             PLLE_CTL, 13, -1, 2500000, 0, 0, &plle_lock);
+       clks[PLL_E_25] = clk_register_sp_pll("plle_25", "plle",
+                                            PLLE_CTL, 12, -1, 25000000, 0, 0, &plle_lock);
+       clks[PLL_E_112P5] = clk_register_sp_pll("plle_112p5", "plle",
+                                               PLLE_CTL, 11, -1, 112500000, 0, 0, &plle_lock);
+
+       /* PLL_F */
+       clks[PLL_F] = clk_register_sp_pll("pllf", EXTCLK,
+                                         PLLF_CTL, 0, 10, 13500000, 1, 4, &pllf_lock);
+
+       /* PLL_TV */
+       clks[PLL_TV] = clk_register_sp_pll("plltv", EXTCLK,
+                                          PLLTV_CTL, 0, 15, 27000000, 0, DIV_TV, &plltv_lock);
+       clks[PLL_TV_A] = clk_register_divider(NULL, "plltv_a", "plltv", 0,
+                                             PLLTV_CTL + 4, 5, 1,
+                                             CLK_DIVIDER_POWER_OF_TWO, &plltv_lock);
+       clk_register_clkdev(clks[PLL_TV_A], NULL, "plltv_a");
+
+       /* PLL_SYS */

Add interrupt controller driver for Sunplus SP7021 SoC.

This is the interrupt controller in P-chip which collects all interrupt sources in P-chip and routes them to parent interrupt controller in C-chip.

Signed-off-by Qin Jian <[email protected]>

---
 MAINTAINERS                       |   1 +
 drivers/irqchip/Kconfig           |   9 +
 drivers/irqchip/Makefile          |   1 +
 drivers/irqchip/irq-sp7021-intc.c | 284 ++++++++++++++++++++++++++++++
 4 files changed, 295 insertions(+)
 create mode 100644 drivers/irqchip/irq-sp7021-intc.c

MAINTAINERS +1 -0

index 6b3bbe021..febbd97bf 100644
@@ -2665,6 +2665,7 @@ F:	Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:	Documentation/devicetree/bindings/reset/sunplus,reset.yaml
 F:	drivers/clk/clk-sp7021.c
+F:	drivers/irqchip/irq-sp7021-intc.c
 F:	drivers/reset/reset-sunplus.c
 F:	include/dt-bindings/clock/sp-sp7021.h
 F:	include/dt-bindings/reset/sp-sp7021.h

drivers/irqchip/Kconfig +9 -0

index aca7b595c..b9429b8d0 100644
@@ -602,4 +602,13 @@ config APPLE_AIC
 	  Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
 	  such as the M1.
 
+config SUNPLUS_SP7021_INTC
+	bool "Sunplus SP7021 interrupt controller"
+	help
+	  Support for the Sunplus SP7021 Interrupt Controller IP core.
+	  SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
+	  chained controller, routing all interrupt source in P-Chip to
+	  the primary controller on C-Chip.
+	  This is selected automatically by platform config.
+
 endmenu

drivers/irqchip/Makefile +1 -0

index f88cbf36a..75411f654 100644
@@ -116,3 +116,4 @@ obj-$(CONFIG_MACH_REALTEK_RTL)		+= irq-realtek-rtl.o
 obj-$(CONFIG_WPCM450_AIC)		+= irq-wpcm450-aic.o
 obj-$(CONFIG_IRQ_IDT3243X)		+= irq-idt3243x.o
 obj-$(CONFIG_APPLE_AIC)			+= irq-apple-aic.o
+obj-$(CONFIG_SUNPLUS_SP7021_INTC)	+= irq-sp7021-intc.o

drivers/irqchip/irq-sp7021-intc.c new file +76 -0

new file mode 100644
index 000000000..beabc64d5
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) Sunplus Technology Co., Ltd.
+ *       All rights reserved.
+ */
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define SP_INTC_HWIRQ_MIN	0
+#define SP_INTC_HWIRQ_MAX	223
+
+#define SP_INTC_NR_IRQS		(SP_INTC_HWIRQ_MAX - SP_INTC_HWIRQ_MIN + 1)
+#define SP_INTC_NR_GROUPS	DIV_ROUND_UP(SP_INTC_NR_IRQS, 32)
+#define SP_INTC_REG_SIZE	(SP_INTC_NR_GROUPS * 4)
+
+/* REG_GROUP_0 regs */
+#define REG_INTR_TYPE		(sp_intc.g0)
+#define REG_INTR_POLARITY	(REG_INTR_TYPE     + SP_INTC_REG_SIZE)
+#define REG_INTR_PRIORITY	(REG_INTR_POLARITY + SP_INTC_REG_SIZE)
+#define REG_INTR_MASK		(REG_INTR_PRIORITY + SP_INTC_REG_SIZE)
+
+/* REG_GROUP_1 regs */
+#define REG_INTR_CLEAR		(sp_intc.g1)
+#define REG_MASKED_EXT1		(REG_INTR_CLEAR    + SP_INTC_REG_SIZE)
+#define REG_MASKED_EXT0		(REG_MASKED_EXT1   + SP_INTC_REG_SIZE)
+#define REG_INTR_GROUP		(REG_INTR_CLEAR    + 31 * 4)
+
+#define GROUP_MASK			(BIT(SP_INTC_NR_GROUPS) - 1)
+#define GROUP_SHIFT_EXT1	(0)
+#define GROUP_SHIFT_EXT0	(8)
+
+/*
+ * When GPIO_INT0~7 set to edge trigger, doesn't work properly.
+ * WORKAROUND: change it to level trigger, and toggle the polarity
+ * at ACK/Handler to make the HW work.
+ */
+#define GPIO_INT0_HWIRQ		120
+#define GPIO_INT7_HWIRQ		127
+#define IS_GPIO_INT(irq)	\
+({ \
+	u32 i = irq; \
+	(i >= GPIO_INT0_HWIRQ) && (i <= GPIO_INT7_HWIRQ); \
+})
+
+/* index of states */
+enum {
+	_IS_EDGE = 0,
+	_IS_LOW,
+	_IS_ACTIVE
+};
+
+#define STATE_BIT(irq, idx)			(((irq) - GPIO_INT0_HWIRQ) * 3 + (idx))
+#define ASSIGN_STATE(irq, idx, v)	assign_bit(STATE_BIT(irq, idx), sp_intc.states, v)
+#define TEST_STATE(irq, idx)		test_bit(STATE_BIT(irq, idx), sp_intc.states)
+
+static struct sp_intctl {
+	/*
+	 * REG_GROUP_0: include type/polarity/priority/mask regs.
+	 * REG_GROUP_1: include clear/masked_ext0/masked_ext1/group regs.
+	 */
+	void __iomem *g0; // REG_GROUP_0 base
+	void __iomem *g1; // REG_GROUP_1 base
+
+	struct irq_domain *domain;
+	raw_spinlock_t lock;
+
+	/*
+	 * store GPIO_INT states
+	 * each interrupt has 3 states: is_edge, is_low, is_active
+	 */
+	DECLARE_BITMAP(states, (GPIO_INT7_HWIRQ - GPIO_INT0_HWIRQ + 1) * 3);

drivers/irqchip/irq-sp7021-intc.c new file +131 -0

+	raw_spin_unlock_irqrestore(&sp_intc.lock, flags);
+}
+
+static void sp_intc_ack_irq(struct irq_data *d)
+{
+	u32 hwirq = d->hwirq;
+
+	if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND
+		sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW));
+		ASSIGN_STATE(hwirq, _IS_ACTIVE, true);
+	}
+
+	sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1);
+}
+
+static void sp_intc_mask_irq(struct irq_data *d)
+{
+	sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0);
+}
+
+static void sp_intc_unmask_irq(struct irq_data *d)
+{
+	sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 1);
+}
+
+static int sp_intc_set_type(struct irq_data *d, unsigned int type)
+{
+	u32 hwirq = d->hwirq;
+	bool is_edge = !(type & IRQ_TYPE_LEVEL_MASK);
+	bool is_low = (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING);
+
+	irq_set_handler_locked(d, is_edge ? handle_edge_irq : handle_level_irq);
+
+	if (unlikely(IS_GPIO_INT(hwirq) && is_edge)) { // WORKAROUND
+		/* store states */
+		ASSIGN_STATE(hwirq, _IS_EDGE, is_edge);
+		ASSIGN_STATE(hwirq, _IS_LOW, is_low);
+		ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
+		/* change to level */
+		is_edge = false;
+	}
+
+	sp_intc_assign_bit(hwirq, REG_INTR_TYPE, is_edge);
+	sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, is_low);
+
+	return 0;
+}
+
+static int sp_intc_get_ext_irq(int ext_num)
+{
+	void __iomem *base = ext_num ? REG_MASKED_EXT1 : REG_MASKED_EXT0;
+	u32 shift = ext_num ? GROUP_SHIFT_EXT1 : GROUP_SHIFT_EXT0;
+	u32 groups;
+	u32 pending_group;
+	u32 group;
+	u32 pending_irq;
+
+	groups = readl_relaxed(REG_INTR_GROUP);
+	pending_group = (groups >> shift) & GROUP_MASK;
+	if (!pending_group)
+		return -1;
+
+	group = fls(pending_group) - 1;
+	pending_irq = readl_relaxed(base + group * 4);
+	if (!pending_irq)
+		return -1;
+
+	return (group * 32) + fls(pending_irq) - 1;
+}
+
+static void sp_intc_handle_ext_cascaded(struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	int ext_num = (int)irq_desc_get_handler_data(desc);
+	int hwirq;
+
+	chained_irq_enter(chip, desc);
+
+	while ((hwirq = sp_intc_get_ext_irq(ext_num)) >= 0) {
+		if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_ACTIVE))) { // WORKAROUND
+			ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
+			sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, TEST_STATE(hwirq, _IS_LOW));
+		} else {
+			generic_handle_domain_irq(sp_intc.domain, hwirq);
+		}
+	}
+
+	chained_irq_exit(chip, desc);
+}
+
+#ifdef CONFIG_SMP
+static int sp_intc_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
+{
+	return -EINVAL;
+}
+#endif
+
+static struct irq_chip sp_intc_chip = {
+	.name = "sp_intc",
+	.irq_ack = sp_intc_ack_irq,
+	.irq_mask = sp_intc_mask_irq,
+	.irq_unmask = sp_intc_unmask_irq,
+	.irq_set_type = sp_intc_set_type,
+#ifdef CONFIG_SMP
+	.irq_set_affinity = sp_intc_set_affinity,
+#endif
+};
+
+static int sp_intc_irq_domain_map(struct irq_domain *domain,
+				  unsigned int irq, irq_hw_number_t hwirq)
+{
+	irq_set_chip_and_handler(irq, &sp_intc_chip, handle_level_irq);
+	irq_set_chip_data(irq, &sp_intc_chip);
+	irq_set_noprobe(irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops sp_intc_dm_ops = {
+	.xlate = irq_domain_xlate_twocell,
+	.map = sp_intc_irq_domain_map,
+};
+
+static int sp_intc_irq_map(struct device_node *node, int i)
+{
+	unsigned int irq;
+
+	irq = irq_of_parse_and_map(node, i);
+	if (!irq)
+		return -ENOENT;
+

drivers/irqchip/irq-sp7021-intc.c new file +45 -0

+{
+	int i, ret;
+
+	sp_intc.g0 = of_iomap(node, 0);
+	if (!sp_intc.g0)
+		return -ENXIO;
+
+	sp_intc.g1 = of_iomap(node, 1);
+	if (!sp_intc.g1) {
+		ret = -ENXIO;
+		goto out_unmap0;
+	}
+
+	ret = sp_intc_irq_map(node, 0); // EXT_INT0
+	if (ret)
+		goto out_unmap1;
+
+	ret = sp_intc_irq_map(node, 1); // EXT_INT1
+	if (ret)
+		goto out_unmap1;
+
+	/* initial regs */
+	for (i = 0; i < SP_INTC_NR_GROUPS; i++) {
+		/* all mask */
+		writel_relaxed(0, REG_INTR_MASK + i * 4);
+		/* all edge */
+		writel_relaxed(~0, REG_INTR_TYPE + i * 4);
+		/* all high-active */
+		writel_relaxed(0, REG_INTR_POLARITY + i * 4);
+		/* all EXT_INT0 */
+		writel_relaxed(~0, REG_INTR_PRIORITY + i * 4);
+		/* all clear */
+		writel_relaxed(~0, REG_INTR_CLEAR + i * 4);
+	}
+
+	sp_intc.domain = irq_domain_add_linear(node, SP_INTC_NR_IRQS,
+					       &sp_intc_dm_ops, &sp_intc);
+	if (!sp_intc.domain) {
+		ret = -ENOMEM;
+		goto out_unmap1;
+	}
+
+	raw_spin_lock_init(&sp_intc.lock);
+
+	return 0;

drivers/irqchip/irq-sp7021-intc.c line 227

Quoted 5 lines

drivers/irqchip/irq-sp7021-intc.c new file +5 -0

+void sp_intc_set_ext(u32 hwirq, int ext_num)
+{
+	sp_intc_assign_bit(hwirq, REG_INTR_PRIORITY, !ext_num);
+}
+EXPORT_SYMBOL_GPL(sp_intc_set_ext);

No way. We don't export random symbols without a good justification, and you didn't give any.

Quoted 9 lines

drivers/irqchip/irq-sp7021-intc.c line 227

Quoted 5 lines

drivers/irqchip/irq-sp7021-intc.c new file +5 -0

+void sp_intc_set_ext(u32 hwirq, int ext_num)
+{
+	sp_intc_assign_bit(hwirq, REG_INTR_PRIORITY, !ext_num);
+}
+EXPORT_SYMBOL_GPL(sp_intc_set_ext);

No way. We don't export random symbols without a good justification, and you didn't give any.

This function called by SP7021 display driver to decide DISPLAY_IRQ routing to which parent irq (EXT_INT0 or EXT_INT1).

In previous patches, which defined in DT, parsed & processed @ sp_intc_xlate_of()
From your comment, this is a SW decision. So I removed it from DT & intc driver, only
export this function to access the related intc reg.

-----Original Message-----
From: Marc Zyngier <[email protected]>
Sent: Wednesday, December 8, 2021 3:45 PM
To: qinjian[覃健] <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; Wells Lu 呂芳騰 <[email protected]>
Subject: Re: [PATCH v5 08/10] irqchip: Add Sunplus SP7021 interrupt controller driver

Quoted 10 lines · qinjian[覃健]

Quoted 9 lines

drivers/irqchip/irq-sp7021-intc.c line 227

Quoted 5 lines

drivers/irqchip/irq-sp7021-intc.c new file +5 -0

+void sp_intc_set_ext(u32 hwirq, int ext_num)
+{
+	sp_intc_assign_bit(hwirq, REG_INTR_PRIORITY, !ext_num);
+}
+EXPORT_SYMBOL_GPL(sp_intc_set_ext);

No way. We don't export random symbols without a good justification, and you didn't give any.

Quoted 2 lines

This function called by SP7021 display driver to decide DISPLAY_IRQ routing to which parent irq (EXT_INT0 or EXT_INT1).

Based on what? How can a display driver decide which parent is appropriate? What improvement does this bring?

Quoted 24 lines

-----Original Message-----
From: Marc Zyngier <[email protected]>
Sent: Wednesday, December 8, 2021 3:45 PM
To: qinjian[覃健] <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; Wells Lu 呂芳騰 <[email protected]>
Subject: Re: [PATCH v5 08/10] irqchip: Add Sunplus SP7021 interrupt controller driver

Quoted 12 lines · qinjian[覃健]

Quoted 9 lines

drivers/irqchip/irq-sp7021-intc.c line 227

Quoted 5 lines

drivers/irqchip/irq-sp7021-intc.c new file +5 -0

+void sp_intc_set_ext(u32 hwirq, int ext_num)
+{
+	sp_intc_assign_bit(hwirq, REG_INTR_PRIORITY, !ext_num);
+}
+EXPORT_SYMBOL_GPL(sp_intc_set_ext);

No way. We don't export random symbols without a good justification, and you didn't give any.

This function called by SP7021 display driver to decide DISPLAY_IRQ routing to which parent irq (EXT_INT0 or EXT_INT1).

Quoted 2 lines

Based on what? How can a display driver decide which parent is appropriate? What improvement does this bring?

In default, all IRQ routing to EXT_INT0, which processed by CPU0 Some device's IRQ need low latency, like display, so routing DISPLAY_IRQ to EXT_INT1, which processed by CPU1 (set /proc/irq/<EXT_INT1>/smp_affinity_list)

arch/arm/Kconfig +0 -0

@@ -487,6 +487,22 @@ config ARCH_S3C24XX
          (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
          Samsung SMDK2410 development board (and derivatives).
 

arch/arm/Kconfig config ARCH_S3C24XX · line 499

Quoted 10 lines

arch/arm/Kconfig +10 -0

+config ARCH_SUNPLUS
+       bool "Sunplus SoCs"
+       select CLKSRC_OF
+       select COMMON_CLK
+       select GENERIC_CLOCKEVENTS
+       select GENERIC_IRQ_CHIP
+       select GENERIC_IRQ_MULTI_HANDLER
+       select USE_OF
+       select RTC_CLASS
+       select RESET_SUNPLUS

This is in the wrong place: move the Kconfig entry into arch/arm/mach-sunplus/Kconfig
and make it 'depends on ARCH_MULTI_V7'.

I think you can remove all the 'select' lines as well because they are either implied by
ARCH_MULTI_V7 or not actually necessary.
......

arch/arm/Makefile textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 · line 155

Quoted 6 lines

arch/arm/Makefile +1 -0

@@ -152,6 +152,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+textofs-$(CONFIG_ARCH_SUNPLUS) := 0x00308000

What is this needed for? If it boots without this line, better avoid adding it, because
it will increase the kernel size for everyone else (unless they also enable AXXIA).

Quoted 11 lines

arch/arm/Makefile textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 · line 155

Quoted 5 lines

arch/arm/Makefile +1 -0

@@ -152,6 +152,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+textofs-$(CONFIG_ARCH_SUNPLUS) := 0x00308000

What is this needed for? If it boots without this line, better avoid adding it, because
it will increase the kernel size for everyone else (unless they also enable AXXIA).

SP7021 reserved the 1st 1MB memory for ARM926@P-Chip using, The 2nd 1MB memory for IOP device and the 3rd 1MB memory for bootloader. I'll add these comments at next commit.

Quoted 12 lines

Quoted 11 lines

arch/arm/Makefile textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 · line 155

Quoted 5 lines

arch/arm/Makefile +1 -0

@@ -152,6 +152,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+textofs-$(CONFIG_ARCH_SUNPLUS) := 0x00308000

What is this needed for? If it boots without this line, better avoid adding it, because
it will increase the kernel size for everyone else (unless they also enable AXXIA).

Quoted 3 lines

SP7021 reserved the 1st 1MB memory for ARM926@P-Chip using, The 2nd 1MB memory for IOP device and the 3rd 1MB memory for bootloader. I'll add these comments at next commit.

I think you can just remove the memory from the system memory map in the device tree and pretend it only starts after the bootloader. It's been a while since I looked at this though, so I could be misremembering what the minimum boundaries are for doing this.

Arnd

Quoted 17 lines · qinjian[覃健]

Quoted 15 lines

Quoted 11 lines

arch/arm/Makefile textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 · line 155

Quoted 5 lines

arch/arm/Makefile +1 -0

@@ -152,6 +152,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+textofs-$(CONFIG_ARCH_SUNPLUS) := 0x00308000

What is this needed for? If it boots without this line, better avoid adding it, because
it will increase the kernel size for everyone else (unless they also enable AXXIA).

SP7021 reserved the 1st 1MB memory for ARM926@P-Chip using, The 2nd 1MB memory for IOP device and the 3rd 1MB memory for bootloader. I'll add these comments at next commit.

Quoted 4 lines

I think you can just remove the memory from the system memory map in the device tree and pretend it only starts after the bootloader. It's been a while since I looked at this though, so I could be misremembering what the minimum boundaries are for doing this.

I have test following 3 methods:

1. current patch
DT:

        memory {
                reg = <0x00000000 0x20000000>; /* 512MB */
        };

        reserved-memory {
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;

                iop_reserve: iop_device {
                        no-map;
                        reg = <0x00100000 0x00100000>;
                };
                a926_reserve: a926_memory {
                        no-map;
                        reg = <0x00000000 0x00100000>;
                };
        };
arch/arm/Makefile:
        textofs-$(CONFIG_ARCH_SUNPLUS) := 0x00308000

bootlog & meminfo :

[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x00000000001fffff]
[    0.000000]   node   0: [mem 0x0000000000200000-0x000000001fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]

~ # cat /proc/meminfo

MemTotal:         514008 kB
MemFree:          491960 kB
MemAvailable:     488608 kB

2. DT same as case 1, but no modify @ arch/arm/Makefile

bootlog & meminfo :

[    0.000000] OF: fdt: Reserved memory: failed to reserve memory for node 'iop_device': base 0x00100000, size 1 MiB
[    0.000000] OF: fdt: Reserved memory: failed to reserve memory for node 'a926_memory': base 0x00000000, size 1 MiB
...
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]

~ # cat /proc/meminfo

MemTotal:         516056 kB
MemFree:          493928 kB
MemAvailable:     490572 kB

3. DT:

        memory {
                reg = <0x00300000 0x1FD00000>; /* 512 - 3 MB */
        };

no modify @ arch/arm/Makefile

bootlog & meminfo :

[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000400000-0x000000001fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000400000-0x000000001fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000400000-0x000000001fffffff]

~ # cat /proc/meminfo

MemTotal:         511964 kB
MemFree:          489636 kB
MemAvailable:     486292 kB

I think method 1 should be correct (compare method 2) & better (compare method 3).

Quoted 17 lines · qinjian[覃健]

Quoted 17 lines · qinjian[覃健]

Quoted 15 lines

Quoted 11 lines

arch/arm/Makefile textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 · line 155

Quoted 5 lines

arch/arm/Makefile +1 -0

@@ -152,6 +152,7 @@ textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 textofs-$(CONFIG_ARCH_MESON) := 0x00208000
 textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
+textofs-$(CONFIG_ARCH_SUNPLUS) := 0x00308000

What is this needed for? If it boots without this line, better avoid adding it, because
it will increase the kernel size for everyone else (unless they also enable AXXIA).

SP7021 reserved the 1st 1MB memory for ARM926@P-Chip using, The 2nd 1MB memory for IOP device and the 3rd 1MB memory for bootloader. I'll add these comments at next commit.

Quoted 6 lines

Quoted 4 lines

I think you can just remove the memory from the system memory map in the device tree and pretend it only starts after the bootloader. It's been a while since I looked at this though, so I could be misremembering what the minimum boundaries are for doing this.

I have test following 3 methods:

Right, I was thinking of the third method here, which has the advantage of not requiring the same odd base address for all other platforms, this is important to us.
I don't see what the problem is with it in your example, does that mean you have a little less usable memory, or that something fails to work right? I don't know what the requirements are for memreserve.

Adding a few more people to Cc, maybe they have ideas about how this was solved elsewhere.

Quoted 83 lines

1. current patch
DT:

        memory {
                reg = <0x00000000 0x20000000>; /* 512MB */
        };

        reserved-memory {
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;

                iop_reserve: iop_device {
                        no-map;
                        reg = <0x00100000 0x00100000>;
                };
                a926_reserve: a926_memory {
                        no-map;
                        reg = <0x00000000 0x00100000>;
                };
        };
arch/arm/Makefile:
        textofs-$(CONFIG_ARCH_SUNPLUS) := 0x00308000

bootlog & meminfo :

[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x00000000001fffff]
[    0.000000]   node   0: [mem 0x0000000000200000-0x000000001fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]

~ # cat /proc/meminfo

MemTotal:         514008 kB
MemFree:          491960 kB
MemAvailable:     488608 kB

2. DT same as case 1, but no modify @ arch/arm/Makefile

bootlog & meminfo :

[    0.000000] OF: fdt: Reserved memory: failed to reserve memory for node 'iop_device': base 0x00100000, size 1 MiB
[    0.000000] OF: fdt: Reserved memory: failed to reserve memory for node 'a926_memory': base 0x00000000, size 1 MiB
...
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000001fffffff]

~ # cat /proc/meminfo

MemTotal:         516056 kB
MemFree:          493928 kB
MemAvailable:     490572 kB

3. DT:

        memory {
                reg = <0x00300000 0x1FD00000>; /* 512 - 3 MB */
        };

no modify @ arch/arm/Makefile

bootlog & meminfo :

[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000400000-0x000000001fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000400000-0x000000001fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000400000-0x000000001fffffff]

~ # cat /proc/meminfo

MemTotal:         511964 kB
MemFree:          489636 kB
MemAvailable:     486292 kB

I think method 1 should be correct (compare method 2) & better (compare method 3).

Add generic Sunplus SP7021 based board defconfig

Signed-off-by Qin Jian <[email protected]>

---
 MAINTAINERS                       |   1 +
 arch/arm/configs/sp7021_defconfig | 178 ++++++++++++++++++++++++++++++

MAINTAINERS +1 -0

index 0ae537a41..9340f8760 100644
@@ -2664,6 +2664,7 @@ F:        Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
 F:     Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
 F:     Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml
 F:     Documentation/devicetree/bindings/reset/sunplus,reset.yaml
+F:     arch/arm/configs/sp7021_*defconfig
 F:     arch/arm/mach-sunplus/
 F:     drivers/clk/clk-sp7021.c
 F:     drivers/irqchip/irq-sp7021-intc.c

arch/arm/configs/sp7021_defconfig new file +0 -0

new file mode 100644
index 000000000..249fe779e