arm64: DT binding/PMU updates

Wire up the new DT compatibles so we can present appropriate PMU names to userspace for the latest and greatest CPUs.

Signed-off-by Robin Murphy <[email protected]>

---
 arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

arch/arm64/kernel/perf_event.c +9 -0

index 57720372da62..3fe4dcfc28d4 100644
@@ -1215,6 +1215,26 @@ static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
 	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
 }
 
+static int armv9_a510_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a510", NULL);
+}
+
+static int armv9_a710_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a710", NULL);
+}

arch/arm64/kernel/perf_event.c +17 -0

+
 static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
 {
 	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL);

@@ -1225,6 +1245,16 @@ static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
 	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL);
 }
 
+static int armv9_n2_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_neoverse_n2", NULL);
+}
+
+static int armv8_v1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_v1", NULL);
+}
+
 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
 {
 	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",

@@ -1251,8 +1281,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
 	{.compatible = "arm,cortex-a76-pmu",	.data = armv8_a76_pmu_init},
 	{.compatible = "arm,cortex-a77-pmu",	.data = armv8_a77_pmu_init},
 	{.compatible = "arm,cortex-a78-pmu",	.data = armv8_a78_pmu_init},
+	{.compatible = "arm,cortex-a510-pmu",	.data = armv9_a510_pmu_init},
+	{.compatible = "arm,cortex-a710-pmu",	.data = armv9_a710_pmu_init},
+	{.compatible = "arm,cortex-x1-pmu",	.data = armv8_x1_pmu_init},
+	{.compatible = "arm,cortex-x2-pmu",	.data = armv9_x2_pmu_init},
 	{.compatible = "arm,neoverse-e1-pmu",	.data = armv8_e1_pmu_init},
 	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
+	{.compatible = "arm,neoverse-n2-pmu",	.data = armv9_n2_pmu_init},
+	{.compatible = "arm,neoverse-v1-pmu",	.data = armv8_v1_pmu_init},
 	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
 	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
 	{},

Signature · 1 line

2.28.0.dirty

Quoted 25 lines · Robin Murphy

Wire up the new DT compatibles so we can present appropriate PMU names to userspace for the latest and greatest CPUs.

Signed-off-by Robin Murphy <[email protected]>

---
  arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++++++++++++++++++
  1 file changed, 36 insertions(+)

arch/arm64/kernel/perf_event.c +9 -0

index 57720372da62..3fe4dcfc28d4 100644
@@ -1215,6 +1215,26 @@ static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
  }
 
+static int armv9_a510_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a510", NULL);
+}
+
+static int armv9_a710_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a710", NULL);
+}

arch/arm64/kernel/perf_event.c static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu) · line 1236

Quoted 10 lines

arch/arm64/kernel/perf_event.c +10 -0

+
+static int armv8_x1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_x1", NULL);
+}
+
+static int armv9_x2_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_x2", NULL);
+}

I wonder if it'd be better to do something like:

#define PMU_INIT_SIMPLE(name) \
static int name##_pmu_init(struct arm_pmu *cpu_pmu) \

{
	return armv8_pmu_init_nogroups(cpu_pmu, #name, NULL);		\
}

PMU_INIT_SIMPLE(armv9_cortex_a510)
PMU_INIT_SIMPLE(armv9_cortex_a710)
PMU_INIT_SIMPLE(armv8_xortex_x1)
PMU_INIT_SIMPLE(armv9_xortex_x2)

... and fix up the armv8_pmu_of_device_ids[] table to use the longer init names that results in?

Otherwise, looks good to me.

Thanks,
Mark.

Quoted 39 lines

arch/arm64/kernel/perf_event.c +17 -0

+
  static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
  {
  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL);

@@ -1225,6 +1245,16 @@ static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL);
  }
 
+static int armv9_n2_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_neoverse_n2", NULL);
+}
+
+static int armv8_v1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_v1", NULL);
+}
+
  static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
  {
  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",

@@ -1251,8 +1281,14 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
  	{.compatible = "arm,cortex-a76-pmu",	.data = armv8_a76_pmu_init},
  	{.compatible = "arm,cortex-a77-pmu",	.data = armv8_a77_pmu_init},
  	{.compatible = "arm,cortex-a78-pmu",	.data = armv8_a78_pmu_init},
+	{.compatible = "arm,cortex-a510-pmu",	.data = armv9_a510_pmu_init},
+	{.compatible = "arm,cortex-a710-pmu",	.data = armv9_a710_pmu_init},
+	{.compatible = "arm,cortex-x1-pmu",	.data = armv8_x1_pmu_init},
+	{.compatible = "arm,cortex-x2-pmu",	.data = armv9_x2_pmu_init},
  	{.compatible = "arm,neoverse-e1-pmu",	.data = armv8_e1_pmu_init},
  	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},
+	{.compatible = "arm,neoverse-n2-pmu",	.data = armv9_n2_pmu_init},
+	{.compatible = "arm,neoverse-v1-pmu",	.data = armv8_v1_pmu_init},
  	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},
  	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},
  	{},

Signature · 1 line

2.28.0.dirty

Convert the DSU binding to schema, as one does.

Signed-off-by Robin Murphy <[email protected]>

---
 .../devicetree/bindings/arm/arm-dsu-pmu.txt   | 27 ------------
 .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
 2 files changed, 41 insertions(+), 27 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
 create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml

Add bindings for the 2020 and 2021 cohorts of Cortex-A and Neoverse CPUs, now featuring their Cortex-X cousins as well.

Signed-off-by Robin Murphy <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
 Documentation/devicetree/bindings/arm/pmu.yaml  | 6 ++++++
 2 files changed, 12 insertions(+)

Convert the DSU binding to schema, as one does.

Signed-off-by Robin Murphy <[email protected]>

---
 .../devicetree/bindings/arm/arm-dsu-pmu.txt   | 27 ------------
 .../devicetree/bindings/perf/arm,dsu-pmu.yaml | 41 +++++++++++++++++++
 2 files changed, 41 insertions(+), 27 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
 create mode 100644 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml

Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt deleted +0 -27

deleted file mode 100644
index 6efabba530f1..000000000000
@@ -1,27 +0,0 @@
-* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
-
-ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
-with a shared L3 memory system, control logic and external interfaces to
-form a multicore cluster. The PMU enables to gather various statistics on
-the operations of the DSU. The PMU provides independent 32bit counters that
-can count any of the supported events, along with a 64bit cycle counter.
-The PMU is accessed via CPU system registers and has no MMIO component.
-
-** DSU PMU required properties:
-
-- compatible	: should be one of :
-
-		"arm,dsu-pmu"
-
-- interrupts	: Exactly 1 SPI must be listed.
-
-- cpus		: List of phandles for the CPUs connected to this DSU instance.
-
-
-** Example:
-
-dsu-pmu-0 {
-	compatible = "arm,dsu-pmu";
-	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
-	cpus = <&cpu_0>, <&cpu_1>;
-};

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml new file +14 -0

new file mode 100644
index 000000000000..b78b6b0fce66
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Arm Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
+
+maintainers:
+  - Suzuki K Poulose <[email protected]>
+  - Robin Murphy <[email protected]>
+
+description:

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml new file +13 -0

+
+  cpus:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minitems: 1
+    maxitems: 8
+    description: List of phandles for the CPUs connected to this DSU instance.
+
+required:
+  - compatible
+  - interrupts
+  - cpus
+
+additionalProperties: false

Signature · 1 line

2.28.0.dirty

DSU-110 is the newest and shiniest for Armv9. Its programmer's model is largely identical to the previous generation of DSUs, so we can treat it as compatible, but it does have a a handful of extra IMP-DEF PMU events to call its own. Thanks to the new notion of core complexes, the maximum number of supported CPUs goes up as well.

Signed-off-by Robin Murphy <[email protected]>

---
 Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml +0 -0

index b78b6b0fce66..b623520ad302 100644

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml +1 -1

   interrupts:
     items:

@@ -30,7 +34,7 @@ properties:
   cpus:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     minitems: 1
-    maxitems: 8
+    maxitems: 12
     description: List of phandles for the CPUs connected to this DSU instance.
 
 required:

Signature · 1 line

2.28.0.dirty

Quoted 16 lines · Robin Murphy

DSU-110 is the newest and shiniest for Armv9. Its programmer's model is largely identical to the previous generation of DSUs, so we can treat it as compatible, but it does have a a handful of extra IMP-DEF PMU events to call its own. Thanks to the new notion of core complexes, the maximum number of supported CPUs goes up as well.

Signed-off-by Robin Murphy <[email protected]>

---
  Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml | 8 ++++++--
  1 file changed, 6 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml +0 -0

index b78b6b0fce66..b623520ad302 100644

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml description: · line 24

Quoted 5 lines

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml +1 -1

@@ -21,7 +21,11 @@ description:
 
  properties:
    compatible:
-    const: "arm,dsu-pmu"
+    oneof:

'oneOf' and should be a list.

jsonschema is case sensitive yet the tools are silent on wrong case (but handled by dtschema).

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml description: · line 28

Quoted 4 lines

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml +4 -0

+      const: "arm,dsu-pmu"
+      items:
+        const: "arm,dsu-110-pmu"
+        const: "arm,dsu-pmu"

'items' needs to be a list here (Use '-').

Quoted 17 lines

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml +1 -1

    interrupts:
      items:

@@ -30,7 +34,7 @@ properties:
    cpus:
      $ref: /schemas/types.yaml#/definitions/phandle-array
      minitems: 1
-    maxitems: 8
+    maxitems: 12
      description: List of phandles for the CPUs connected to this DSU instance.
 
  required:

Signature · 1 line

2.28.0.dirty

Quoted 49 lines · Mark Rutland

Quoted 24 lines · Robin Murphy

Wire up the new DT compatibles so we can present appropriate PMU names to userspace for the latest and greatest CPUs.

Signed-off-by Robin Murphy <[email protected]>

---
  arch/arm64/kernel/perf_event.c | 36 ++++++++++++++++++++++++++++++++++
  1 file changed, 36 insertions(+)

arch/arm64/kernel/perf_event.c +9 -0

index 57720372da62..3fe4dcfc28d4 100644
@@ -1215,6 +1215,26 @@ static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
  	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
  }
+static int armv9_a510_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a510", NULL);
+}
+
+static int armv9_a710_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_a710", NULL);
+}

arch/arm64/kernel/perf_event.c static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu) · line 1235

Quoted 10 lines

arch/arm64/kernel/perf_event.c +10 -0

+
+static int armv8_x1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_x1", NULL);
+}
+
+static int armv9_x2_pmu_init(struct arm_pmu *cpu_pmu)
+{
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv9_cortex_x2", NULL);
+}

I wonder if it'd be better to do something like:

#define PMU_INIT_SIMPLE(name) \
static int name##_pmu_init(struct arm_pmu *cpu_pmu) \

{
	return armv8_pmu_init_nogroups(cpu_pmu, #name, NULL);		\
}

PMU_INIT_SIMPLE(armv9_cortex_a510)
PMU_INIT_SIMPLE(armv9_cortex_a710)
PMU_INIT_SIMPLE(armv8_xortex_x1)
PMU_INIT_SIMPLE(armv9_xortex_x2)

Quoted 2 lines

... and fix up the armv8_pmu_of_device_ids[] table to use the longer init names that results in?

Indeed I did ponder doing almost exactly that, but at that point I'd rather try refactoring a bit deeper to convert most of the arm_pmu init business to pure data, so I figured I'd chuck in the simple tweak to mitigate these new additions with minimal churn, then have a go at the bigger change in its own right.

The arm_pmu framework requires map_event to be non-NULL, so let armv8_pmu_init() treat NULL as a default value for the generic PMUv3 event map and simplify the boilerplate in the callers a bit.

Signed-off-by Robin Murphy <[email protected]>

---
 arch/arm64/kernel/perf_event.c | 32 +++++++++++---------------------
 1 file changed, 11 insertions(+), 21 deletions(-)

arch/arm64/kernel/perf_event.c +0 -0

index b4044469527e..57720372da62 100644

arch/arm64/kernel/perf_event.c +10 -20

@@ -1147,14 +1147,12 @@ static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
 
 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3", NULL);
 }
 
 static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34", NULL);
 }
 
 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)

@@ -1171,8 +1169,7 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
 
 static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55", NULL);
 }
 
 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)

@@ -1183,8 +1180,7 @@ static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
 
 static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65", NULL);
 }
 
 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)

@@ -1201,38 +1197,32 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
 
 static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75", NULL);
 }
 
 static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76", NULL);
 }
 
 static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77", NULL);
 }
 
 static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78", NULL);
 }
 
 static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1", NULL);
 }
 
 static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
 {
-	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
-				       armv8_pmuv3_map_event);
+	return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1", NULL);
 }
 
 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)

Signature · 1 line

2.28.0.dirty