riscv: dts: Miscellaneous fixes

PATCH In review Geert Uytterhoeven 3 participants 14 messages Dec 17, 2021 – Jan 9, 2022

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Geert Uytterhoeven

author

2021-12-17 12:49 UTC #0 lore raw

v3 cover riscv: dts: Miscellaneous fixes

Hi Paul, Palmer, Albert,

This patch series contains miscellaneous fixes for the DTS files for RISC-V platforms.

Changes compared to v2[1]:
- Add Reviewed-by, Tested-by.

Changes compared to v1[2]:
- Add Reviewed-by, Tested-by,
- Move mpfs refclk clock-frequency to board DTS,
- New patches "[PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node" and "[PATCH v2 11/11] riscv: dts: sifive:
fu540-c000: Fix PLIC node".

Thanks for applying!

[1] https://lore.kernel.org/r/[email protected]
[2] https://lore.kernel.org/r/[email protected]

Geert Uytterhoeven (11):
riscv: dts: canaan: Fix SPI FLASH node names
riscv: dts: canaan: Group tuples in interrupt properties
riscv: dts: microchip: mpfs: Drop empty chosen node
riscv: dts: microchip: mpfs: Fix PLIC node
riscv: dts: microchip: mpfs: Fix reference clock node
riscv: dts: microchip: mpfs: Fix clock controller node
riscv: dts: microchip: mpfs: Group tuples in interrupt properties
riscv: dts: sifive: Group tuples in interrupt properties
riscv: dts: sifive: Group tuples in register properties
riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
riscv: dts: sifive: fu540-c000: Fix PLIC node

 arch/riscv/boot/dts/canaan/k210.dtsi          | 23 +++----
 .../riscv/boot/dts/canaan/sipeed_maix_bit.dts |  2 +-
 .../boot/dts/canaan/sipeed_maix_dock.dts      |  2 +-
 arch/riscv/boot/dts/canaan/sipeed_maix_go.dts |  2 +-
 .../boot/dts/canaan/sipeed_maixduino.dts      |  2 +-
 .../microchip/microchip-mpfs-icicle-kit.dts   |  4 ++
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 60 ++++++++-----------
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 40 +++++++------
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi    | 14 ++---
 9 files changed, 72 insertions(+), 77 deletions(-)

Signature · 12 lines

2.25.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #10 lore raw

PATCH v3 9/11 riscv: dts: sifive: Group tuples in register properties

To improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets.

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

---
v3:
- No changes,

v2:
- Add Reviewed-by.

---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

arch/riscv/boot/dts/sifive/fu540-c000.dtsi +6 -6

index 0caca0ccf6711ded..e2efcf08210926f8 100644
@@ -196,8 +196,8 @@ i2c0: i2c@10030000 {
 		};
 		qspi0: spi@10040000 {
 			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
-			reg = <0x0 0x10040000 0x0 0x1000
-			       0x0 0x20000000 0x0 0x10000000>;
+			reg = <0x0 0x10040000 0x0 0x1000>,
+			      <0x0 0x20000000 0x0 0x10000000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <51>;
 			clocks = <&prci PRCI_CLK_TLCLK>;

@@ -207,8 +207,8 @@ qspi0: spi@10040000 {
 		};
 		qspi1: spi@10041000 {
 			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
-			reg = <0x0 0x10041000 0x0 0x1000
-			       0x0 0x30000000 0x0 0x10000000>;
+			reg = <0x0 0x10041000 0x0 0x1000>,
+			      <0x0 0x30000000 0x0 0x10000000>;
 			interrupt-parent = <&plic0>;
 			interrupts = <52>;
 			clocks = <&prci PRCI_CLK_TLCLK>;

@@ -230,8 +230,8 @@ eth0: ethernet@10090000 {
 			compatible = "sifive,fu540-c000-gem";
 			interrupt-parent = <&plic0>;
 			interrupts = <53>;
-			reg = <0x0 0x10090000 0x0 0x2000
-			       0x0 0x100a0000 0x0 0x1000>;
+			reg = <0x0 0x10090000 0x0 0x2000>,
+			      <0x0 0x100a0000 0x0 0x1000>;
 			local-mac-address = [00 00 00 00 00 00];
 			clock-names = "pclk", "hclk";
 			clocks = <&prci PRCI_CLK_GEMGXLPLL>,

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #3 lore raw

PATCH v3 3/11 riscv: dts: microchip: mpfs: Drop empty chosen node

In reply to Geert Uytterhoeven

It does not make sense to have an (empty) chosen node in an SoC-specific .dtsi, as chosen is meant for system-specific configuration. It is already provided in microchip-mpfs-icicle-kit.dts anyway.

Fixes 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

Tested-by Conor Dooley <[email protected]>

---
v3:
- Add Tested-by,

v2:
- Add Reviewed-by.

---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ---
 1 file changed, 3 deletions(-)

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +0 -3

index c9f6d205d2ba1a5e..794da883acb19256 100644
@@ -9,9 +9,6 @@ / {
 	model = "Microchip PolarFire SoC";
 	compatible = "microchip,mpfs";
 
-	chosen {
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #7 lore raw

PATCH v3 6/11 riscv: dts: microchip: mpfs: Fix clock controller node

In reply to Geert Uytterhoeven

Fix the device node for the clock controller:
- Remove bogus "reg-names" property,
- Remove unneeded "clock-output-names" property.

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

Tested-by Conor Dooley <[email protected]>

---
v3:
- Add Reviewed-by, Tested-by,

v2:
- New.

---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 9 ---------
 1 file changed, 9 deletions(-)

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +0 -9

index b372bc6459bf163a..d9c1dee3fb25beb8 100644
@@ -197,17 +197,8 @@ dma@3000000 {
 		clkcfg: clkcfg@20002000 {
 			compatible = "microchip,mpfs-clkcfg";
 			reg = <0x0 0x20002000 0x0 0x1000>;
-			reg-names = "mss_sysreg";
 			clocks = <&refclk>;
 			#clock-cells = <1>;
-			clock-output-names = "cpu", "axi", "ahb", "envm",	/* 0-3   */
-				 "mac0", "mac1", "mmc", "timer",		/* 4-7   */
-				"mmuart0", "mmuart1", "mmuart2", "mmuart3",	/* 8-11  */
-				"mmuart4", "spi0", "spi1", "i2c0",		/* 12-15 */
-				"i2c1", "can0", "can1", "usb",			/* 16-19 */
-				"rsvd", "rtc", "qspi", "gpio0",			/* 20-23 */
-				"gpio1", "gpio2", "ddrc", "fic0",		/* 24-27 */
-				"fic1", "fic2", "fic3", "athena", "cfm";	/* 28-32 */
 		};
 
 		serial0: serial@20000000 {

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #8 lore raw

PATCH v3 7/11 riscv: dts: microchip: mpfs: Group tuples in interrupt properties

In reply to Geert Uytterhoeven

To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped.

Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets.

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

Tested-by Conor Dooley <[email protected]>

---
v3:
- Add Tested-by,

v2:
- Add Reviewed-by.

---
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 31 ++++++++++---------
 1 file changed, 16 insertions(+), 15 deletions(-)

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +16 ~~-15~~

index d9c1dee3fb25beb8..869aaf0d5c066c9d 100644
@@ -158,18 +158,18 @@ cache-controller@2010000 {
 			cache-size = <2097152>;
 			cache-unified;
 			interrupt-parent = <&plic>;
-			interrupts = <1 2 3>;
+			interrupts = <1>, <2>, <3>;
 			reg = <0x0 0x2010000 0x0 0x1000>;
 		};
 
 		clint@2000000 {
 			compatible = "sifive,fu540-c000-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0xC000>;
-			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
-						&cpu1_intc 3 &cpu1_intc 7
-						&cpu2_intc 3 &cpu2_intc 7
-						&cpu3_intc 3 &cpu3_intc 7
-						&cpu4_intc 3 &cpu4_intc 7>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>;
 		};
 
 		plic: interrupt-controller@c000000 {

@@ -178,11 +178,11 @@ plic: interrupt-controller@c000000 {
 			#address-cells = <0>;
 			#interrupt-cells = <1>;
 			interrupt-controller;
-			interrupts-extended = <&cpu0_intc 11
-					&cpu1_intc 11 &cpu1_intc 9
-					&cpu2_intc 11 &cpu2_intc 9
-					&cpu3_intc 11 &cpu3_intc 9
-					&cpu4_intc 11 &cpu4_intc 9>;
+			interrupts-extended = <&cpu0_intc 11>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>;
 			riscv,ndev = <186>;
 		};

@@ -190,7 +190,8 @@ dma@3000000 {
 			compatible = "sifive,fu540-c000-pdma";
 			reg = <0x0 0x3000000 0x0 0x8000>;
 			interrupt-parent = <&plic>;
-			interrupts = <23 24 25 26 27 28 29 30>;
+			interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+				     <30>;
 			#dma-cells = <1>;
 		};

@@ -254,7 +255,7 @@ mmc: mmc@20008000 {
 			compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
 			reg = <0x0 0x20008000 0x0 0x1000>;
 			interrupt-parent = <&plic>;
-			interrupts = <88 89>;
+			interrupts = <88>, <89>;
 			clocks = <&clkcfg 6>;
 			max-frequency = <200000000>;
 			status = "disabled";

@@ -264,7 +265,7 @@ emac0: ethernet@20110000 {
 			compatible = "cdns,macb";
 			reg = <0x0 0x20110000 0x0 0x2000>;
 			interrupt-parent = <&plic>;
-			interrupts = <64 65 66 67>;
+			interrupts = <64>, <65>, <66>, <67>;
 			local-mac-address = [00 00 00 00 00 00];
 			clocks = <&clkcfg 4>, <&clkcfg 2>;
 			clock-names = "pclk", "hclk";

@@ -277,7 +278,7 @@ emac1: ethernet@20112000 {
 			compatible = "cdns,macb";
 			reg = <0x0 0x20112000 0x0 0x2000>;
 			interrupt-parent = <&plic>;
-			interrupts = <70 71 72 73>;
+			interrupts = <70>, <71>, <72>, <73>;
 			local-mac-address = [00 00 00 00 00 00];
 			clocks = <&clkcfg 5>, <&clkcfg 2>;
 			status = "disabled";

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #9 lore raw

PATCH v3 8/11 riscv: dts: sifive: Group tuples in interrupt properties

In reply to Geert Uytterhoeven

To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped.

Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets.

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

---
v3:
- No changes,

v2:
- Add Reviewed-by.

---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++----------
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++-------
 2 files changed, 18 insertions(+), 17 deletions(-)

arch/riscv/boot/dts/sifive/fu540-c000.dtsi +11 ~~-10~~

index 0655b5c4201d9f71..0caca0ccf6711ded 100644
@@ -145,12 +145,12 @@ plic0: interrupt-controller@c000000 {
 			reg = <0x0 0xc000000 0x0 0x4000000>;
 			riscv,ndev = <53>;
 			interrupt-controller;
-			interrupts-extended = <
-				&cpu0_intc 0xffffffff
-				&cpu1_intc 0xffffffff &cpu1_intc 9
-				&cpu2_intc 0xffffffff &cpu2_intc 9
-				&cpu3_intc 0xffffffff &cpu3_intc 9
-				&cpu4_intc 0xffffffff &cpu4_intc 9>;
+			interrupts-extended =
+				<&cpu0_intc 0xffffffff>,
+				<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+				<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+				<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+				<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
 		};
 		prci: clock-controller@10000000 {
 			compatible = "sifive,fu540-c000-prci";

@@ -170,7 +170,8 @@ dma: dma@3000000 {
 			compatible = "sifive,fu540-c000-pdma";
 			reg = <0x0 0x3000000 0x0 0x8000>;
 			interrupt-parent = <&plic0>;
-			interrupts = <23 24 25 26 27 28 29 30>;
+			interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+				     <30>;
 			#dma-cells = <1>;
 		};
 		uart1: serial@10011000 {

@@ -243,7 +244,7 @@ pwm0: pwm@10020000 {
 			compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
 			reg = <0x0 0x10020000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
-			interrupts = <42 43 44 45>;
+			interrupts = <42>, <43>, <44>, <45>;
 			clocks = <&prci PRCI_CLK_TLCLK>;
 			#pwm-cells = <3>;
 			status = "disabled";

@@ -252,7 +253,7 @@ pwm1: pwm@10021000 {
 			compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
 			reg = <0x0 0x10021000 0x0 0x1000>;
 			interrupt-parent = <&plic0>;
-			interrupts = <46 47 48 49>;
+			interrupts = <46>, <47>, <48>, <49>;
 			clocks = <&prci PRCI_CLK_TLCLK>;
 			#pwm-cells = <3>;
 			status = "disabled";

@@ -265,7 +266,7 @@ l2cache: cache-controller@2010000 {
 			cache-size = <2097152>;
 			cache-unified;
 			interrupt-parent = <&plic0>;
-			interrupts = <1 2 3>;
+			interrupts = <1>, <2>, <3>;
 			reg = <0x0 0x2010000 0x0 0x1000>;
 		};
 		gpio: gpio@10060000 {

arch/riscv/boot/dts/sifive/fu740-c000.dtsi +7 -7

index abbb960f90a00ac2..8464b0e3c88791e1 100644
@@ -147,12 +147,12 @@ plic0: interrupt-controller@c000000 {
 			reg = <0x0 0xc000000 0x0 0x4000000>;
 			riscv,ndev = <69>;
 			interrupt-controller;
-			interrupts-extended = <
-				&cpu0_intc 0xffffffff
-				&cpu1_intc 0xffffffff &cpu1_intc 9
-				&cpu2_intc 0xffffffff &cpu2_intc 9
-				&cpu3_intc 0xffffffff &cpu3_intc 9
-				&cpu4_intc 0xffffffff &cpu4_intc 9>;
+			interrupts-extended =
+				<&cpu0_intc 0xffffffff>,
+				<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+				<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+				<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+				<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
 		};
 		prci: clock-controller@10000000 {
 			compatible = "sifive,fu740-c000-prci";

@@ -273,7 +273,7 @@ ccache: cache-controller@2010000 {
 			cache-size = <2097152>;
 			cache-unified;
 			interrupt-parent = <&plic0>;
-			interrupts = <19 21 22 20>;
+			interrupts = <19>, <21>, <22>, <20>;
 			reg = <0x0 0x2010000 0x0 0x1000>;
 		};
 		gpio: gpio@10060000 {

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #12 lore raw

PATCH v3 11/11 riscv: dts: sifive: fu540-c000: Fix PLIC node

In reply to Geert Uytterhoeven

Fix the device node for the Platform-Level Interrupt Controller (PLIC):
- Add missing "#address-cells" property,
- Sort properties according to DT bindings.

Signed-off-by Geert Uytterhoeven <[email protected]>

---
v3:
- No changes,

v2:
- New.

---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/riscv/boot/dts/sifive/fu540-c000.dtsi +3 -2

index b1250c16816f5c9d..3eef52b1a59b5cb4 100644
@@ -140,10 +140,10 @@ soc {
 		compatible = "simple-bus";
 		ranges;
 		plic0: interrupt-controller@c000000 {
-			#interrupt-cells = <1>;
 			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-			riscv,ndev = <53>;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
 			interrupt-controller;
 			interrupts-extended =
 				<&cpu0_intc 0xffffffff>,

@@ -151,6 +151,7 @@ plic0: interrupt-controller@c000000 {
 				<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
 				<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
 				<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
+			riscv,ndev = <53>;
 		};
 		prci: clock-controller@10000000 {
 			compatible = "sifive,fu540-c000-prci";

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #1 lore raw

PATCH v3 1/11 riscv: dts: canaan: Fix SPI FLASH node names

In reply to Geert Uytterhoeven

"make dtbs_check":

arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$'
From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml

Fix this by renaming all SPI FLASH nodes to "flash".

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Damien Le Moal <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

Tested-by Damien Le Moal <[email protected]>

---
v3:
- No changes,

v2:
- Add Reviewed-by, Tested-by.

---
 arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts  | 2 +-
 arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
 arch/riscv/boot/dts/canaan/sipeed_maix_go.dts   | 2 +-
 arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts +1 -1

index 0bcaf35045e795ed..984872f3d3a9b9ea 100644
@@ -199,7 +199,7 @@ slot@0 {
 };
 
 &spi3 {
-	spi-flash@0 {
+	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <50000000>;

arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts +1 -1

index ac8a03f5867adbd0..7ba99b4da304218e 100644
@@ -201,7 +201,7 @@ slot@0 {
 };
 
 &spi3 {
-	spi-flash@0 {
+	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <50000000>;

arch/riscv/boot/dts/canaan/sipeed_maix_go.dts +1 -1

index 623998194bc18aab..be9b12c9b374acb3 100644
@@ -209,7 +209,7 @@ slot@0 {
 };
 
 &spi3 {
-	spi-flash@0 {
+	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <50000000>;

arch/riscv/boot/dts/canaan/sipeed_maixduino.dts +1 -1

index cf605ba0d67e43cd..031c0c28f8195777 100644
@@ -174,7 +174,7 @@ slot@0 {
 };
 
 &spi3 {
-	spi-flash@0 {
+	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <50000000>;

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #6 lore raw

PATCH v3 5/11 riscv: dts: microchip: mpfs: Fix reference clock node

In reply to Geert Uytterhoeven

"make dtbs_check" reports:

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml

Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous "clock-output-names" property.
Move the actual clock-frequency value to the board DTS, since it is not set until bitstream programming time.

Signed-off-by Geert Uytterhoeven <[email protected]>

Acked-by Krzysztof Kozlowski <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

Tested-by Conor Dooley <[email protected]>

---
v3:
- Add Reviewed-by, Tested-by,

v2:
- Add Acked-by,
- Move clock-frequency to board DTS.

---
 .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts |  4 ++++
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi    | 12 +++++-------
 2 files changed, 9 insertions(+), 7 deletions(-)

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +4 -0

index fc1e5869df1b9fc5..0c748ae1b0068df7 100644
@@ -35,6 +35,10 @@ memory@80000000 {
 	};
 };
 
+&refclk {
+	clock-frequency = <600000000>;
+};
+
 &serial0 {
 	status = "okay";
 };

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +5 -7

index ee59751544a0d3bc..b372bc6459bf163a 100644
@@ -139,6 +139,11 @@ cpu4_intc: interrupt-controller {
 		};
 	};
 
+	refclk: msspllclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -189,13 +194,6 @@ dma@3000000 {
 			#dma-cells = <1>;
 		};
 
-		refclk: refclk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <600000000>;
-			clock-output-names = "msspllclk";
-		};
-
 		clkcfg: clkcfg@20002000 {
 			compatible = "microchip,mpfs-clkcfg";
 			reg = <0x0 0x20002000 0x0 0x1000>;

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #11 lore raw

PATCH v3 10/11 riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values

In reply to Geert Uytterhoeven

"make dtbs_check":

arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected
From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed:
'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00']
'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00']
'sifive,fu540-c000' was expected
'sifive,fu740-c000' was expected
'sifive,fu540' was expected
'sifive,fu740' was expected
From schema: Documentation/devicetree/bindings/riscv/sifive.yaml

This happens because the "soc" subnode declares compatibility with "sifive,fu540-c000" and "sifive,fu540", while these are only intended for the root node.

Fix this by removing the bogus compatible values from the "soc" node.

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

---
v3:
- No changes,

v2:
- Add Reviewed-by.

---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/riscv/boot/dts/sifive/fu540-c000.dtsi +1 -1

index e2efcf08210926f8..b1250c16816f5c9d 100644
@@ -137,7 +137,7 @@ cpu4_intc: interrupt-controller {
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
-		compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+		compatible = "simple-bus";
 		ranges;
 		plic0: interrupt-controller@c000000 {
 			#interrupt-cells = <1>;

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #2 lore raw

PATCH v3 2/11 riscv: dts: canaan: Group tuples in interrupt properties

In reply to Geert Uytterhoeven

To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped.

Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets.

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Damien Le Moal <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

Tested-by Damien Le Moal <[email protected]>

---
v3:
- No changes,

v2:
- Add Reviewed-by, Tested-by.

---
 arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

arch/riscv/boot/dts/canaan/k210.dtsi +12 ~~-11~~

index 5e8ca8142482153b..56f57118c633b91a 100644
@@ -103,8 +103,8 @@ rom0: nvmem@1000 {
 		clint0: timer@2000000 {
 			compatible = "canaan,k210-clint", "sifive,clint0";
 			reg = <0x2000000 0xC000>;
-			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
-					      &cpu1_intc 3 &cpu1_intc 7>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>;
 		};
 
 		plic0: interrupt-controller@c000000 {

@@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 {
 			compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
 			reg = <0xC000000 0x4000000>;
 			interrupt-controller;
-			interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
 			riscv,ndev = <65>;
 		};

@@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 {
 			compatible = "canaan,k210-gpiohs", "sifive,gpio0";
 			reg = <0x38001000 0x1000>;
 			interrupt-controller;
-			interrupts = <34 35 36 37 38 39 40 41
-				      42 43 44 45 46 47 48 49
-				      50 51 52 53 54 55 56 57
-				      58 59 60 61 62 63 64 65>;
+			interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
+				     <41>, <42>, <43>, <44>, <45>, <46>, <47>,
+				     <48>, <49>, <50>, <51>, <52>, <53>, <54>,
+				     <55>, <56>, <57>, <58>, <59>, <60>, <61>,
+				     <62>, <63>, <64>, <65>;
 			gpio-controller;
 			ngpios = <32>;
 		};

@@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 {
 		dmac0: dma-controller@50000000 {
 			compatible = "snps,axi-dma-1.01a";
 			reg = <0x50000000 0x1000>;
-			interrupts = <27 28 29 30 31 32>;
+			interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
 			#dma-cells = <1>;
 			clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
 			clock-names = "core-clk", "cfgr-clk";

@@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 {
 			timer0: timer@502d0000 {
 				compatible = "snps,dw-apb-timer";
 				reg = <0x502D0000 0x100>;
-				interrupts = <14 15>;
+				interrupts = <14>, <15>;
 				clocks = <&sysclk K210_CLK_TIMER0>,
 					 <&sysclk K210_CLK_APB0>;
 				clock-names = "timer", "pclk";

@@ -326,7 +327,7 @@ timer0: timer@502d0000 {
 			timer1: timer@502e0000 {
 				compatible = "snps,dw-apb-timer";
 				reg = <0x502E0000 0x100>;
-				interrupts = <16 17>;
+				interrupts = <16>, <17>;
 				clocks = <&sysclk K210_CLK_TIMER1>,
 					 <&sysclk K210_CLK_APB0>;
 				clock-names = "timer", "pclk";

@@ -336,7 +337,7 @@ timer1: timer@502e0000 {
 			timer2: timer@502f0000 {
 				compatible = "snps,dw-apb-timer";
 				reg = <0x502F0000 0x100>;
-				interrupts = <18 19>;
+				interrupts = <18>, <19>;
 				clocks = <&sysclk K210_CLK_TIMER2>,
 					 <&sysclk K210_CLK_APB0>;
 				clock-names = "timer", "pclk";

Signature · 1 line

2.25.1

Geert Uytterhoeven

author

2021-12-17 12:49 UTC #5 lore raw

PATCH v3 4/11 riscv: dts: microchip: mpfs: Fix PLIC node

In reply to Geert Uytterhoeven

Fix the device node for the Platform-Level Interrupt Controller (PLIC):
- Add missing "#address-cells" property,
- Sort properties according to DT bindings.

Signed-off-by Geert Uytterhoeven <[email protected]>

Reviewed-by Krzysztof Kozlowski <[email protected]>

Reviewed-by Conor Dooley <[email protected]>

Tested-by Conor Dooley <[email protected]>

---
v3:
- Add Tested-by,

v2:
- Add Reviewed-by.

---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +3 -2

index 794da883acb19256..ee59751544a0d3bc 100644
@@ -168,16 +168,17 @@ &cpu3_intc 3 &cpu3_intc 7
 		};
 
 		plic: interrupt-controller@c000000 {
-			#interrupt-cells = <1>;
 			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-			riscv,ndev = <186>;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
 			interrupt-controller;
 			interrupts-extended = <&cpu0_intc 11
 					&cpu1_intc 11 &cpu1_intc 9
 					&cpu2_intc 11 &cpu2_intc 9
 					&cpu3_intc 11 &cpu3_intc 9
 					&cpu4_intc 11 &cpu4_intc 9>;
+			riscv,ndev = <186>;
 		};
 
 		dma@3000000 {

Signature · 1 line

2.25.1

Krzysztof Kozlowski

Reviewed-by on v3 3/11

2021-12-17 15:10 UTC #4 lore raw

Re: [PATCH v3 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node

In reply to Geert Uytterhoeven

Quoted 12 lines · Geert Uytterhoeven

It does not make sense to have an (empty) chosen node in an SoC-specific .dtsi, as chosen is meant for system-specific configuration. It is already provided in microchip-mpfs-icicle-kit.dts anyway.
Fixes 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by Geert Uytterhoeven <[email protected]>
Reviewed-by Conor Dooley <[email protected]>
Tested-by Conor Dooley <[email protected]>
---
v3:
- Add Tested-by,

Quoted 6 lines

v2:
- Add Reviewed-by.

---
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ---
 1 file changed, 3 deletions(-)

Reviewed-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

Palmer Dabbelt

maintainer

2022-01-09 18:21 UTC #13 lore raw

In reply to Geert Uytterhoeven

Quoted 8 lines · On Fri, 17 Dec 2021 04:49:21 PST (-0800), [email protected] wrote:

Hi Paul, Palmer, Albert,
This patch series contains miscellaneous fixes for the DTS files for RISC-V platforms.
Changes compared to v2[1]:
- Add Reviewed-by, Tested-by.

Quoted 8 lines

Changes compared to v1[2]:
- Add Reviewed-by, Tested-by,
- Move mpfs refclk clock-frequency to board DTS,
- New patches "[PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node" and "[PATCH v2 11/11] riscv: dts: sifive:
fu540-c000: Fix PLIC node".
Thanks for applying!

Thanks, these are on for-next.

Quoted 27 lines

[1] https://lore.kernel.org/r/[email protected]
[2] https://lore.kernel.org/r/[email protected]
Geert Uytterhoeven (11):
riscv: dts: canaan: Fix SPI FLASH node names
riscv: dts: canaan: Group tuples in interrupt properties
riscv: dts: microchip: mpfs: Drop empty chosen node
riscv: dts: microchip: mpfs: Fix PLIC node
riscv: dts: microchip: mpfs: Fix reference clock node
riscv: dts: microchip: mpfs: Fix clock controller node
riscv: dts: microchip: mpfs: Group tuples in interrupt properties
riscv: dts: sifive: Group tuples in interrupt properties
riscv: dts: sifive: Group tuples in register properties
riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
riscv: dts: sifive: fu540-c000: Fix PLIC node
 arch/riscv/boot/dts/canaan/k210.dtsi          | 23 +++----
 .../riscv/boot/dts/canaan/sipeed_maix_bit.dts |  2 +-
 .../boot/dts/canaan/sipeed_maix_dock.dts      |  2 +-
 arch/riscv/boot/dts/canaan/sipeed_maix_go.dts |  2 +-
 .../boot/dts/canaan/sipeed_maixduino.dts      |  2 +-
 .../microchip/microchip-mpfs-icicle-kit.dts   |  4 ++
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 60 ++++++++-----------
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 40 +++++++------
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi    | 14 ++---
 9 files changed, 72 insertions(+), 77 deletions(-)