lib/rwmmio/arm64: Add support to trace register reads/writes

Per discussion in [1], it was decided to move to using architecture independent/asm-generic IO memory barriers to have just one set of them and deprecate use of arm64 specific IO memory barriers in driver code. So replace current usage of __io_rmb()/__iowmb() in drivers to __io_ar()/__io_bw().

[1] https://lore.kernel.org/lkml/CAK8P3a0L2tLeF1Q0+0ijUxhGNaw+Z0fyPC1oW6_ELQfn0=i4iw@mail.gmail.com/

Cc Mathieu Poirier <[email protected]>

Cc Suzuki K Poulose <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

Reviewed-by Arnd Bergmann <[email protected]>

---
  drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++----
  drivers/hwtracing/coresight/coresight-etm4x.h      | 8 ++++----
  2 files changed, 8 insertions(+), 8 deletions(-)

drivers/hwtracing/coresight/coresight-etm4x-core.c +4 -4

index 7f416a12000e..81c0faf45b28 100644
@@ -98,7 +98,7 @@ u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  	}
 
  	if (!_relaxed)
-		__iormb(res);	/* Imitate the !relaxed I/O helpers */
+		__io_ar(res);	/* Imitate the !relaxed I/O helpers */
 
  	return res;
  }

@@ -106,7 +106,7 @@ u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
  {
  	if (!_relaxed)
-		__iowmb();	/* Imitate the !relaxed I/O helpers */
+		__io_bw();	/* Imitate the !relaxed I/O helpers */
  	if (!_64bit)
  		val &= GENMASK(31, 0);
 

@@ -130,7 +130,7 @@ static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  	}
 
  	if (!_relaxed)
-		__iormb(res);	/* Imitate the !relaxed I/O helpers */
+		__io_ar(res);	/* Imitate the !relaxed I/O helpers */
 
  	return res;
  }

@@ -138,7 +138,7 @@ static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
  static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
  {
  	if (!_relaxed)
-		__iowmb();	/* Imitate the !relaxed I/O helpers */
+		__io_bw();	/* Imitate the !relaxed I/O helpers */
  	if (!_64bit)
  		val &= GENMASK(31, 0);
 

drivers/hwtracing/coresight/coresight-etm4x.h +4 -4

index 3c4d69b096ca..f54698731582 100644
@@ -448,14 +448,14 @@
  #define etm4x_read32(csa, offset)					\
  	({								\
  		u32 __val = etm4x_relaxed_read32((csa), (offset));	\
-		__iormb(__val);						\
+		__io_ar(__val);						\
  		__val;							\
  	 })
 
  #define etm4x_read64(csa, offset)					\
  	({								\
  		u64 __val = etm4x_relaxed_read64((csa), (offset));	\
-		__iormb(__val);						\
+		__io_ar(__val);						\
  		__val;							\
  	 })
 

@@ -479,13 +479,13 @@
 
  #define etm4x_write32(csa, val, offset)					\
  	do {								\
-		__iowmb();						\
+		__io_bw();						\
  		etm4x_relaxed_write32((csa), (val), (offset));		\
  	} while (0)
 
  #define etm4x_write64(csa, val, offset)					\
  	do {								\
-		__iowmb();						\
+		__io_bw();						\
  		etm4x_relaxed_write64((csa), (val), (offset));		\
  	} while (0)
 

Hi,

Quoted 8 lines · Sai Prakash Ranjan

Per discussion in [1], it was decided to move to using architecture independent/asm-generic IO memory barriers to have just one set of them and deprecate use of arm64 specific IO memory barriers in driver code. So replace current usage of __io_rmb()/__iowmb() in drivers to __io_ar()/__io_bw().

[1] https://lore.kernel.org/lkml/CAK8P3a0L2tLeF1Q0+0ijUxhGNaw+Z0fyPC1oW6_ELQfn0=i4iw@mail.gmail.com/

Looking at the dis-assembly it looks like in effect they are slightly different for arm64.

i.e., before this patch we had

"dmb osh{ld/st}"

and after the patch we have :

"dsb {ld/st}"

Is this really what we want ? I don't think this is desirable.

Suzuki

Quoted 76 lines

Cc Mathieu Poirier <[email protected]>

Cc Suzuki K Poulose <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

Reviewed-by Arnd Bergmann <[email protected]>

---
  drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++---- drivers/hwtracing/coresight/coresight-etm4x.h      | 8 ++++----

  2 files changed, 8 insertions(+), 8 deletions(-)

drivers/hwtracing/coresight/coresight-etm4x-core.c +2 -2

index 7f416a12000e..81c0faf45b28 100644
@@ -98,7 +98,7 @@ u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
       }
         if (!_relaxed)
-        __iormb(res);    /* Imitate the !relaxed I/O helpers */
+        __io_ar(res);    /* Imitate the !relaxed I/O helpers */
         return res;
   }

@@ -106,7 +106,7 @@ u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
   void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
   {
       if (!_relaxed)
-        __iowmb();    /* Imitate the !relaxed I/O helpers */
+        __io_bw();    /* Imitate the !relaxed I/O helpers */
       if (!_64bit)
           val &= GENMASK(31, 0);
   @@ -130,7 +130,7 @@ static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)

      }
        if (!_relaxed)
-        __iormb(res);    /* Imitate the !relaxed I/O helpers */ +        __io_ar(res);    /* Imitate the !relaxed I/O helpers */ return res;
  }

drivers/hwtracing/coresight/coresight-etm4x-core.c +1 -1

@@ -138,7 +138,7 @@ static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
   static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
   {
       if (!_relaxed)
-        __iowmb();    /* Imitate the !relaxed I/O helpers */
+        __io_bw();    /* Imitate the !relaxed I/O helpers */
       if (!_64bit)
           val &= GENMASK(31, 0);

  diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 3c4d69b096ca..f54698731582 100644

drivers/hwtracing/coresight/coresight-etm4x.h +2 -2

@@ -448,14 +448,14 @@
   #define etm4x_read32(csa, offset)                    \
       ({                                \
           u32 __val = etm4x_relaxed_read32((csa), (offset)); \
-        __iormb(__val);                        \
+        __io_ar(__val);                        \
           __val;                            \
        })
     #define etm4x_read64(csa, offset)                    \
       ({                                \
           u64 __val = etm4x_relaxed_read64((csa), (offset)); \
-        __iormb(__val);                        \
+        __io_ar(__val);                        \
           __val;                            \
        })

  @@ -479,13 +479,13 @@
    #define etm4x_write32(csa, val, offset)                    \
      do {                                \
-        __iowmb();                        \
+        __io_bw();                        \
          etm4x_relaxed_write32((csa), (val), (offset)); \
      } while (0)
    #define etm4x_write64(csa, val, offset)                    \
      do {                                \
-        __iowmb();                        \
+        __io_bw();                        \
          etm4x_relaxed_write64((csa), (val), (offset)); \
      } while (0)

Hi Suzuki,

Quoted 20 lines · Suzuki K Poulose

Hi,

Quoted 9 lines · Sai Prakash Ranjan

Per discussion in [1], it was decided to move to using architecture independent/asm-generic IO memory barriers to have just one set of them and deprecate use of arm64 specific IO memory barriers in driver code. So replace current usage of __io_rmb()/__iowmb() in drivers to __io_ar()/__io_bw().

[1] https://lore.kernel.org/lkml/CAK8P3a0L2tLeF1Q0+0ijUxhGNaw+Z0fyPC1oW6_ELQfn0=i4iw@mail.gmail.com/

Looking at the dis-assembly it looks like in effect they are slightly different for arm64.

i.e., before this patch we had

"dmb osh{ld/st}"

Quoted 8 lines

and after the patch we have :

"dsb {ld/st}"

Is this really what we want ? I don't think this is desirable.

Suzuki

No, this is not supposed to happen and I do not see how it could happen. __io_ar() is defined as __iormb() and __io_bw() is __iowmb().

I checked the disassembly in both case with MMIO trace off/on with __etm4_cpu_save() as below and saw the same number of "dmb"s.

aarch64-linux-gnu-gdb -batch -ex "disassemble/rs __etm4_cpu_save" vmlinux-without-mmio aarch64-linux-gnu-gdb -batch -ex "disassemble/rs __etm4_cpu_save" vmlinux-with-mmio

Can you tell me how are you validating if I am missing something?

Quoted 40 lines · Sai Prakash Ranjan

Hi Suzuki,

Quoted 19 lines · Suzuki K Poulose

Hi,

Quoted 8 lines · Sai Prakash Ranjan

Per discussion in [1], it was decided to move to using architecture independent/asm-generic IO memory barriers to have just one set of them and deprecate use of arm64 specific IO memory barriers in driver code. So replace current usage of __io_rmb()/__iowmb() in drivers to __io_ar()/__io_bw().

[1] https://lore.kernel.org/lkml/CAK8P3a0L2tLeF1Q0+0ijUxhGNaw+Z0fyPC1oW6_ELQfn0=i4iw@mail.gmail.com/

Looking at the dis-assembly it looks like in effect they are slightly different for arm64.

i.e., before this patch we had

"dmb osh{ld/st}"

Quoted 8 lines

and after the patch we have :

"dsb {ld/st}"

Is this really what we want ? I don't think this is desirable.

Suzuki

No, this is not supposed to happen and I do not see how it could happen. __io_ar() is defined as __iormb() and __io_bw() is __iowmb().

I checked the disassembly in both case with MMIO trace off/on with __etm4_cpu_save() as below and saw the same number of "dmb"s.

aarch64-linux-gnu-gdb -batch -ex "disassemble/rs __etm4_cpu_save" vmlinux-without-mmio aarch64-linux-gnu-gdb -batch -ex "disassemble/rs __etm4_cpu_save" vmlinux-with-mmio

Quoted 1 line

Can you tell me how are you validating if I am missing something?

Apologies, I was missing the patch in this series, which adds the arm64 definition for __io_ar/__io_bw. (hint: Please Cc the affected subsystem in the Cover letter for the series, so we know what the intention of the changes are).

With the patch1, yes this makes sense to me. Otherwise, __io_ar() is default to rmb() which implies dsb ld.

With that said,

Reviewed-by Suzuki K Poulose <[email protected]>

From: Prasad Sodagudi <[email protected]>

Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors are typically used to read/write from/to memory mapped registers and can cause hangs or some undefined behaviour in following few cases,

* If the access to the register space is unclocked, for example: if there is an access to multimedia(MM) block registers without MM clocks.

* If the register space is protected and not set to be accessible from non-secure world, for example: only EL3 (EL: Exception level) access is allowed and any EL2/EL1 access is forbidden.

* If xPU(memory/register protection units) is controlling access to certain memory/register space for specific clients.

and more...

Such cases usually results in instant reboot/SErrors/NOC or interconnect hangs and tracing these register accesses can be very helpful to debug such issues during initial development stages and also in later stages.

So use ftrace trace events to log such MMIO register accesses which provides rich feature set such as early enablement of trace events, filtering capability, dumping ftrace logs on console and many more.

Sample output:

rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610

Signed-off-by Prasad Sodagudi <[email protected]>

Co-developed-by Sai Prakash Ranjan <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
  arch/Kconfig                  |  3 ++
  arch/arm64/Kconfig            |  1 +
  include/trace/events/rwmmio.h | 97 +++++++++++++++++++++++++++++++++++
  lib/Kconfig                   |  7 +++
  lib/Makefile                  |  2 +
  lib/trace_readwrite.c         | 47 +++++++++++++++++
  6 files changed, 157 insertions(+)

create mode 100644 include/trace/events/rwmmio.h create mode 100644 lib/trace_readwrite.c

arch/Kconfig +3 -0

index 31c4fdc4a4ba..5e7aa17ed609 100644
@@ -1369,6 +1369,9 @@ config ARCH_HAS_ELFCORE_COMPAT
  config ARCH_HAS_PARANOID_L1D_FLUSH
  	bool
 
+config ARCH_HAVE_TRACE_MMIO_ACCESS
+	bool
+
  config DYNAMIC_SIGFRAME
  	bool
 

arch/arm64/Kconfig +1 -0

index 20ea89d9ac2f..926e1a252b6f 100644
@@ -48,6 +48,7 @@ config ARM64
  	select ARCH_HAS_ZONE_DMA_SET if EXPERT
  	select ARCH_HAVE_ELF_PROT
  	select ARCH_HAVE_NMI_SAFE_CMPXCHG
+	select ARCH_HAVE_TRACE_MMIO_ACCESS
  	select ARCH_INLINE_READ_LOCK if !PREEMPTION
  	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
  	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION

include/trace/events/rwmmio.h new file +97 -0

new file mode 100644
index 000000000000..82edee9bf716
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM rwmmio
+
+#if !defined(_TRACE_RWMMIO_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_RWMMIO_H
+
+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(rwmmio_rw_template,
+
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+
+	TP_ARGS(caller, val, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u64, val)
+		__field(u8, width)
+	),
+
+	TP_fast_assign(
+		__entry->caller = caller;
+		__entry->val = val;
+		__entry->addr = (unsigned long)(void *)addr;
+		__entry->width = width;
+	),
+
+	TP_printk("%pS width=%d val=%#llx addr=%#lx",
+		(void *)(unsigned long)__entry->caller, __entry->width,
+		__entry->val, __entry->addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_write,
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+	TP_ARGS(caller, val, width, addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write,
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+	TP_ARGS(caller, val, width, addr)
+);
+
+TRACE_EVENT(rwmmio_read,
+
+	TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr),
+
+	TP_ARGS(caller, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u8, width)
+	),
+
+	TP_fast_assign(
+		__entry->caller = caller;
+		__entry->addr = (unsigned long)(void *)addr;
+		__entry->width = width;
+	),
+
+	TP_printk("%pS width=%d addr=%#lx",
+		 (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr)
+);
+
+TRACE_EVENT(rwmmio_post_read,
+
+	TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr),
+
+	TP_ARGS(caller, val, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u64, val)
+		__field(u8, width)
+	),
+
+	TP_fast_assign(
+		__entry->caller = caller;
+		__entry->val = val;
+		__entry->addr = (unsigned long)(void *)addr;
+		__entry->width = width;
+	),
+
+	TP_printk("%pS width=%d val=%#llx addr=%#lx",
+		 (void *)(unsigned long)__entry->caller, __entry->width,
+		 __entry->val, __entry->addr)
+);
+
+#endif /* _TRACE_RWMMIO_H */
+
+#include <trace/define_trace.h>

lib/Kconfig +7 -0

index 087e06b4cdfd..5e2fd075724f 100644
@@ -118,6 +118,13 @@ config INDIRECT_IOMEM_FALLBACK
  	  mmio accesses when the IO memory address is not a registered
  	  emulated region.
 
+config TRACE_MMIO_ACCESS
+	bool "Register read/write tracing"
+	depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS
+	help
+	  Create tracepoints for MMIO read/write operations. These trace events
+	  can be used for logging all MMIO read/write operations.
+
  source "lib/crypto/Kconfig"
 
  config CRC_CCITT

lib/Makefile +2 -0

index 6b9ffc1bd1ee..3df7d24e65d2 100644
@@ -151,6 +151,8 @@ lib-y += logic_pio.o
 
  lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o
 
+obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o
+
  obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o
 
  obj-$(CONFIG_BTREE) += btree.o

lib/trace_readwrite.c new file +37 -0

new file mode 100644
index 000000000000..88637038b30c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Register read and write tracepoints
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/ftrace.h>
+#include <linux/module.h>
+#include <asm-generic/io.h>
+
+#define CREATE_TRACE_POINTS
+#include <trace/events/rwmmio.h>
+
+#ifdef CONFIG_TRACE_MMIO_ACCESS
+void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+		    unsigned long caller_addr)
+{
+	trace_rwmmio_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write);
+
+void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+			 unsigned long caller_addr)
+{
+	trace_rwmmio_post_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write);
+
+void log_read_mmio(u8 width, const volatile void __iomem *addr,
+		   unsigned long caller_addr)
+{
+	trace_rwmmio_read(caller_addr, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_read_mmio);

Quoted 245 lines · Sai Prakash Ranjan

From: Prasad Sodagudi <[email protected]>

Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors are typically used to read/write from/to memory mapped registers and can cause hangs or some undefined behaviour in following few cases,

* If the access to the register space is unclocked, for example: if there is an access to multimedia(MM) block registers without MM clocks.

* If the register space is protected and not set to be accessible from non-secure world, for example: only EL3 (EL: Exception level) access is allowed and any EL2/EL1 access is forbidden.

* If xPU(memory/register protection units) is controlling access to certain memory/register space for specific clients.

and more...

Such cases usually results in instant reboot/SErrors/NOC or interconnect hangs and tracing these register accesses can be very helpful to debug such issues during initial development stages and also in later stages.

So use ftrace trace events to log such MMIO register accesses which provides rich feature set such as early enablement of trace events, filtering capability, dumping ftrace logs on console and many more.

Sample output:

rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610

Signed-off-by Prasad Sodagudi <[email protected]>

Co-developed-by Sai Prakash Ranjan <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
  arch/Kconfig                  |  3 ++
  arch/arm64/Kconfig            |  1 + include/trace/events/rwmmio.h | 97 +++++++++++++++++++++++++++++++++++ lib/Kconfig                   |  7 +++
  lib/Makefile                  |  2 +
  lib/trace_readwrite.c         | 47 +++++++++++++++++

  6 files changed, 157 insertions(+)

  create mode 100644 include/trace/events/rwmmio.h create mode 100644 lib/trace_readwrite.c

arch/Kconfig +0 -0

index 31c4fdc4a4ba..5e7aa17ed609 100644
@@ -1369,6 +1369,9 @@ config ARCH_HAS_ELFCORE_COMPAT

  config ARCH_HAS_PARANOID_L1D_FLUSH
      bool
  +config ARCH_HAVE_TRACE_MMIO_ACCESS
+    bool
+
  config DYNAMIC_SIGFRAME
      bool
  diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 20ea89d9ac2f..926e1a252b6f 100644

arch/arm64/Kconfig +0 -0

@@ -48,6 +48,7 @@ config ARM64

      select ARCH_HAS_ZONE_DMA_SET if EXPERT select ARCH_HAVE_ELF_PROT
      select ARCH_HAVE_NMI_SAFE_CMPXCHG
+    select ARCH_HAVE_TRACE_MMIO_ACCESS select ARCH_INLINE_READ_LOCK if !PREEMPTION select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION

include/trace/events/rwmmio.h new file +97 -0

new file mode 100644
index 000000000000..82edee9bf716
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM rwmmio
+
+#if !defined(_TRACE_RWMMIO_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_RWMMIO_H
+
+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(rwmmio_rw_template,
+
+    TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+
+    TP_ARGS(caller, val, width, addr),
+
+    TP_STRUCT__entry(
+        __field(unsigned long, caller)
+        __field(unsigned long, addr)
+        __field(u64, val)
+        __field(u8, width)
+    ),
+
+    TP_fast_assign(
+        __entry->caller = caller;
+        __entry->val = val;
+        __entry->addr = (unsigned long)(void *)addr;
+        __entry->width = width;
+    ),
+
+    TP_printk("%pS width=%d val=%#llx addr=%#lx",
+        (void *)(unsigned long)__entry->caller, __entry->width,
+        __entry->val, __entry->addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_write,
+    TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+    TP_ARGS(caller, val, width, addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write,
+    TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+    TP_ARGS(caller, val, width, addr)
+);
+
+TRACE_EVENT(rwmmio_read,
+
+    TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr),
+
+    TP_ARGS(caller, width, addr),
+
+    TP_STRUCT__entry(
+        __field(unsigned long, caller)
+        __field(unsigned long, addr)
+        __field(u8, width)
+    ),
+
+    TP_fast_assign(
+        __entry->caller = caller;
+        __entry->addr = (unsigned long)(void *)addr;
+        __entry->width = width;
+    ),
+
+    TP_printk("%pS width=%d addr=%#lx",
+         (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr)
+);
+
+TRACE_EVENT(rwmmio_post_read,
+
+    TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr),
+
+    TP_ARGS(caller, val, width, addr),
+
+    TP_STRUCT__entry(
+        __field(unsigned long, caller)
+        __field(unsigned long, addr)
+        __field(u64, val)
+        __field(u8, width)
+    ),
+
+    TP_fast_assign(
+        __entry->caller = caller;
+        __entry->val = val;
+        __entry->addr = (unsigned long)(void *)addr;
+        __entry->width = width;
+    ),
+
+    TP_printk("%pS width=%d val=%#llx addr=%#lx",
+         (void *)(unsigned long)__entry->caller, __entry->width,
+         __entry->val, __entry->addr)
+);
+
+#endif /* _TRACE_RWMMIO_H */
+
+#include <trace/define_trace.h>

lib/Kconfig +0 -0

index 087e06b4cdfd..5e2fd075724f 100644
@@ -118,6 +118,13 @@ config INDIRECT_IOMEM_FALLBACK

        mmio accesses when the IO memory address is not a registered emulated region.
  +config TRACE_MMIO_ACCESS
+    bool "Register read/write tracing"
+    depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS
+    help
+      Create tracepoints for MMIO read/write operations. These trace events +      can be used for logging all MMIO read/write operations.
+
  source "lib/crypto/Kconfig"
    config CRC_CCITT

lib/Makefile +0 -0

index 6b9ffc1bd1ee..3df7d24e65d2 100644
@@ -151,6 +151,8 @@ lib-y += logic_pio.o

    lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o +obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o +
  obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o obj-$(CONFIG_BTREE) += btree.o

lib/trace_readwrite.c new file +37 -0

new file mode 100644
index 000000000000..88637038b30c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Register read and write tracepoints
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/ftrace.h>
+#include <linux/module.h>
+#include <asm-generic/io.h>
+
+#define CREATE_TRACE_POINTS
+#include <trace/events/rwmmio.h>
+
+#ifdef CONFIG_TRACE_MMIO_ACCESS
+void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+            unsigned long caller_addr)
+{
+    trace_rwmmio_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write);
+
+void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+             unsigned long caller_addr)
+{
+    trace_rwmmio_post_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write);
+
+void log_read_mmio(u8 width, const volatile void __iomem *addr,
+           unsigned long caller_addr)
+{
+    trace_rwmmio_read(caller_addr, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_read_mmio);

lib/trace_readwrite.c line 47

Quoted 10 lines

lib/trace_readwrite.c new file +10 -0

+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read);
+
+void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
+            unsigned long caller_addr)
+{
+    trace_rwmmio_post_read(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_read_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read);
+#endif /* CONFIG_TRACE_MMIO_ACCESS */

Hi Steve,

Could you please review this patch, it is the main one left for this series to get merged. All your previous review comments have been incorporated, you can find them in  the cover letter changelog.

Thanks,
Sai

include/trace/events/rwmmio.h new file +14 -0

+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(rwmmio_rw_template,
+
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+
+	TP_ARGS(caller, val, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u64, val)
+		__field(u8, width)
+	),

include/trace/events/rwmmio.h new file +23 -0

+		__entry->val, __entry->addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_write,
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+	TP_ARGS(caller, val, width, addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write,
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+	TP_ARGS(caller, val, width, addr)
+);
+
+TRACE_EVENT(rwmmio_read,
+
+	TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr),
+
+	TP_ARGS(caller, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u8, width)

include/trace/events/rwmmio.h new file +14 -0

+);
+
+TRACE_EVENT(rwmmio_post_read,
+
+	TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr),
+
+	TP_ARGS(caller, val, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u64, val)
+		__field(u8, width)
+	),

include/trace/events/rwmmio.h new file +6 -0

+		 __entry->val, __entry->addr)
+);
+
+#endif /* _TRACE_RWMMIO_H */
+
+#include <trace/define_trace.h>

lib/Kconfig +7 -0

index 087e06b4cdfd..5e2fd075724f 100644
@@ -118,6 +118,13 @@ config INDIRECT_IOMEM_FALLBACK
 	  mmio accesses when the IO memory address is not a registered
 	  emulated region.
 
+config TRACE_MMIO_ACCESS
+	bool "Register read/write tracing"
+	depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS
+	help
+	  Create tracepoints for MMIO read/write operations. These trace events
+	  can be used for logging all MMIO read/write operations.
+
 source "lib/crypto/Kconfig"
 
 config CRC_CCITT

lib/Makefile +2 -0

index 6b9ffc1bd1ee..3df7d24e65d2 100644
@@ -151,6 +151,8 @@ lib-y += logic_pio.o
 
 lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o
 
+obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o
+
 obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o
 
 obj-$(CONFIG_BTREE) += btree.o

lib/trace_readwrite.c new file +6 -0

new file mode 100644
index 000000000000..88637038b30c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Register read and write tracepoints
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */

lib/trace_readwrite.c new file +31 -0

+		    unsigned long caller_addr)
+{
+	trace_rwmmio_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write);
+
+void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+			 unsigned long caller_addr)
+{
+	trace_rwmmio_post_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write);
+
+void log_read_mmio(u8 width, const volatile void __iomem *addr,
+		   unsigned long caller_addr)
+{
+	trace_rwmmio_read(caller_addr, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_read_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read);
+
+void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
+			unsigned long caller_addr)
+{
+	trace_rwmmio_post_read(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_read_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read);
+#endif /* CONFIG_TRACE_MMIO_ACCESS */

Quoted 18 lines · On Wed, 4 May 2022 16:58:24 +0530 Sai Prakash Ranjan…

include/trace/events/rwmmio.h new file +18 -0

+#include <linux/tracepoint.h>
+
+DECLARE_EVENT_CLASS(rwmmio_rw_template,
+
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+
+	TP_ARGS(caller, val, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u64, val)
+		__field(u8, width)
+	),
+
+	TP_fast_assign(
+		__entry->caller = caller;
+		__entry->val = val;

include/trace/events/rwmmio.h line 34

Quoted 6 lines

include/trace/events/rwmmio.h new file +6 -0

+		__entry->addr = (unsigned long)(void *)addr;
+		__entry->width = width;
+	),
+
+	TP_printk("%pS width=%d val=%#llx addr=%#lx",
+		(void *)(unsigned long)__entry->caller, __entry->width,

__entry->caller is already defined as "unsigned long", why the extra typecast?

Quoted 27 lines

include/trace/events/rwmmio.h new file +27 -0

+		__entry->val, __entry->addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_write,
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+	TP_ARGS(caller, val, width, addr)
+);
+
+DEFINE_EVENT(rwmmio_rw_template, rwmmio_post_write,
+	TP_PROTO(unsigned long caller, u64 val, u8 width, volatile void __iomem *addr),
+	TP_ARGS(caller, val, width, addr)
+);
+
+TRACE_EVENT(rwmmio_read,
+
+	TP_PROTO(unsigned long caller, u8 width, const volatile void __iomem *addr),
+
+	TP_ARGS(caller, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u8, width)
+	),
+
+	TP_fast_assign(
+		__entry->caller = caller;

include/trace/events/rwmmio.h line 67

Quoted 6 lines

include/trace/events/rwmmio.h new file +6 -0

+		__entry->addr = (unsigned long)(void *)addr;
+		__entry->width = width;
+	),
+
+	TP_printk("%pS width=%d addr=%#lx",
+		 (void *)(unsigned long)__entry->caller, __entry->width, __entry->addr)

Same here.

Quoted 17 lines

include/trace/events/rwmmio.h new file +17 -0

+);
+
+TRACE_EVENT(rwmmio_post_read,
+
+	TP_PROTO(unsigned long caller, u64 val, u8 width, const volatile void __iomem *addr),
+
+	TP_ARGS(caller, val, width, addr),
+
+	TP_STRUCT__entry(
+		__field(unsigned long, caller)
+		__field(unsigned long, addr)
+		__field(u64, val)
+		__field(u8, width)
+	),
+
+	TP_fast_assign(
+		__entry->caller = caller;

include/trace/events/rwmmio.h line 34

Quoted 7 lines

include/trace/events/rwmmio.h new file +7 -0

+		__entry->val = val;
+		__entry->addr = (unsigned long)(void *)addr;
+		__entry->width = width;
+	),
+
+	TP_printk("%pS width=%d val=%#llx addr=%#lx",
+		 (void *)(unsigned long)__entry->caller, __entry->width,

And here.

Quoted 53 lines

include/trace/events/rwmmio.h new file +6 -0

+		 __entry->val, __entry->addr)
+);
+
+#endif /* _TRACE_RWMMIO_H */
+
+#include <trace/define_trace.h>

lib/Kconfig +7 -0

index 087e06b4cdfd..5e2fd075724f 100644
@@ -118,6 +118,13 @@ config INDIRECT_IOMEM_FALLBACK
  	  mmio accesses when the IO memory address is not a registered
  	  emulated region.
 
+config TRACE_MMIO_ACCESS
+	bool "Register read/write tracing"
+	depends on TRACING && ARCH_HAVE_TRACE_MMIO_ACCESS
+	help
+	  Create tracepoints for MMIO read/write operations. These trace events
+	  can be used for logging all MMIO read/write operations.
+
  source "lib/crypto/Kconfig"
 
  config CRC_CCITT

lib/Makefile +2 -0

index 6b9ffc1bd1ee..3df7d24e65d2 100644
@@ -151,6 +151,8 @@ lib-y += logic_pio.o
 
  lib-$(CONFIG_INDIRECT_IOMEM) += logic_iomem.o
 
+obj-$(CONFIG_TRACE_MMIO_ACCESS) += trace_readwrite.o
+
  obj-$(CONFIG_GENERIC_HWEIGHT) += hweight.o
 
  obj-$(CONFIG_BTREE) += btree.o

lib/trace_readwrite.c new file +10 -0

new file mode 100644
index 000000000000..88637038b30c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Register read and write tracepoints
+ *
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/ftrace.h>
+#include <linux/module.h>
+#include <asm-generic/io.h>

lib/trace_readwrite.c line 16

Quoted 6 lines

lib/trace_readwrite.c new file +6 -0

+
+#define CREATE_TRACE_POINTS
+#include <trace/events/rwmmio.h>
+
+#ifdef CONFIG_TRACE_MMIO_ACCESS
+void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,

Where's the header file that defines these functions? I would think it should be in this patch as well.

-- Steve

Quoted 31 lines

lib/trace_readwrite.c new file +31 -0

+		    unsigned long caller_addr)
+{
+	trace_rwmmio_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_write);
+
+void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
+			 unsigned long caller_addr)
+{
+	trace_rwmmio_post_write(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_write_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_write);
+
+void log_read_mmio(u8 width, const volatile void __iomem *addr,
+		   unsigned long caller_addr)
+{
+	trace_rwmmio_read(caller_addr, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_read_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_read);
+
+void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
+			unsigned long caller_addr)
+{
+	trace_rwmmio_post_read(caller_addr, val, width, addr);
+}
+EXPORT_SYMBOL_GPL(log_post_read_mmio);
+EXPORT_TRACEPOINT_SYMBOL_GPL(rwmmio_post_read);
+#endif /* CONFIG_TRACE_MMIO_ACCESS */

Hi Steve,

Quoted 3 lines · Steven Rostedt

Quoted 1 line

+        (void *)(unsigned long)__entry->caller, __entry->width,

__entry->caller is already defined as "unsigned long", why the extra typecast?

I remember seeing compilation errors without this change in early versions of the series. Let me check this again.

Generic MMIO read/write i.e., __raw_{read,write}{b,l,w,q} accessors are typically used to read/write from/to memory mapped registers and can cause hangs or some undefined behaviour in following cases,

* If the access to the register space is unclocked, for example: if there is an access to multimedia(MM) block registers without MM clocks.

* If the register space is protected and not set to be accessible from non-secure world, for example: only EL3 (EL: Exception level) access is allowed and any EL2/EL1 access is forbidden.

* If xPU(memory/register protection units) is controlling access to certain memory/register space for specific clients.

and more...

Such cases usually results in instant reboot/SErrors/NOC or interconnect hangs and tracing these register accesses can be very helpful to debug such issues during initial development stages and also in later stages.

So use ftrace trace events to log such MMIO register accesses which provides rich feature set such as early enablement of trace events, filtering capability, dumping ftrace logs on console and many more.

Sample output:

rwmmio_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_post_write: __qcom_geni_serial_console_write+0x160/0x1e0 width=32 val=0xa0d5d addr=0xfffffbfffdbff700
rwmmio_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 addr=0xfffffbfffdbff610
rwmmio_post_read: qcom_geni_serial_poll_bit+0x94/0x138 width=32 val=0x0 addr=0xfffffbfffdbff610

This series is a follow-up for the series [1] and a recent series [2] making use of both.

[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/

Note in v4 version, Arnd suggested to benchmark and compare size with callback based implementation, please see [3] for more details on that with brief comparison below.

**Inline version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**

$ size vmlinux
    text           data             bss     dec             hex         filename
  23884219        14284468         532568 38701255        24e88c7        vmlinux

**Callback version with CONFIG_FTRACE=y and CONFIG_TRACE_MMIO_ACCESS=y**

$ size vmlinux
     text          data             bss     dec             hex        filename
  24108179        14279596         532568 38920343        251e097       vmlinux

$ ./scripts/bloat-o-meter inline-vmlinux callback-vmlinux
add/remove: 8/3 grow/shrink: 4889/89 up/down: 242244/-11564 (230680)
Total: Before=25812612, After=26043292, chg +0.89%

[3] https://lore.kernel.org/lkml/[email protected]/

Changes in v14:
* Add more description to disabling MMIO traces in geni serial drivers (Steve).

Changes in v13:
* Remove the copyright update as one line change doesn't warrant it (Greg and Lawyers :))
* Update the comment about disabling MMIO traces in geni se and uart drivers.
* Add description for the build time flag to asm-generic/io.h.

Changes in v12:
* Split the generic flag addition patch (Greg).
* Move the flag from makefile to driver .c file (Greg).

Changes in v11:
* Use unsigned long for caller ip and current ip addr (Steven Rostedt).
* Include review tags from Arnd.

Changes in v10:
* Use GENMASK(31, 0) for -Woverflow warning in irqchip tegra driver (Marc).
* Convert ETM4x ARM64 driver to use asm-generic IO memory barriers (Catalin).
* Collect ack from Catalin for arm64 change.

Changes in v9:
* Use TRACE_EVENT_CLASS for rwmmio_write and post_write (Steven Rostedt).

Changes in v8:
* Fix build error reported by kernel test robot.

Changes in v7:
* Use lib/ instead of kernel/trace/ based on review comment by Steven Rostedt.

Changes in v6:
* Implemented suggestions by Arnd Bergmann:
- Use arch independent IO barriers in arm64/asm
- Add ARCH_HAVE_TRACE_MMIO_ACCESS
- Add post read and post write logging support
- Remove tracepoint_active check
* Fix build error reported by kernel test robot.

Changes in v5:
* Move arm64 to use asm-generic provided high level MMIO accessors (Arnd).
* Add inline logging for MMIO relaxed and non-relaxed accessors.
* Move nVHE KVM comment to makefile (Marc).
* Fix overflow warning due to switch to inline accessors instead of macro.
* Modify trace event field to include caller and parent details for more detailed logs.

Changes in v4:
* Drop dynamic debug based filter support since that will be developed later with the help from Steven (Ftrace maintainer).
* Drop value passed to writel as it is causing hangs when tracing is enabled.
* Code cleanup for trace event as suggested by Steven for earlier version.
* Fixed some build errors reported by 0-day bot.

Changes in v3:
* Create a generic mmio header for instrumented version (Earlier suggested in [1] by Will Deacon and recently [2] by Greg to have a generic version first).
* Add dynamic debug support to filter out traces which can be very useful for targeted debugging specific to subsystems or drivers.
* Few modifications to the rwmmio trace event fields to include the mmio width and print addresses in hex.
* Rewrote commit msg to explain some more about usecases.

Prasad Sodagudi (1):
lib: Add register read/write tracing support

Sai Prakash Ranjan (8):
arm64: io: Use asm-generic high level MMIO accessors
coresight: etm4x: Use asm-generic IO memory barriers irqchip/tegra: Fix overflow implicit truncation warnings drm/meson: Fix overflow implicit truncation warnings
KVM: arm64: Add a flag to disable MMIO trace for nVHE KVM asm-generic/io: Add logging support for MMIO accessors
serial: qcom_geni_serial: Disable MMIO tracing for geni serial
soc: qcom: geni: Disable MMIO tracing for GENI SE

  arch/Kconfig                                  |  3 +
  arch/arm64/Kconfig                            |  1 +
  arch/arm64/include/asm/io.h                   | 41 ++------
  arch/arm64/kvm/hyp/nvhe/Makefile              |  7 +-
  drivers/gpu/drm/meson/meson_viu.c             | 22 ++---
  .../coresight/coresight-etm4x-core.c          |  8 +-
  drivers/hwtracing/coresight/coresight-etm4x.h |  8 +-
  drivers/irqchip/irq-tegra.c                   | 10 +-
  drivers/soc/qcom/qcom-geni-se.c               |  3 +
  drivers/tty/serial/qcom_geni_serial.c         |  3 +
  include/asm-generic/io.h                      | 91 ++++++++++++++++-
  include/trace/events/rwmmio.h                 | 97 +++++++++++++++++++
  lib/Kconfig                                   |  7 ++
  lib/Makefile                                  |  2 +
  lib/trace_readwrite.c                         | 47 +++++++++
  15 files changed, 288 insertions(+), 62 deletions(-)

create mode 100644 include/trace/events/rwmmio.h create mode 100644 lib/trace_readwrite.c