Move TLB invalidation code for its own file and document it

PATCH In review Mauro Carvalho Chehab 7 participants 19 messages Aug 4, 2022 – Aug 9, 2022

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DRM drivers Documentation DRM misc Intel i915

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Mauro Carvalho Chehab

author

2022-08-04 07:37 UTC #0 lore raw

v3 cover Move TLB invalidation code for its own file and document it

There are more things to be added to TLB invalidation. Before doing that, move the code to its own file, and add the relevant documentation.

Patch 1 fixes vma_invalidate_tlb() logic to make it update the right var;

Patch 2 only moves the code and do some function renames. No functional change;

Patch 3 adds documentation for the TLB invalidation algorithm and functions.

---

v3:
- Added a fix for an issue from the last TLB patch series;
- included a better description about the changes on patch 2;
- did some minor fixes at kernel-doc markups;

v2: only patch 2 (kernel-doc) was modified:

- The kernel-doc markups for TLB were added to i915.rst doc;
- Some minor fixes at the texts;
- Use a table instead of a literal block while explaining how the algorithm works. That should make easier to understand the logic, both in text form and after its conversion to HTML/PDF;
- Remove mention for GuC, as this depends on a series that will be sent later.

Chris Wilson (1):
drm/i915/gt: Move TLB invalidation to its own file

Mauro Carvalho Chehab (2):
drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb() drm/i915/gt: document TLB cache invalidation functions

 Documentation/gpu/i915.rst                |   7 +
 drivers/gpu/drm/i915/Makefile             |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_pages.c |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.c        | 168 +----------------
 drivers/gpu/drm/i915/gt/intel_gt.h        |  12 --
 drivers/gpu/drm/i915/gt/intel_ppgtt.c     |   2 +-
 drivers/gpu/drm/i915/gt/intel_tlb.c       | 208 ++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_tlb.h       | 128 +++++++++++++
 drivers/gpu/drm/i915/i915_vma.c           |   7 +-
 drivers/gpu/drm/i915/i915_vma.h           |   2 +-
 10 files changed, 355 insertions(+), 184 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.h

Signature · 1 line

2.37.1

Mauro Carvalho Chehab

author

2022-08-04 07:37 UTC #1 lore raw

PATCH v3 1/3 drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()

WRITE_ONCE() should happen at the original var, not on a local copy of it.

Fixes 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 0/3] at: https://lore.kernel.org/all/[email protected]/

 drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
 drivers/gpu/drm/i915/i915_vma.c       | 6 +++---
 drivers/gpu/drm/i915/i915_vma.h       | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

drivers/gpu/drm/i915/gt/intel_ppgtt.c +1 -1

index 2da6c82a8bd2..6ee8d1127016 100644
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
 
 	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
 	if (vma_res->tlb)
-		vma_invalidate_tlb(vm, *vma_res->tlb);
+		vma_invalidate_tlb(vm, vma_res->tlb);
 }
 
 static unsigned long pd_count(u64 size, int shift)

drivers/gpu/drm/i915/i915_vma.c +3 -3

index 84a9ccbc5fc5..260371716490 100644
@@ -1308,7 +1308,7 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct i915_vma *vma)
 	return err;
 }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
 {
 	/*
 	 * Before we release the pages that were bound by this vma, we

@@ -1318,7 +1318,7 @@ void vma_invalidate_tlb(struct i915_address_space *vm, u32 tlb)
 	 * the most recent TLB invalidation seqno, and if we have not yet
 	 * flushed the TLBs upon release, perform a full invalidation.
 	 */
-	WRITE_ONCE(tlb, intel_gt_next_invalidate_tlb_full(vm->gt));
+	WRITE_ONCE(*tlb, intel_gt_next_invalidate_tlb_full(vm->gt));
 }
 
 static void __vma_put_pages(struct i915_vma *vma, unsigned int count)

@@ -1971,7 +1971,7 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async)
 			dma_fence_put(unbind_fence);
 			unbind_fence = NULL;
 		}
-		vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+		vma_invalidate_tlb(vma->vm, &vma->obj->mm.tlb);
 	}
 
 	/*

drivers/gpu/drm/i915/i915_vma.h +1 -1

index 5048eed536da..33a58f605d75 100644
@@ -213,7 +213,7 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
 			u64 size, u64 alignment, u64 flags);
 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
 void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
 struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
 int __i915_vma_unbind(struct i915_vma *vma);
 int __must_check i915_vma_unbind(struct i915_vma *vma);

Signature · 1 line

2.37.1

Tvrtko Ursulin

2022-08-04 08:18 UTC #2 lore raw

Re: [PATCH v3 1/3] drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()

Quoted 4 lines · Mauro Carvalho Chehab

WRITE_ONCE() should happen at the original var, not on a local copy of it.
Fixes 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")

Cc stable I think, since the above one was. So both hit 5.21 (or 6.1) together.

Regards,

Tvrtko

Quoted 68 lines

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 0/3] at: https://lore.kernel.org/all/[email protected]/

  drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
  drivers/gpu/drm/i915/i915_vma.c       | 6 +++---
  drivers/gpu/drm/i915/i915_vma.h       | 2 +-
  3 files changed, 5 insertions(+), 5 deletions(-)

drivers/gpu/drm/i915/gt/intel_ppgtt.c +1 -1

index 2da6c82a8bd2..6ee8d1127016 100644
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
 
  	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
  	if (vma_res->tlb)
-		vma_invalidate_tlb(vm, *vma_res->tlb);
+		vma_invalidate_tlb(vm, vma_res->tlb);
  }
 
  static unsigned long pd_count(u64 size, int shift)

drivers/gpu/drm/i915/i915_vma.c +3 -3

index 84a9ccbc5fc5..260371716490 100644
@@ -1308,7 +1308,7 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct i915_vma *vma)
  	return err;
  }
 
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
  {
  	/*
  	 * Before we release the pages that were bound by this vma, we

@@ -1318,7 +1318,7 @@ void vma_invalidate_tlb(struct i915_address_space *vm, u32 tlb)
  	 * the most recent TLB invalidation seqno, and if we have not yet
  	 * flushed the TLBs upon release, perform a full invalidation.
  	 */
-	WRITE_ONCE(tlb, intel_gt_next_invalidate_tlb_full(vm->gt));
+	WRITE_ONCE(*tlb, intel_gt_next_invalidate_tlb_full(vm->gt));
  }
 
  static void __vma_put_pages(struct i915_vma *vma, unsigned int count)

@@ -1971,7 +1971,7 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async)
  			dma_fence_put(unbind_fence);
  			unbind_fence = NULL;
  		}
-		vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+		vma_invalidate_tlb(vma->vm, &vma->obj->mm.tlb);
  	}
 
  	/*

drivers/gpu/drm/i915/i915_vma.h +1 -1

index 5048eed536da..33a58f605d75 100644
@@ -213,7 +213,7 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
  			u64 size, u64 alignment, u64 flags);
  void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
  void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
  struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
  int __i915_vma_unbind(struct i915_vma *vma);
  int __must_check i915_vma_unbind(struct i915_vma *vma);

Andi Shyti

Reviewed-by on v3 1/3

2022-08-08 16:38 UTC #3 lore raw

Re: [PATCH v3 1/3] drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()

In reply to Mauro Carvalho Chehab

Hi Mauro,

Quoted 5 lines · Mauro Carvalho Chehab

WRITE_ONCE() should happen at the original var, not on a local copy of it.
Fixes 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")
Signed-off-by Mauro Carvalho Chehab <[email protected]>

Reviewed-by Andi Shyti <[email protected]>

Are you going to send it to the stable mailing list?

Andi

Rodrigo Vivi

maintainer

2022-08-08 19:05 UTC #4 lore raw

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()

Quoted 10 lines · Andi Shyti

Hi Mauro,
Quoted 5 lines · Mauro Carvalho Chehab
WRITE_ONCE() should happen at the original var, not on a local copy of it.
Fixes 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")
Signed-off-by Mauro Carvalho Chehab <[email protected]>
Reviewed-by Andi Shyti <[email protected]>

Thanks and pushed...

Quoted 2 lines

Are you going to send it to the stable mailing list?

I added cc stable while pushing and the cherry-pick to drm-intel-next-fixes has the right sha, so I'd assume this would be automagically now. But yeap, it would be good if Mauro can follow up whenever this gets to Linus tree and Greg's script start to pop up the heads-up messages.

Thanks,
Rodrigo.

Quoted 2 lines

Andi

Andi Shyti

2022-08-08 23:10 UTC #5 lore raw

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()

Hi Rodrigo,

Quoted 7 lines · Rodrigo Vivi

Quoted 6 lines · Andi Shyti
Hi Mauro,
Quoted 3 lines · Mauro Carvalho Chehab
WRITE_ONCE() should happen at the original var, not on a local copy of it.

Quoted 6 lines

Quoted 4 lines
Quoted 2 lines
Fixes 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")
Signed-off-by Mauro Carvalho Chehab <[email protected]>
Reviewed-by Andi Shyti <[email protected]>
Thanks and pushed...

Thanks!

Quoted 7 lines

Quoted 2 lines
Are you going to send it to the stable mailing list?
I added cc stable while pushing and the cherry-pick to drm-intel-next-fixes has the right sha, so I'd assume this would be automagically now. But yeap, it would be good if Mauro can follow up whenever this gets to Linus tree and Greg's script start to pop up the heads-up messages.

That's what I meant... does Mauro now need to send the e-mail again for the stable?

I thought there was some suspicion towards e-mails pushed without being first sent to both stable and upstream mailing lists because they can get lost or forgotten... maybe I'm wrong.

Andi

Quoted 5 lines

Thanks,
Rodrigo.
Quoted 2 lines
Andi

Vivi, Rodrigo

maintainer

2022-08-09 00:15 UTC #6 lore raw

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()

Quoted 31 lines · Andi Shyti

Hi Rodrigo,
Quoted 8 lines · Rodrigo Vivi
Quoted 7 lines · Andi Shyti
Hi Mauro,
Quoted 3 lines · Mauro Carvalho Chehab
WRITE_ONCE() should happen at the original var, not on a local copy of it.
Quoted 6 lines
Quoted 4 lines
Quoted 2 lines
Fixes 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")
Signed-off-by Mauro Carvalho Chehab <[email protected]>
Reviewed-by Andi Shyti <[email protected]>
Thanks and pushed...
Thanks!
Quoted 10 lines
Quoted 2 lines
Are you going to send it to the stable mailing list?
I added cc stable while pushing and the cherry-pick to drm-intel- next-fixes
has the right sha, so I'd assume this would be automagically now. But yeap, it would be good if Mauro can follow up whenever this gets
to Linus tree and Greg's script start to pop up the heads-up messages.

Quoted 6 lines

That's what I meant... does Mauro now need to send the e-mail again for the stable?
I thought there was some suspicion towards e-mails pushed without being first sent to both stable and upstream mailing lists because they can get lost or forgotten... maybe I'm wrong.

It doesn't help to send now to stable ml because it can only be merged there after it reaches the Linus' master tree.
Right now with the right fixes and cc:stable it should be automatically and he shouldn't worry.
But in case he notices that the first patch got in but the second didn't then it is when we send the patch directly to the stable ml.

Quoted 8 lines

Andi
Quoted 5 lines
Thanks,
Rodrigo.
Quoted 2 lines
Andi

Mauro Carvalho Chehab

2022-08-09 06:29 UTC #7 lore raw

Re: [Intel-gfx] [PATCH v3 1/3] drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()

Quoted 39 lines · Rodrigo

Quoted 31 lines · Andi Shyti
Hi Rodrigo,
Quoted 8 lines · Rodrigo Vivi
Quoted 7 lines · Andi Shyti
Hi Mauro,
Quoted 3 lines · Mauro Carvalho Chehab
WRITE_ONCE() should happen at the original var, not on a local copy of it.
Quoted 6 lines
Quoted 4 lines
Quoted 2 lines
Fixes 5d36acb7198b ("drm/i915/gt: Batch TLB invalidations")
Signed-off-by Mauro Carvalho Chehab <[email protected]>
Reviewed-by Andi Shyti <[email protected]>
Thanks and pushed...
Thanks!
Quoted 10 lines
Quoted 2 lines
Are you going to send it to the stable mailing list?
I added cc stable while pushing and the cherry-pick to drm-intel- next-fixes
has the right sha, so I'd assume this would be automagically now. But yeap, it would be good if Mauro can follow up whenever this gets
to Linus tree and Greg's script start to pop up the heads-up messages.
Quoted 6 lines
That's what I meant... does Mauro now need to send the e-mail again for the stable?
I thought there was some suspicion towards e-mails pushed without being first sent to both stable and upstream mailing lists because they can get lost or forgotten... maybe I'm wrong.

Quoted 6 lines

It doesn't help to send now to stable ml because it can only be merged there after it reaches the Linus' master tree.
Right now with the right fixes and cc:stable it should be automatically and he shouldn't worry.
But in case he notices that the first patch got in but the second didn't then it is when we send the patch directly to the stable ml.

I sent a heads-up to Greg to warn him about the issue. I'll keep my eyes on the -stable automatic e-mails to double-check that they'll both be merged altogether.

Thanks!
Mauro

Quoted 11 lines

Quoted 10 lines
Andi
Quoted 5 lines
Thanks,
Rodrigo.
Quoted 2 lines
Andi

Mauro Carvalho Chehab

author

2022-08-04 07:37 UTC #8 lore raw

PATCH v3 2/3 drm/i915/gt: Move TLB invalidation to its own file

In reply to Mauro Carvalho Chehab

From: Chris Wilson <[email protected]>

Prepare for supporting more TLB invalidation scenarios by moving the current MMIO invalidation to its own file.

It also:

- Renames intel_gt_invalidate_tlb() to intel_gt_invalidate_tlb_full()
- Add intel_gt_init_tlb() and intel_gt_fini_tlb() abstracts.

Signed-off-by Chris Wilson <[email protected]>

Reviewed-by Niranjana Vishwanathapura <[email protected]>

Reviewed-by Andi Shyti <[email protected]>

Cc Fei Yang <[email protected]>

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 0/3] at: https://lore.kernel.org/all/[email protected]/

 drivers/gpu/drm/i915/Makefile             |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_pages.c |   4 +-
 drivers/gpu/drm/i915/gt/intel_gt.c        | 168 +-------------------
 drivers/gpu/drm/i915/gt/intel_gt.h        |  12 --
 drivers/gpu/drm/i915/gt/intel_tlb.c       | 183 ++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_tlb.h       |  29 ++++
 drivers/gpu/drm/i915/i915_vma.c           |   1 +
 7 files changed, 219 insertions(+), 179 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.h

drivers/gpu/drm/i915/Makefile +1 -0

index 522ef9b4aff3..d3df9832d1f7 100644
@@ -126,6 +126,7 @@ gt-y += \
 	gt/intel_sseu.o \
 	gt/intel_sseu_debugfs.o \
 	gt/intel_timeline.o \
+	gt/intel_tlb.o \
 	gt/intel_workarounds.o \
 	gt/shmem_utils.o \
 	gt/sysfs_engines.o

drivers/gpu/drm/i915/gem/i915_gem_pages.c +2 -2

index 8357dbdcab5c..1cd76cc5d9f3 100644
@@ -7,7 +7,7 @@
 #include <drm/drm_cache.h>
 
 #include "gt/intel_gt.h"
-#include "gt/intel_gt_pm.h"
+#include "gt/intel_tlb.h"
 
 #include "i915_drv.h"
 #include "i915_gem_object.h"

@@ -199,7 +199,7 @@ static void flush_tlb_invalidate(struct drm_i915_gem_object *obj)
 	if (!obj->mm.tlb)
 		return;
 
-	intel_gt_invalidate_tlb(gt, obj->mm.tlb);
+	intel_gt_invalidate_tlb_full(gt, obj->mm.tlb);
 	obj->mm.tlb = 0;
 }

drivers/gpu/drm/i915/gt/intel_gt.c +3 ~~-165~~

196 lines not on this page · raw message

drivers/gpu/drm/i915/gt/intel_gt.h +0 ~~-12~~

index 40b06adf509a..b4bba16cdb53 100644
@@ -101,16 +101,4 @@ void intel_gt_info_print(const struct intel_gt_info *info,
 
 void intel_gt_watchdog_work(struct work_struct *work);
 
-static inline u32 intel_gt_tlb_seqno(const struct intel_gt *gt)
-{
-	return seqprop_sequence(&gt->tlb.seqno);
-}
-
-static inline u32 intel_gt_next_invalidate_tlb_full(const struct intel_gt *gt)
-{
-	return intel_gt_tlb_seqno(gt) | 1;
-}
-
-void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno);
-
 #endif /* __INTEL_GT_H__ */

drivers/gpu/drm/i915/gt/intel_tlb.c new file +183 -0

183 lines not on this page · raw message

drivers/gpu/drm/i915/gt/intel_tlb.h new file +29 -0

new file mode 100644
index 000000000000..46ce25bf5afe
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef INTEL_TLB_H
+#define INTEL_TLB_H
+
+#include <linux/seqlock.h>
+#include <linux/types.h>
+
+#include "intel_gt_types.h"
+
+void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno);
+
+void intel_gt_init_tlb(struct intel_gt *gt);
+void intel_gt_fini_tlb(struct intel_gt *gt);
+
+static inline u32 intel_gt_tlb_seqno(const struct intel_gt *gt)
+{
+	return seqprop_sequence(&gt->tlb.seqno);
+}
+
+static inline u32 intel_gt_next_invalidate_tlb_full(const struct intel_gt *gt)
+{
+	return intel_gt_tlb_seqno(gt) | 1;
+}
+
+#endif /* INTEL_TLB_H */

drivers/gpu/drm/i915/i915_vma.c +1 -0

index 260371716490..21c6883dbeb2 100644
@@ -33,6 +33,7 @@
 #include "gt/intel_engine_heartbeat.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_requests.h"
+#include "gt/intel_tlb.h"
 
 #include "i915_drv.h"
 #include "i915_gem_evict.h"

Signature · 1 line

2.37.1

Mauro Carvalho Chehab

author

2022-08-04 07:37 UTC #9 lore raw

PATCH v3 3/3 drm/i915/gt: document TLB cache invalidation functions

In reply to Mauro Carvalho Chehab

Add a description for the TLB cache invalidation algorithm and for the related kAPI functions.

Signed-off-by Mauro Carvalho Chehab <[email protected]>

---

To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 0/3] at: https://lore.kernel.org/all/[email protected]/

 Documentation/gpu/i915.rst          |  7 ++
 drivers/gpu/drm/i915/gt/intel_tlb.c | 25 ++++++++
 drivers/gpu/drm/i915/gt/intel_tlb.h | 99 +++++++++++++++++++++++++++++
 3 files changed, 131 insertions(+)

Documentation/gpu/i915.rst +7 -0

index 4e59db1cfb00..46911fdd79e8 100644
@@ -58,6 +58,13 @@ Intel GVT-g Host Support(vGPU device model)
 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
    :internal:
 
+TLB cache invalidation
+----------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_tlb.h
+
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_tlb.c
+
 Workarounds
 -----------

drivers/gpu/drm/i915/gt/intel_tlb.c +25 -0

index af8cae979489..16b918ffe824 100644
@@ -145,6 +145,18 @@ static void mmio_invalidate_full(struct intel_gt *gt)
 	intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
 }
 
+/**
+ * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
+ * @gt: GT structure
+ * @seqno: sequence number
+ *
+ * Do a full TLB cache invalidation if the @seqno is bigger than the last
+ * full TLB cache invalidation.
+ *
+ * Note:
+ * The TLB cache invalidation logic depends on GEN-specific registers.
+ * It currently supports MMIO-based TLB flush for GEN8 to GEN12.
+ */
 void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno)
 {
 	intel_wakeref_t wakeref;

@@ -171,12 +183,25 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno)
 	}
 }
 
+/**
+ * intel_gt_init_tlb - initialize TLB-specific vars
+ * @gt: GT structure
+ *
+ * TLB cache invalidation logic internally uses some resources that require
+ * initialization. Should be called before doing any TLB cache invalidation.
+ */
 void intel_gt_init_tlb(struct intel_gt *gt)
 {
 	mutex_init(&gt->tlb.invalidate_lock);
 	seqcount_mutex_init(&gt->tlb.seqno, &gt->tlb.invalidate_lock);
 }
 
+/**
+ * intel_gt_fini_tlb - free TLB-specific vars
+ * @gt: GT structure
+ *
+ * Frees any resources needed by TLB cache invalidation logic.
+ */
 void intel_gt_fini_tlb(struct intel_gt *gt)
 {
 	mutex_destroy(&gt->tlb.invalidate_lock);

drivers/gpu/drm/i915/gt/intel_tlb.h +99 -0

115 lines not on this page · raw message

Signature · 1 line

2.37.1

Randy Dunlap

reviewer

2022-08-04 19:00 UTC #10 lore raw

Re: [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions

Hi Mauro,

Quoted 20 lines · Mauro Carvalho Chehab

Add a description for the TLB cache invalidation algorithm and for the related kAPI functions.
Signed-off-by Mauro Carvalho Chehab <[email protected]>
---
To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v3 0/3] at: https://lore.kernel.org/all/[email protected]/
 Documentation/gpu/i915.rst          |  7 ++
 drivers/gpu/drm/i915/gt/intel_tlb.c | 25 ++++++++
 drivers/gpu/drm/i915/gt/intel_tlb.h | 99 +++++++++++++++++++++++++++++
 3 files changed, 131 insertions(+)
drivers/gpu/drm/i915/gt/intel_tlb.c +0 -0
index af8cae979489..16b918ffe824 100644

drivers/gpu/drm/i915/gt/intel_tlb.c static void mmio_invalidate_full(struct intel_gt *gt) · line 150

Quoted 6 lines

drivers/gpu/drm/i915/gt/intel_tlb.c +3 -0

@@ -145,6 +145,18 @@ static void mmio_invalidate_full(struct intel_gt *gt)
 	intel_uncore_forcewake_put_delayed(uncore, FORCEWAKE_ALL);
 }
 
+/**
+ * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
+ * @gt: GT structure

In multiple places (here and below) it would be nice to know what a GT structure is. I looked thru multiple C and header files yesterday and didn't find any comments about it.

Just saying that @gt is a GT structure isn't very helpful, other than making kernel-doc shut up.

Quoted 49 lines

drivers/gpu/drm/i915/gt/intel_tlb.c +22 -0

+ * @seqno: sequence number
+ *
+ * Do a full TLB cache invalidation if the @seqno is bigger than the last
+ * full TLB cache invalidation.
+ *
+ * Note:
+ * The TLB cache invalidation logic depends on GEN-specific registers.
+ * It currently supports MMIO-based TLB flush for GEN8 to GEN12.
+ */
 void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno)
 {
 	intel_wakeref_t wakeref;

@@ -171,12 +183,25 @@ void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno)
 	}
 }
 
+/**
+ * intel_gt_init_tlb - initialize TLB-specific vars
+ * @gt: GT structure
+ *
+ * TLB cache invalidation logic internally uses some resources that require
+ * initialization. Should be called before doing any TLB cache invalidation.
+ */
 void intel_gt_init_tlb(struct intel_gt *gt)
 {
 	mutex_init(&gt->tlb.invalidate_lock);
 	seqcount_mutex_init(&gt->tlb.seqno, &gt->tlb.invalidate_lock);
 }
 
+/**
+ * intel_gt_fini_tlb - free TLB-specific vars
+ * @gt: GT structure
+ *
+ * Frees any resources needed by TLB cache invalidation logic.
+ */
 void intel_gt_fini_tlb(struct intel_gt *gt)
 {
 	mutex_destroy(&gt->tlb.invalidate_lock);

drivers/gpu/drm/i915/gt/intel_tlb.h +3 -0

index 46ce25bf5afe..2838c051f872 100644
@@ -11,16 +11,115 @@
 
 #include "intel_gt_types.h"
 
+/**
+ * DOC: TLB cache invalidation logic
+ *

...

Quoted 17 lines

drivers/gpu/drm/i915/gt/intel_tlb.h +7 -0

+
 void intel_gt_invalidate_tlb_full(struct intel_gt *gt, u32 seqno);
 
 void intel_gt_init_tlb(struct intel_gt *gt);
 void intel_gt_fini_tlb(struct intel_gt *gt);
 
+/**
+ * intel_gt_tlb_seqno - Returns the current TLB invlidation sequence number
+ * @gt: GT structure
+ *
+ * There's no need to lock while calling it, as seqprop_sequence is thread-safe
+ */
 static inline u32 intel_gt_tlb_seqno(const struct intel_gt *gt)
 {
 	return seqprop_sequence(&gt->tlb.seqno);
 }

drivers/gpu/drm/i915/gt/intel_tlb.h line 125

Quoted 10 lines

drivers/gpu/drm/i915/gt/intel_tlb.h +7 -0

+/**
+ * intel_gt_next_invalidate_tlb_full - Returns the next TLB full invalidation
+ *	sequence number
+ * @gt: GT structure
+ *
+ * There's no need to lock while calling it, as seqprop_sequence is thread-safe
+ */
 static inline u32 intel_gt_next_invalidate_tlb_full(const struct intel_gt *gt)
 {
 	return intel_gt_tlb_seqno(gt) | 1;

thanks.

Signature · 1 line

~Randy

Andi Shyti

2022-08-05 09:08 UTC #11 lore raw

Re: [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions

Hi Randy,

Quoted 10 lines

Quoted 3 lines
+/**
+ * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
+ * @gt: GT structure
In multiple places (here and below) it would be nice to know what a GT structure is. I looked thru multiple C and header files yesterday and didn't find any comments about it.
Just saying that @gt is a GT structure isn't very helpful, other than making kernel-doc shut up.

the 'gt' belongs to the drivers/gpu/drm/i915/gt/ subsystem and it's widely used a throughout i915.

I think it's inappropriate to describe it just here. On the other hand I agree that a better documentation is required for the GT itself where other parts can point to.

Andi

Tvrtko Ursulin

2022-08-05 09:26 UTC #12 lore raw

Re: [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions

Quoted 13 lines · Andi Shyti

Hi Randy,
Quoted 10 lines
Quoted 3 lines
+/**
+ * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
+ * @gt: GT structure
In multiple places (here and below) it would be nice to know what a GT structure is. I looked thru multiple C and header files yesterday and didn't find any comments about it.
Just saying that @gt is a GT structure isn't very helpful, other than making kernel-doc shut up.

Quoted 6 lines

the 'gt' belongs to the drivers/gpu/drm/i915/gt/ subsystem and it's widely used a throughout i915.
I think it's inappropriate to describe it just here. On the other hand I agree that a better documentation is required for the GT itself where other parts can point to.

Yeah agreed there is no point of copy pasting some explanation all over the place. Could we just do s/GT structure/struct intel_gt/, or "pointer to struct intel_gt to operate on", would that be good enough?

Regards,

Tvrtko

Mauro Carvalho Chehab

2022-08-05 10:30 UTC #13 lore raw

Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions

Quoted 14 lines · On Fri, 5 Aug 2022 10:24:25 +0100 Tvrtko Ursulin…

Quoted 13 lines · Andi Shyti
Hi Randy,
Quoted 10 lines
Quoted 3 lines
+/**
+ * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
+ * @gt: GT structure
In multiple places (here and below) it would be nice to know what a GT structure is. I looked thru multiple C and header files yesterday and didn't find any comments about it.
Just saying that @gt is a GT structure isn't very helpful, other than making kernel-doc shut up.

Quoted 6 lines

Quoted 6 lines
the 'gt' belongs to the drivers/gpu/drm/i915/gt/ subsystem and it's widely used a throughout i915.
I think it's inappropriate to describe it just here. On the other hand I agree that a better documentation is required for the GT itself where other parts can point to.

GT is actually a well-understood term for GPU developers. It is an alias for:

https://en.wikipedia.org/wiki/Intel_Graphics_Technology

It is basically the "core" of the GPU, where the engine units sit.

I agree with Andi: terms like this should likely be defined on a glossary at i915.rst file.

Quoted 3 lines

Yeah agreed there is no point of copy pasting some explanation all over the place. Could we just do s/GT structure/struct intel_gt/, or "pointer to struct intel_gt to operate on", would that be good enough?

IMO, it won't make any difference. kerneldoc already says that the parameter has struct intel_gt type on its output:

	.. c:function:: void intel_gt_fini_tlb (struct intel_gt *gt)

	   free TLB-specific vars

	**Parameters**

	``struct intel_gt *gt``
	  GT structure
	
	**Description**

	Frees any resources needed by TLB cache invalidation logic.

This struct somewhat is similar to struct device. This is a container struct that has the common data needed to control the GT hardware.

Almost all functions that work with GT needs it. There's not much sense to describe it everywhere. What makes sense is to have struct intel_gt documented at intel_gt_types.h, letting the build system to generate hiperlinks to it.

This is easier said than done...

Regards,
Mauro

Andi Shyti

Reviewed-by on v3 3/3

2022-08-08 16:58 UTC #14 lore raw

Re: [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions

In reply to Mauro Carvalho Chehab

Hi Mauro,

Quoted 4 lines · Mauro Carvalho Chehab

Add a description for the TLB cache invalidation algorithm and for the related kAPI functions.
Signed-off-by Mauro Carvalho Chehab <[email protected]>

Reviewed-by Andi Shyti <[email protected]>

Andi

Patchwork

2022-08-04 08:12 UTC #15 lore raw

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move TLB invalidation code for its own file and document it (rev4)

In reply to Mauro Carvalho Chehab

== Series Details ==

Series: Move TLB invalidation code for its own file and document it (rev4)
URL : https://patchwork.freedesktop.org/series/106805/
State : warning

== Summary ==

Error: dim checkpatch failed
c884d515384d drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb() e78e81b032d5 drm/i915/gt: Move TLB invalidation to its own file
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:281: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #281:
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 294 lines checked 03f39a09e961 drm/i915/gt: document TLB cache invalidation functions -:103: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #103: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:31:
+ * ^Iwith_intel_gt_pm_if_awake(gt, wakeref) {$

-:104: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #104: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:32:
+ * ^I^Imutex_lock(&gt->tlb.invalidate_lock);$

-:105: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #105: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:33:
+ * ^I^Iif (tlb_seqno_passed(gt, seqno))$

-:106: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #106: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:34:
+ * ^I^I^I^Igoto unlock;$

-:108: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #108: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:36:
+ * ^I^I// Some code to do TLB invalidation$

-:111: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #111: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:39:
+ * ^I^Iwrite_seqcount_invalidate(&gt->tlb.seqno); // increment seqno$

-:112: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #112: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:40:
+ * ^I^Imutex_lock(&gt->tlb.invalidate_lock);$

-:118: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #118: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:46:
+ * ^Iobj1$

-:119: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #119: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:47:
+ * ^Iobj2$

-:120: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #120: FILE: drivers/gpu/drm/i915/gt/intel_tlb.h:48:
+ * ^Iobj3$

total: 0 errors, 10 warnings, 0 checks, 171 lines checked

Patchwork

2022-08-04 08:12 UTC #16 lore raw

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Move TLB invalidation code for its own file and document it (rev4)

In reply to Mauro Carvalho Chehab

== Series Details ==

Series: Move TLB invalidation code for its own file and document it (rev4)
URL : https://patchwork.freedesktop.org/series/106805/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Patchwork

2022-08-04 08:35 UTC #17 lore raw

[Intel-gfx] ✓ Fi.CI.BAT: success for Move TLB invalidation code for its own file and document it (rev4)

In reply to Mauro Carvalho Chehab

== Series Details ==

Series: Move TLB invalidation code for its own file and document it (rev4)
URL : https://patchwork.freedesktop.org/series/106805/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11966 -> Patchwork_106805v4
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/index.html

Participating hosts (41 -> 39)
------------------------------

Additional (2): bat-rpls-1 bat-dg2-10
Missing (4): fi-kbl-soraka fi-rkl-11600 bat-jsl-1 bat-dg1-5

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_106805v4:

### IGT changes ###

#### Suppressed ####

The following results come from untrusted machines, tests, or statuses. They do not affect the overall result.

* igt@i915_module_load@load:
- {bat-dg2-10}: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/bat-dg2-10/igt@[email protected]

Known issues
------------

Here are the changes found in Patchwork_106805v4 that come from known issues:

### CI changes ###

#### Possible fixes ####

* boot:
- fi-kbl-8809g: [FAIL][2] -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-kbl-8809g/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-kbl-8809g/boot.html

### IGT changes ###

#### Issues hit ####

* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-kbl-8809g/igt@[email protected]

* igt@gem_lmem_swapping@basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-kbl-8809g/igt@[email protected]

* igt@i915_selftest@live@gt_pm:
- bat-adlp-4: [PASS][6] -> [DMESG-FAIL][7] ([i915#3987])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-adlp-4/igt@i915_selftest@live@gt_pm.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/bat-adlp-4/igt@i915_selftest@live@gt_pm.html

* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][8] -> [INCOMPLETE][9] ([i915#4785])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-hsw-4770/igt@i915_selftest@[email protected]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-hsw-4770/igt@i915_selftest@[email protected]
- fi-hsw-g3258: [PASS][10] -> [INCOMPLETE][11] ([i915#3303] / [i915#4785])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-hsw-g3258/igt@i915_selftest@[email protected]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-hsw-g3258/igt@i915_selftest@[email protected]
- bat-dg1-6: [PASS][12] -> [DMESG-FAIL][13] ([i915#4494] / [i915#4957])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-dg1-6/igt@i915_selftest@[email protected]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/bat-dg1-6/igt@i915_selftest@[email protected]

* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-8809g: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-kbl-8809g/igt@[email protected]

* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-kbl-8809g: NOTRUN -> [SKIP][15] ([fdo#109271]) +26 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-kbl-8809g/igt@[email protected]

* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#4312] / [i915#5594] / [i915#6246])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-hsw-4770/igt@[email protected]
- fi-hsw-g3258: NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#4312] / [i915#6246])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-hsw-g3258/igt@[email protected]

#### Possible fixes ####

* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][18] ([i915#2582]) -> [PASS][19] +4 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rpls-2/igt@[email protected]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/bat-rpls-2/igt@[email protected]

* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][20] ([i915#2867]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rplp-1/igt@gem_exec_suspend@[email protected]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/bat-rplp-1/igt@gem_exec_suspend@[email protected]

* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][22] ([i915#6298]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html

* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][24] ([i915#1849]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rpls-2/igt@[email protected]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/bat-rpls-2/igt@[email protected]

* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}: [SKIP][26] ([fdo#109295] / [i915#1845] / [i915#3708]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/bat-rpls-2/igt@[email protected]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/bat-rpls-2/igt@[email protected]

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes
-------------

* Linux: CI_DRM_11966 -> Patchwork_106805v4

CI-20190529: 20190529
CI_DRM_11966: f3c1d1b53388aaa69e20a1b72f8307ad57116565 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6613: 209230467200f2fa63a6f71fe6299996470dd813 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_106805v4: f3c1d1b53388aaa69e20a1b72f8307ad57116565 @ git://anongit.freedesktop.org/gfx-ci/linux

### Linux commits

ab8c90b06da5 drm/i915/gt: document TLB cache invalidation functions 96a7199a6661 drm/i915/gt: Move TLB invalidation to its own file 6ad5536f0ed8 drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/index.html

Patchwork

2022-08-04 10:09 UTC #18 lore raw

[Intel-gfx] ✓ Fi.CI.IGT: success for Move TLB invalidation code for its own file and document it (rev4)

In reply to Mauro Carvalho Chehab

== Series Details ==

Series: Move TLB invalidation code for its own file and document it (rev4)
URL : https://patchwork.freedesktop.org/series/106805/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11966_full -> Patchwork_106805v4_full
====================================================

Summary
-------

**SUCCESS**

No regressions found.

Participating hosts (10 -> 12)
------------------------------

Additional (2): shard-rkl shard-tglu

Possible new issues
-------------------

Here are the unknown changes that may have been introduced in Patchwork_106805v4_full:

### IGT changes ###

#### Suppressed ####

The following results come from untrusted machines, tests, or statuses. They do not affect the overall result.

* igt@gem_ppgtt@blt-vs-render-ctx0:
- {shard-rkl}: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-rkl-5/igt@[email protected]

Known issues
------------

Here are the changes found in Patchwork_106805v4_full that come from known issues:

### CI changes ###

#### Issues hit ####

### IGT changes ###

#### Issues hit ####

* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][51] -> [SKIP][52] ([i915#4525])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb1/igt@[email protected]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb8/igt@[email protected]

* igt@gem_exec_fair@basic-deadline:
- shard-glk: NOTRUN -> [FAIL][53] ([i915#2846])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk1/igt@[email protected]

* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][54] -> [FAIL][55] ([i915#2842]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-tglb2/igt@gem_exec_fair@[email protected]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-tglb1/igt@gem_exec_fair@[email protected]

* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][56] -> [FAIL][57] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-apl4/igt@gem_exec_fair@[email protected]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl3/igt@gem_exec_fair@[email protected]

* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: [PASS][58] -> [FAIL][59] ([i915#2842]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-kbl1/igt@gem_exec_fair@[email protected]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl4/igt@gem_exec_fair@[email protected]

* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#2842])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-glk7/igt@gem_exec_fair@[email protected]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk7/igt@gem_exec_fair@[email protected]

* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][62] -> [FAIL][63] ([i915#2842])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb8/igt@gem_exec_fair@[email protected]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb6/igt@gem_exec_fair@[email protected]

* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][64] -> [SKIP][65] ([i915#2190])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-tglb3/igt@[email protected]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-tglb7/igt@[email protected]

* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk1/igt@[email protected]

* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-skl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#4613]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl6/igt@[email protected]

* igt@gem_lmem_swapping@smem-oom:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl6/igt@[email protected]

* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#3323])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl2/igt@[email protected]
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#3323])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl4/igt@[email protected]

* igt@gem_workarounds@suspend-resume-fd:
- shard-snb: [PASS][71] -> [INCOMPLETE][72] ([i915#5129])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-snb4/igt@[email protected]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-snb6/igt@[email protected]

* igt@gen9_exec_parse@allowed-single:
- shard-apl: NOTRUN -> [DMESG-WARN][73] ([i915#5566] / [i915#716])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl6/igt@[email protected]

* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#1937])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl7/igt@i915_pm_lpsp@[email protected]

* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3886]) +4 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl6/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +4 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

* igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271]) +68 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl6/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html

* igt@kms_chamelium@dp-crc-single:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111827]) +14 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl6/igt@[email protected]

* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271] / [fdo#111827]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk1/igt@[email protected]

* igt@kms_chamelium@hdmi-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl6/igt@[email protected]

* igt@kms_color_chamelium@pipe-a-gamma:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +3 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl4/igt@[email protected]

* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][83] ([i915#1319])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl7/igt@[email protected]

* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][84] ([i915#2105])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl3/igt@[email protected]

* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [PASS][85] -> [FAIL][86] ([i915#2346])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-glk2/igt@kms_cursor_legacy@[email protected]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk5/igt@kms_cursor_legacy@[email protected]

* igt@kms_cursor_legacy@flip-vs-cursor@toggle:
- shard-iclb: [PASS][87] -> [FAIL][88] ([i915#2346]) +3 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb8/igt@kms_cursor_legacy@[email protected]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb7/igt@kms_cursor_legacy@[email protected]

* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][89] -> [FAIL][90] ([i915#4767])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-skl6/igt@[email protected]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl10/igt@[email protected]

* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl: [PASS][91] -> [DMESG-WARN][92] ([i915#165] / [i915#180])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-kbl4/igt@kms_flip@[email protected]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl7/igt@kms_flip@[email protected]

* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [PASS][93] -> [DMESG-WARN][94] ([i915#180]) +6 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-kbl4/igt@kms_flip@[email protected]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl7/igt@kms_flip@[email protected]

* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-skl: [PASS][95] -> [INCOMPLETE][96] ([i915#4839])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-skl10/igt@kms_flip@[email protected]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl9/igt@kms_flip@[email protected]

* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][97] ([i915#2672]) +6 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html

* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][98] ([i915#2672] / [i915#3555])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-glk: NOTRUN -> [SKIP][99] ([fdo#109271]) +42 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html

* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
- shard-skl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#1888]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][101] ([fdo#108145] / [i915#265])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl3/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][102] ([i915#265])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl6/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][103] ([i915#265])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk1/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][104] ([fdo#108145] / [i915#265])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl6/igt@[email protected]

* igt@kms_plane_alpha_blend@pipe-d-alpha-transparent-fb:
- shard-apl: NOTRUN -> [SKIP][105] ([fdo#109271]) +162 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl4/igt@[email protected]

* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-iclb: [PASS][106] -> [SKIP][107] ([i915#5176]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html

* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-apl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#658])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl4/igt@[email protected]

* igt@kms_psr@psr2_dpms:
- shard-kbl: NOTRUN -> [SKIP][109] ([fdo#109271]) +28 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl4/igt@kms_psr@psr2_dpms.html

* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#533])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl2/igt@[email protected]
- shard-kbl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#533])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl4/igt@[email protected]

* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2437])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl3/igt@[email protected]

* igt@perf@short-reads:
- shard-skl: [PASS][113] -> [FAIL][114] ([i915#51])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-skl1/igt@[email protected]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl4/igt@[email protected]

* igt@sysfs_clients@pidname:
- shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#2994]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl7/igt@[email protected]

* igt@sysfs_clients@sema-10:
- shard-glk: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#2994])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk1/igt@[email protected]

#### Possible fixes ####

* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [TIMEOUT][117] ([i915#3063]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-tglb3/igt@[email protected]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-tglb5/igt@[email protected]

* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [SKIP][119] ([i915#4525]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb3/igt@[email protected]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb1/igt@[email protected]

* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][121] ([i915#2842]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb4/igt@gem_exec_fair@[email protected]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb3/igt@gem_exec_fair@[email protected]

* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [FAIL][123] ([i915#2842]) -> [PASS][124] +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-glk2/igt@gem_exec_fair@[email protected]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-glk5/igt@gem_exec_fair@[email protected]

* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][125] ([i915#2842]) -> [PASS][126] +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-kbl7/igt@gem_exec_fair@[email protected]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl7/igt@gem_exec_fair@[email protected]

* igt@gem_softpin@noreloc-s3:
- shard-kbl: [DMESG-WARN][127] ([i915#180]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-kbl7/igt@[email protected]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl4/igt@[email protected]

* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-iclb: [DMESG-WARN][129] ([i915#6316]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb2/igt@[email protected]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb2/igt@[email protected]

* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-skl: [FAIL][131] ([i915#2521]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-skl7/igt@kms_async_flips@[email protected]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl7/igt@kms_async_flips@[email protected]

* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [FAIL][133] ([i915#79]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-skl4/igt@kms_flip@[email protected]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl6/igt@kms_flip@[email protected]

* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][135] ([i915#2122]) -> [PASS][136] +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-skl1/igt@kms_flip@[email protected]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl4/igt@kms_flip@[email protected]

* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-kbl: [FAIL][137] ([i915#1188]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-kbl7/igt@kms_hdr@[email protected]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl4/igt@kms_hdr@[email protected]

* igt@kms_invalid_mode@int-max-clock@dp-1-pipe-c:
- shard-apl: [DMESG-WARN][139] ([i915#62]) -> [PASS][140] +12 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-apl7/igt@kms_invalid_mode@[email protected]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl1/igt@kms_invalid_mode@[email protected]

* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][141] ([i915#180]) -> [PASS][142] +4 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-apl4/igt@[email protected]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-apl6/igt@[email protected]

#### Warnings ####

* igt@gem_eio@kms:
- shard-tglb: [TIMEOUT][143] ([i915#3063]) -> [FAIL][144] ([i915#5784])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-tglb5/igt@[email protected]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-tglb2/igt@[email protected]

* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][145] ([i915#6117]) -> [SKIP][146] ([i915#4525])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb4/igt@[email protected]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb3/igt@[email protected]

* igt@gem_exec_fair@basic-none@bcs0:
- shard-iclb: [FAIL][147] ([i915#2842]) -> [FAIL][148] ([i915#2849])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-iclb4/igt@gem_exec_fair@[email protected]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-iclb1/igt@gem_exec_fair@[email protected]

* igt@i915_selftest@mock@vma:
- shard-skl: [INCOMPLETE][149] ([i915#6473] / [i915#6509]) -> [INCOMPLETE][150] ([i915#6473])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-skl1/igt@i915_selftest@[email protected]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-skl4/igt@i915_selftest@[email protected]

* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl: [DMESG-WARN][151] ([i915#180]) -> [DMESG-FAIL][152] ([i915#180])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11966/shard-kbl7/igt@kms_hdr@[email protected]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/shard-kbl7/igt@kms_hdr@[email protected]

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes
-------------

* Linux: CI_DRM_11966 -> Patchwork_106805v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106805v4/index.html