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arm64: zynqmp: Misc zynqmp changes

PATCH Applied Michal Simek 2 participants 13 messages May 22, 2023 – Jun 5, 2023

Subsystems (2)
Device tree bindings Arm/Zynq architecture

v2 of 3 Applied Latest is v3 →

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Michal Simek

author maintainer
#0 lore raw

v2 cover arm64: zynqmp: Misc zynqmp changes

Hi,

the series is syncing the latest dt changes based on board status and the latest DT schema.
The patches are based on
https://lore.kernel.org/all/[email protected]/

I have applied patches which were reviewed already to have smaller series. Patches can be found https://github.com/Xilinx/linux-xlnx/tree/zynqmp/dt
Or they are in Linux-next already.

v1 is at
https://lore.kernel.org/r/[email protected].

Thanks,
Michal

Changes in v2:
- fix typo in commit message
- Update commit message to skip spi-nor part - reported by Laurent
- Update commit message to remove Linux part - reported by Laurent
- Update commit message to remove OS content - reported by Laurent

Amit Kumar Mahapatra (1):
arm64: zynqmp: Set qspi tx-buswidth to 4

Ashok Reddy Soma (1):
arm64: zynqmp: Fix usb node drive strength and slew rate

Michal Simek (2):
arm64: zynqmp: Describe TI phy as ethernet-phy-id
arm64: zynqmp: Used fixed-partitions for QSPI in k26

Radhey Shyam Pandey (2):
arm64: zynqmp: Add L2 cache nodes
arm64: zynqmp: Add pmu interrupt-affinity

 .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso |   8 +-
 .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso |   8 +-
 .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts    | 171 +++++++++---------
 .../boot/dts/xilinx/zynqmp-zc1232-revA.dts    |   2 +-
 .../boot/dts/xilinx/zynqmp-zc1254-revA.dts    |   2 +-
 .../dts/xilinx/zynqmp-zc1751-xm015-dc1.dts    |  10 +-
 .../dts/xilinx/zynqmp-zc1751-xm016-dc2.dts    |   8 +-
 .../dts/xilinx/zynqmp-zc1751-xm018-dc4.dts    |   2 +-
 .../boot/dts/xilinx/zynqmp-zcu100-revC.dts    |  13 +-
 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    |  30 ++-
 .../boot/dts/xilinx/zynqmp-zcu102-revB.dts    |  25 ++-
 .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    |  30 ++-
 .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    |  30 ++-
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    |  29 ++-
 .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    |  29 ++-
 .../boot/dts/xilinx/zynqmp-zcu1275-revA.dts   |   2 +-
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi        |  13 ++
 17 files changed, 256 insertions(+), 156 deletions(-)
Signature · 1 line
2.36.1
author maintainer
#1 lore raw

PATCH v2 1/6 arm64: zynqmp: Describe TI phy as ethernet-phy-id

TI DP83867 is using strapping based on MIO pins. Tristate setup can influence PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Phy reset is done via gpio.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- fix typo in commit message

Checkpatch is reporting issue
warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented but it should be fully aligned with Documentation/devicetree/bindings/net/ethernet-phy.yaml

c&p more details from v1 version:
Phy has some pins which is using for strapping for phy address after phy reset or power on. Pretty much it is resistor array which based on datasheet is decoded to certain phy address.
And because some phy pins are also used as data pin for RGMII they are connected via MIO pins on a silicon. That's why IO block output setting really matter here because it changes resistor array and it moves phy address.
That's why there is a need to do proper IO pin setup and after it call phy reset to get it to address which was decided by PCB designer.

---
 .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    | 23 +++++++++++------
 .../boot/dts/xilinx/zynqmp-zcu102-revB.dts    | 25 +++++++++++--------
 .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    | 22 ++++++++++------
 .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 22 ++++++++++------
 .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    | 22 ++++++++++------
 .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    | 22 ++++++++++------
 6 files changed, 90 insertions(+), 46 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +15 -8
index 230ef94d5dcb..f36353a51863 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevA
  *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -200,13 +201,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@21 {
-		reg = <21>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
-		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@21 {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <21>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +15 -10
index 63419deb5b33..3c28130909bc 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevB
  *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -16,16 +17,20 @@ / {
 
 &gem3 {
 	phy-handle = <&phyc>;
-	phyc: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
-		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+	mdio: mdio {
+		phyc: ethernet-phy@c {
+			#phy-cells = <0x1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
+		/* Cleanup from RevA */
+		/delete-node/ ethernet-phy@21;
 	};
-	/* Cleanup from RevA */
-	/delete-node/ ethernet-phy@21;
 };
 
 /* Fix collision with u61 */
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +15 -7
index d178a4f898c9..3fd47725c2c8 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU104
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -109,12 +110,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +15 -7
index 38b11594c074..4f6429caecff 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU104
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -114,12 +115,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +15 -7
index 8af0879806cf..8c3fa3fe28d5 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU106
  *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -212,12 +213,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			reg = <0xc>;
+			compatible = "ethernet-phy-id2000.a231";
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +15 -7
index f76687914e30..0d9b6081dff6 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU111
  *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -172,12 +173,19 @@ &gem3 {
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
Signature · 1 line
2.36.1
Applied
#2 lore raw

Re: [PATCH v2 1/6] arm64: zynqmp: Describe TI phy as ethernet-phy-id

Quoted 271 lines · Michal Simek

TI DP83867 is using strapping based on MIO pins. Tristate setup can influence PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Phy reset is done via gpio.

Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- fix typo in commit message

Checkpatch is reporting issue
warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented but it should be fully aligned with Documentation/devicetree/bindings/net/ethernet-phy.yaml

c&p more details from v1 version:
Phy has some pins which is using for strapping for phy address after phy reset or power on. Pretty much it is resistor array which based on datasheet is decoded to certain phy address.
And because some phy pins are also used as data pin for RGMII they are connected via MIO pins on a silicon. That's why IO block output setting really matter here because it changes resistor array and it moves phy address.
That's why there is a need to do proper IO pin setup and after it call phy reset to get it to address which was decided by PCB designer.

---
  .../boot/dts/xilinx/zynqmp-zcu102-revA.dts    | 23 +++++++++++------
  .../boot/dts/xilinx/zynqmp-zcu102-revB.dts    | 25 +++++++++++--------
  .../boot/dts/xilinx/zynqmp-zcu104-revA.dts    | 22 ++++++++++------
  .../boot/dts/xilinx/zynqmp-zcu104-revC.dts    | 22 ++++++++++------
  .../boot/dts/xilinx/zynqmp-zcu106-revA.dts    | 22 ++++++++++------
  .../boot/dts/xilinx/zynqmp-zcu111-revA.dts    | 22 ++++++++++------
  6 files changed, 90 insertions(+), 46 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +15 -8
index 230ef94d5dcb..f36353a51863 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU102 RevA
   *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -200,13 +201,19 @@ &gem3 {
  	phy-mode = "rgmii-id";
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@21 {
-		reg = <21>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
-		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@21 {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <21>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
  	};
  };
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts +15 -10
index 63419deb5b33..3c28130909bc 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU102 RevB
   *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -16,16 +17,20 @@ / {
 
  &gem3 {
  	phy-handle = <&phyc>;
-	phyc: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
-		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+	mdio: mdio {
+		phyc: ethernet-phy@c {
+			#phy-cells = <0x1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
+		/* Cleanup from RevA */
+		/delete-node/ ethernet-phy@21;
  	};
-	/* Cleanup from RevA */
-	/delete-node/ ethernet-phy@21;
  };
 
  /* Fix collision with u61 */
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +15 -7
index d178a4f898c9..3fd47725c2c8 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU104
   *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -109,12 +110,19 @@ &gem3 {
  	phy-mode = "rgmii-id";
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
  	};
  };
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +15 -7
index 38b11594c074..4f6429caecff 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU104
   *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -114,12 +115,19 @@ &gem3 {
  	phy-mode = "rgmii-id";
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
  	};
  };
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +15 -7
index 8af0879806cf..8c3fa3fe28d5 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU106
   *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -212,12 +213,19 @@ &gem3 {
  	phy-mode = "rgmii-id";
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			reg = <0xc>;
+			compatible = "ethernet-phy-id2000.a231";
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
  	};
  };
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +8 -7
index f76687914e30..0d9b6081dff6 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU111
   *
- * (C) Copyright 2017 - 2021, Xilinx, Inc.
+ * (C) Copyright 2017 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -172,12 +173,19 @@ &gem3 {
  	phy-mode = "rgmii-id";
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts &gem3 { · line 191

Quoted 10 lines
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +7 -0
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
+		};
  	};
  };

Applied.
M

Signature · 6 lines
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs
author maintainer
#3 lore raw

PATCH v2 2/6 arm64: zynqmp: Fix usb node drive strength and slew rate

In reply to Michal Simek

From: Ashok Reddy Soma <[email protected]>

As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb group pins.

Signed-off-by Ashok Reddy Soma <[email protected]>
Signed-off-by Michal Simek <[email protected]>

---

(no changes since v1)

c&p more explanation from v1 version.

In design tools all inputs pins are setup like described by default. That's why it could suggest that there is no need to describe default configuration in DT. But all MIOs can be used as GPIOs where pinctrl can change their default values to something else. That's why setting up default values is to be safe even for input pins. I don't know HW details to that extend but that values can also change input behavior that's why having default is not a bad idea.

---
 .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso |  8 ++++++--
 .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso |  8 ++++++--
 .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts     |  8 ++++++--
 .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts     |  8 ++++++--
 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts   | 13 ++++++++++---
 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts   |  5 ++++-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts   |  6 ++++--
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts   |  6 ++++--
 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts   |  5 ++++-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts   |  5 ++++-
 10 files changed, 54 insertions(+), 18 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +6 -2
index 669fe6084f3f..603839c82599 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for KV260 revA Carrier Card
  *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * SD level shifter:
  * "A" - A01 board un-modified (NXP)

@@ -265,19 +266,22 @@ mux {
 	pinctrl_usb0_default: usb0-default {
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			"MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 
 		mux {
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +6 -2
index 7886a19139ee..a91d09e7da4b 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for KV260 revA Carrier Card
  *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -248,19 +249,22 @@ mux {
 	pinctrl_usb0_default: usb0-default {
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			"MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 
 		mux {
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +6 -2
index 1a7995ee62ce..af3331c133ad 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -187,19 +188,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +6 -2
index 869b733a0634..6503f4985f8d 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP zc1751-xm016-dc2
  *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  */

@@ -281,19 +282,22 @@ mux {
 
 		conf {
 			groups = "usb1_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO64", "MIO65", "MIO67";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
 			       "MIO72", "MIO73", "MIO74", "MIO75";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +10 -3
index 544801814bd5..44d1f351bb75 100644
@@ -2,7 +2,8 @@
 /*
  * dts file for Xilinx ZynqMP ZCU100 revC
  *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
  *
  * Michal Simek <[email protected]>
  * Nathalie Chan King Choy

@@ -432,19 +433,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 

@@ -456,19 +460,22 @@ mux {
 
 		conf {
 			groups = "usb1_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO64", "MIO65", "MIO67";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
 			       "MIO72", "MIO73", "MIO74", "MIO75";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 };
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +4 -1
index f36353a51863..a074d8e2b86d 100644
@@ -783,19 +783,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +4 -2
index 3fd47725c2c8..91c9b77f6b1f 100644
@@ -410,20 +410,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
-			drive-strength = <12>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 };
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +4 -2
index 4f6429caecff..954044d9899f 100644
@@ -422,20 +422,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
-			drive-strength = <12>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
 };
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +4 -1
index 8c3fa3fe28d5..ab5e34b43642 100644
@@ -794,19 +794,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +4 -1
index 0d9b6081dff6..f31365a14f73 100644
@@ -660,19 +660,22 @@ mux {
 
 		conf {
 			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
 			power-source = <IO_STANDARD_LVCMOS18>;
 		};
 
 		conf-rx {
 			pins = "MIO52", "MIO53", "MIO55";
 			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
 		};
 
 		conf-tx {
 			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 			       "MIO60", "MIO61", "MIO62", "MIO63";
 			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
 		};
 	};
Signature · 1 line
2.36.1
Applied
#4 lore raw

Re: [PATCH v2 2/6] arm64: zynqmp: Fix usb node drive strength and slew rate

Quoted 382 lines · Michal Simek

From: Ashok Reddy Soma <[email protected]>

As per design, all input/rx pins should have fast slew rate and 12mA drive strength. Rest all pins should be slow slew rate and 4mA drive strength. Fix usb nodes as per this and remove setting of slow slew rate for all the usb group pins.

Signed-off-by Ashok Reddy Soma <[email protected]>
Signed-off-by Michal Simek <[email protected]>

---

(no changes since v1)

c&p more explanation from v1 version.

In design tools all inputs pins are setup like described by default. That's why it could suggest that there is no need to describe default configuration in DT. But all MIOs can be used as GPIOs where pinctrl can change their default values to something else. That's why setting up default values is to be safe even for input pins. I don't know HW details to that extend but that values can also change input behavior that's why having default is not a bad idea.

---
  .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso |  8 ++++++--
  .../arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso |  8 ++++++--
  .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts     |  8 ++++++--
  .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts     |  8 ++++++--
  arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts   | 13 ++++++++++---
  arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts   |  5 ++++-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts   |  6 ++++--
  arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts   |  6 ++++--
  arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts   |  5 ++++-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts   |  5 ++++-
  10 files changed, 54 insertions(+), 18 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +6 -2
index 669fe6084f3f..603839c82599 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for KV260 revA Carrier Card
   *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * SD level shifter:
   * "A" - A01 board un-modified (NXP)

@@ -265,19 +266,22 @@ mux {
  	pinctrl_usb0_default: usb0-default {
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			"MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
 
  		mux {
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +6 -2
index 7886a19139ee..a91d09e7da4b 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for KV260 revA Carrier Card
   *
- * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2020 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -248,19 +249,22 @@ mux {
  	pinctrl_usb0_default: usb0-default {
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			"MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
 
  		mux {
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +6 -2
index 1a7995ee62ce..af3331c133ad 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP zc1751-xm015-dc1
   *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -187,19 +188,22 @@ mux {
 
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +6 -2
index 869b733a0634..6503f4985f8d 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP zc1751-xm016-dc2
   *
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   */

@@ -281,19 +282,22 @@ mux {
 
  		conf {
  			groups = "usb1_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO64", "MIO65", "MIO67";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
  			       "MIO72", "MIO73", "MIO74", "MIO75";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +10 -3
index 544801814bd5..44d1f351bb75 100644
@@ -2,7 +2,8 @@
  /*
   * dts file for Xilinx ZynqMP ZCU100 revC
   *
- * (C) Copyright 2016 - 2021, Xilinx, Inc.
+ * (C) Copyright 2016 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
   *
   * Michal Simek <[email protected]>
   * Nathalie Chan King Choy

@@ -432,19 +433,22 @@ mux {
 
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
 

@@ -456,19 +460,22 @@ mux {
 
  		conf {
  			groups = "usb1_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO64", "MIO65", "MIO67";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
  			       "MIO72", "MIO73", "MIO74", "MIO75";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  };
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +4 -1
index f36353a51863..a074d8e2b86d 100644
@@ -783,19 +783,22 @@ mux {
 
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +4 -2
index 3fd47725c2c8..91c9b77f6b1f 100644
@@ -410,20 +410,22 @@ mux {
 
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
-			drive-strength = <12>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  };
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +4 -2
index 4f6429caecff..954044d9899f 100644
@@ -422,20 +422,22 @@ mux {
 
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
-			drive-strength = <12>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
  };
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +4 -1
index 8c3fa3fe28d5..ab5e34b43642 100644
@@ -794,19 +794,22 @@ mux {
 
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +2 -1
index 0d9b6081dff6..f31365a14f73 100644
@@ -660,19 +660,22 @@ mux {
 
  		conf {
  			groups = "usb0_0_grp";
-			slew-rate = <SLEW_RATE_SLOW>;
  			power-source = <IO_STANDARD_LVCMOS18>;
  		};
 
  		conf-rx {
  			pins = "MIO52", "MIO53", "MIO55";
  			bias-high-impedance;
+			drive-strength = <12>;
+			slew-rate = <SLEW_RATE_FAST>;
  		};

arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts mux { · line 681

Quoted 10 lines
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +2 -0
 
  		conf-tx {
  			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  			       "MIO60", "MIO61", "MIO62", "MIO63";
  			bias-disable;
+			drive-strength = <4>;
+			slew-rate = <SLEW_RATE_SLOW>;
  		};
  	};

Applied.
M

Signature · 6 lines
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs
author maintainer
#5 lore raw

PATCH v2 3/6 arm64: zynqmp: Set qspi tx-buswidth to 4

In reply to Michal Simek

From: Amit Kumar Mahapatra <[email protected]>

All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4.
Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line.

Signed-off-by Amit Kumar Mahapatra <[email protected]>
Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- Update commit message to skip spi-nor part - reported by Laurent

 arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts      | 2 +-
 arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts     | 2 +-
 11 files changed, 11 insertions(+), 11 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +1 -1
index c1ab1ab690df..84e18fdce775 100644
@@ -124,7 +124,7 @@ spi_flash: flash@0 { /* MT25QU512A */
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <40000000>; /* 40MHz */
 		partition@0 {
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +1 -1
index 48d6a7202406..04079d1704f1 100644
@@ -44,7 +44,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +1 -1
index e80484f9b137..3dec57cf18be 100644
@@ -45,7 +45,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +1 -1
index af3331c133ad..d9d1de5f313c 100644
@@ -355,7 +355,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +1 -1
index 05be71eab722..6636e76545a5 100644
@@ -173,7 +173,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +1 -1
index a074d8e2b86d..8767f147cbe3 100644
@@ -957,7 +957,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +1 -1
index 91c9b77f6b1f..e185709c0d84 100644
@@ -444,7 +444,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +1 -1
index 954044d9899f..7fceebd1815c 100644
@@ -456,7 +456,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +1 -1
index ab5e34b43642..27b2416cb6d8 100644
@@ -964,7 +964,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +1 -1
index f31365a14f73..6224365826d8 100644
@@ -794,7 +794,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +1 -1
index e615286b8eff..c406017b0348 100644
@@ -47,7 +47,7 @@ &qspi {
 	flash@0 {
 		compatible = "m25p80", "jedec,spi-nor";
 		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <108000000>;
 	};
Signature · 1 line
2.36.1
author maintainer Applied
#6 lore raw

Re: [PATCH v2 3/6] arm64: zynqmp: Set qspi tx-buswidth to 4

Quoted 164 lines · Michal Simek

From: Amit Kumar Mahapatra <[email protected]>

All ZynqMP boards are setting up tx-buswidth to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4.
Using all 4 lines will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line.

Signed-off-by Amit Kumar Mahapatra <[email protected]>
Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- Update commit message to skip spi-nor part - reported by Laurent

  arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts      | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts      | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts      | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts      | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts      | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts      | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts      | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts      | 2 +-
  arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts     | 2 +-
  11 files changed, 11 insertions(+), 11 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +1 -1
index c1ab1ab690df..84e18fdce775 100644
@@ -124,7 +124,7 @@ spi_flash: flash@0 { /* MT25QU512A */
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>;
  		spi-max-frequency = <40000000>; /* 40MHz */
  		partition@0 {
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +1 -1
index 48d6a7202406..04079d1704f1 100644
@@ -44,7 +44,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>;
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +1 -1
index e80484f9b137..3dec57cf18be 100644
@@ -45,7 +45,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +1 -1
index af3331c133ad..d9d1de5f313c 100644
@@ -355,7 +355,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>;
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +1 -1
index 05be71eab722..6636e76545a5 100644
@@ -173,7 +173,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>; /* also DUAL configuration possible */
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +1 -1
index a074d8e2b86d..8767f147cbe3 100644
@@ -957,7 +957,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +1 -1
index 91c9b77f6b1f..e185709c0d84 100644
@@ -444,7 +444,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>;
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +1 -1
index 954044d9899f..7fceebd1815c 100644
@@ -456,7 +456,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>;
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +1 -1
index ab5e34b43642..27b2416cb6d8 100644
@@ -964,7 +964,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +1 -1
index f31365a14f73..6224365826d8 100644
@@ -794,7 +794,7 @@ flash@0 {
  		#address-cells = <1>;
  		#size-cells = <1>;
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  		spi-max-frequency = <108000000>; /* Based on DC1 spec */
  	};
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +0 -0
index e615286b8eff..c406017b0348 100644

arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts &qspi { · line 53

Quoted 8 lines
arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +1 -1
@@ -47,7 +47,7 @@ &qspi {
  	flash@0 {
  		compatible = "m25p80", "jedec,spi-nor";
  		reg = <0x0>;
-		spi-tx-bus-width = <1>;
+		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>;
  		spi-max-frequency = <108000000>;
  	};

Applied.
M

author maintainer
#7 lore raw

PATCH v2 4/6 arm64: zynqmp: Add L2 cache nodes

In reply to Michal Simek

From: Radhey Shyam Pandey <[email protected]>

Describe SoC L2 cache hierarchy.

Signed-off-by Radhey Shyam Pandey <[email protected]>
Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- Update commit message to remove Linux part - reported by Laurent

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it.

---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +9 -0
index a961bb6f31ff..02bd75900238 100644
@@ -33,6 +33,7 @@ cpu0: cpu@0 {
 			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0x0>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@1 {

@@ -42,6 +43,7 @@ cpu1: cpu@1 {
 			reg = <0x1>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@2 {

@@ -51,6 +53,7 @@ cpu2: cpu@2 {
 			reg = <0x2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@3 {

@@ -60,6 +63,12 @@ cpu3: cpu@3 {
 			reg = <0x3>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
 		};
 
 		idle-states {
Signature · 1 line
2.36.1
author maintainer
#8 lore raw

Re: [PATCH v2 4/6] arm64: zynqmp: Add L2 cache nodes

Quoted 48 lines · Michal Simek

From: Radhey Shyam Pandey <[email protected]>

Describe SoC L2 cache hierarchy.

Signed-off-by Radhey Shyam Pandey <[email protected]>
Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- Update commit message to remove Linux part - reported by Laurent

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it.

---
  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++
  1 file changed, 9 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +3 -0
index a961bb6f31ff..02bd75900238 100644
@@ -33,6 +33,7 @@ cpu0: cpu@0 {
  			operating-points-v2 = <&cpu_opp_table>;
  			reg = <0x0>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 
  		cpu1: cpu@1 {

@@ -42,6 +43,7 @@ cpu1: cpu@1 {
  			reg = <0x1>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 
  		cpu2: cpu@2 {

@@ -51,6 +53,7 @@ cpu2: cpu@2 {
  			reg = <0x2>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
  		};
 
  		cpu3: cpu@3 {

arch/arm64/boot/dts/xilinx/zynqmp.dtsi cpu3: cpu@3 { · line 71

Quoted 9 lines
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +6 -0
@@ -60,6 +63,12 @@ cpu3: cpu@3 {
  			reg = <0x3>;
  			operating-points-v2 = <&cpu_opp_table>;
  			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;

Here should be also cache-unified;

Thanks,
Michal

_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

author maintainer
#9 lore raw

PATCH v2 5/6 arm64: zynqmp: Add pmu interrupt-affinity

In reply to Michal Simek

From: Radhey Shyam Pandey <[email protected]>

Based on dt-binding "This property should present when there is more than a single SPI" that's also case that's why explicitly specify interrupt affinity to avoid incorrect usage.

Signed-off-by Radhey Shyam Pandey <[email protected]>
Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- Update commit message to remove OS content - reported by Laurent

This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing.

---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +4 -0
index 02bd75900238..fc5e21bc647c 100644
@@ -164,6 +164,10 @@ pmu {
 			     <0 144 4>,
 			     <0 145 4>,
 			     <0 146 4>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
 	};
 
 	psci {
Signature · 1 line
2.36.1
author maintainer Applied
#10 lore raw

Re: [PATCH v2 5/6] arm64: zynqmp: Add pmu interrupt-affinity

Quoted 26 lines · Michal Simek

From: Radhey Shyam Pandey <[email protected]>

Based on dt-binding "This property should present when there is more than a single SPI" that's also case that's why explicitly specify interrupt affinity to avoid incorrect usage.

Signed-off-by Radhey Shyam Pandey <[email protected]>
Signed-off-by Michal Simek <[email protected]>

---

Changes in v2:
- Update commit message to remove OS content - reported by Laurent

This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing.

---
  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
  1 file changed, 4 insertions(+)
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +0 -0
index 02bd75900238..fc5e21bc647c 100644

arch/arm64/boot/dts/xilinx/zynqmp.dtsi pmu { · line 173

Quoted 10 lines
arch/arm64/boot/dts/xilinx/zynqmp.dtsi +4 -0
@@ -164,6 +164,10 @@ pmu {
  			     <0 144 4>,
  			     <0 145 4>,
  			     <0 146 4>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
  	};
 
  	psci {

Applied.
M

author maintainer
#11 lore raw

PATCH v2 6/6 arm64: zynqmp: Used fixed-partitions for QSPI in k26

In reply to Michal Simek

Using fixed partitions is recommended way how to describe QSPI. Also add label for qspi flash memory to be able to reference it in future.

Signed-off-by Michal Simek <[email protected]>

---

(no changes since v1)

---
 .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts    | 169 +++++++++---------
 1 file changed, 88 insertions(+), 81 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +88 -81
index 84e18fdce775..dfd1a18f5a10 100644
@@ -127,87 +127,94 @@ spi_flash: flash@0 { /* MT25QU512A */
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		spi-max-frequency = <40000000>; /* 40MHz */
-		partition@0 {
-			label = "Image Selector";
-			reg = <0x0 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@80000 {
-			label = "Image Selector Golden";
-			reg = <0x80000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@100000 {
-			label = "Persistent Register";
-			reg = <0x100000 0x20000>; /* 128KB */
-		};
-		partition@120000 {
-			label = "Persistent Register Backup";
-			reg = <0x120000 0x20000>; /* 128KB */
-		};
-		partition@140000 {
-			label = "Open_1";
-			reg = <0x140000 0xC0000>; /* 768KB */
-		};
-		partition@200000 {
-			label = "Image A (FSBL, PMU, ATF, U-Boot)";
-			reg = <0x200000 0xD00000>; /* 13MB */
-		};
-		partition@f00000 {
-			label = "ImgSel Image A Catch";
-			reg = <0xF00000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@f80000 {
-			label = "Image B (FSBL, PMU, ATF, U-Boot)";
-			reg = <0xF80000 0xD00000>; /* 13MB */
-		};
-		partition@1c80000 {
-			label = "ImgSel Image B Catch";
-			reg = <0x1C80000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@1d00000 {
-			label = "Open_2";
-			reg = <0x1D00000 0x100000>; /* 1MB */
-		};
-		partition@1e00000 {
-			label = "Recovery Image";
-			reg = <0x1E00000 0x200000>; /* 2MB */
-			read-only;
-			lock;
-		};
-		partition@2000000 {
-			label = "Recovery Image Backup";
-			reg = <0x2000000 0x200000>; /* 2MB */
-			read-only;
-			lock;
-		};
-		partition@2200000 {
-			label = "U-Boot storage variables";
-			reg = <0x2200000 0x20000>; /* 128KB */
-		};
-		partition@2220000 {
-			label = "U-Boot storage variables backup";
-			reg = <0x2220000 0x20000>; /* 128KB */
-		};
-		partition@2240000 {
-			label = "SHA256";
-			reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
-			read-only;
-			lock;
-		};
-		partition@2280000 {
-			label = "Secure OS Storage";
-			reg = <0x2280000 0x20000>; /* 128KB */
-		};
-		partition@22A0000 {
-			label = "User";
-			reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "Image Selector";
+				reg = <0x0 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@80000 {
+				label = "Image Selector Golden";
+				reg = <0x80000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@100000 {
+				label = "Persistent Register";
+				reg = <0x100000 0x20000>; /* 128KB */
+			};
+			partition@120000 {
+				label = "Persistent Register Backup";
+				reg = <0x120000 0x20000>; /* 128KB */
+			};
+			partition@140000 {
+				label = "Open_1";
+				reg = <0x140000 0xC0000>; /* 768KB */
+			};
+			partition@200000 {
+				label = "Image A (FSBL, PMU, ATF, U-Boot)";
+				reg = <0x200000 0xD00000>; /* 13MB */
+			};
+			partition@f00000 {
+				label = "ImgSel Image A Catch";
+				reg = <0xF00000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@f80000 {
+				label = "Image B (FSBL, PMU, ATF, U-Boot)";
+				reg = <0xF80000 0xD00000>; /* 13MB */
+			};
+			partition@1c80000 {
+				label = "ImgSel Image B Catch";
+				reg = <0x1C80000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@1d00000 {
+				label = "Open_2";
+				reg = <0x1D00000 0x100000>; /* 1MB */
+			};
+			partition@1e00000 {
+				label = "Recovery Image";
+				reg = <0x1E00000 0x200000>; /* 2MB */
+				read-only;
+				lock;
+			};
+			partition@2000000 {
+				label = "Recovery Image Backup";
+				reg = <0x2000000 0x200000>; /* 2MB */
+				read-only;
+				lock;
+			};
+			partition@2200000 {
+				label = "U-Boot storage variables";
+				reg = <0x2200000 0x20000>; /* 128KB */
+			};
+			partition@2220000 {
+				label = "U-Boot storage variables backup";
+				reg = <0x2220000 0x20000>; /* 128KB */
+			};
+			partition@2240000 {
+				label = "SHA256";
+				reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
+				read-only;
+				lock;
+			};
+			partition@2280000 {
+				label = "Secure OS Storage";
+				reg = <0x2280000 0x20000>; /* 128KB */
+			};
+			partition@22A0000 {
+				label = "User";
+				reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
+			};
 		};
 	};
 };
Signature · 1 line
2.36.1
Applied
#12 lore raw

Re: [PATCH v2 6/6] arm64: zynqmp: Used fixed-partitions for QSPI in k26

Quoted 182 lines · Michal Simek

Using fixed partitions is recommended way how to describe QSPI. Also add label for qspi flash memory to be able to reference it in future.

Signed-off-by Michal Simek <[email protected]>

---

(no changes since v1)

---
  .../boot/dts/xilinx/zynqmp-sm-k26-revA.dts    | 169 +++++++++---------
  1 file changed, 88 insertions(+), 81 deletions(-)
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +81 -81
index 84e18fdce775..dfd1a18f5a10 100644
@@ -127,87 +127,94 @@ spi_flash: flash@0 { /* MT25QU512A */
  		spi-tx-bus-width = <4>;
  		spi-rx-bus-width = <4>;
  		spi-max-frequency = <40000000>; /* 40MHz */
-		partition@0 {
-			label = "Image Selector";
-			reg = <0x0 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@80000 {
-			label = "Image Selector Golden";
-			reg = <0x80000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@100000 {
-			label = "Persistent Register";
-			reg = <0x100000 0x20000>; /* 128KB */
-		};
-		partition@120000 {
-			label = "Persistent Register Backup";
-			reg = <0x120000 0x20000>; /* 128KB */
-		};
-		partition@140000 {
-			label = "Open_1";
-			reg = <0x140000 0xC0000>; /* 768KB */
-		};
-		partition@200000 {
-			label = "Image A (FSBL, PMU, ATF, U-Boot)";
-			reg = <0x200000 0xD00000>; /* 13MB */
-		};
-		partition@f00000 {
-			label = "ImgSel Image A Catch";
-			reg = <0xF00000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@f80000 {
-			label = "Image B (FSBL, PMU, ATF, U-Boot)";
-			reg = <0xF80000 0xD00000>; /* 13MB */
-		};
-		partition@1c80000 {
-			label = "ImgSel Image B Catch";
-			reg = <0x1C80000 0x80000>; /* 512KB */
-			read-only;
-			lock;
-		};
-		partition@1d00000 {
-			label = "Open_2";
-			reg = <0x1D00000 0x100000>; /* 1MB */
-		};
-		partition@1e00000 {
-			label = "Recovery Image";
-			reg = <0x1E00000 0x200000>; /* 2MB */
-			read-only;
-			lock;
-		};
-		partition@2000000 {
-			label = "Recovery Image Backup";
-			reg = <0x2000000 0x200000>; /* 2MB */
-			read-only;
-			lock;
-		};
-		partition@2200000 {
-			label = "U-Boot storage variables";
-			reg = <0x2200000 0x20000>; /* 128KB */
-		};
-		partition@2220000 {
-			label = "U-Boot storage variables backup";
-			reg = <0x2220000 0x20000>; /* 128KB */
-		};
-		partition@2240000 {
-			label = "SHA256";
-			reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
-			read-only;
-			lock;
-		};
-		partition@2280000 {
-			label = "Secure OS Storage";
-			reg = <0x2280000 0x20000>; /* 128KB */
-		};
-		partition@22A0000 {
-			label = "User";
-			reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "Image Selector";
+				reg = <0x0 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@80000 {
+				label = "Image Selector Golden";
+				reg = <0x80000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@100000 {
+				label = "Persistent Register";
+				reg = <0x100000 0x20000>; /* 128KB */
+			};
+			partition@120000 {
+				label = "Persistent Register Backup";
+				reg = <0x120000 0x20000>; /* 128KB */
+			};
+			partition@140000 {
+				label = "Open_1";
+				reg = <0x140000 0xC0000>; /* 768KB */
+			};
+			partition@200000 {
+				label = "Image A (FSBL, PMU, ATF, U-Boot)";
+				reg = <0x200000 0xD00000>; /* 13MB */
+			};
+			partition@f00000 {
+				label = "ImgSel Image A Catch";
+				reg = <0xF00000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@f80000 {
+				label = "Image B (FSBL, PMU, ATF, U-Boot)";
+				reg = <0xF80000 0xD00000>; /* 13MB */
+			};
+			partition@1c80000 {
+				label = "ImgSel Image B Catch";
+				reg = <0x1C80000 0x80000>; /* 512KB */
+				read-only;
+				lock;
+			};
+			partition@1d00000 {
+				label = "Open_2";
+				reg = <0x1D00000 0x100000>; /* 1MB */
+			};
+			partition@1e00000 {
+				label = "Recovery Image";
+				reg = <0x1E00000 0x200000>; /* 2MB */
+				read-only;
+				lock;
+			};
+			partition@2000000 {
+				label = "Recovery Image Backup";
+				reg = <0x2000000 0x200000>; /* 2MB */
+				read-only;
+				lock;
+			};
+			partition@2200000 {
+				label = "U-Boot storage variables";
+				reg = <0x2200000 0x20000>; /* 128KB */
+			};
+			partition@2220000 {
+				label = "U-Boot storage variables backup";
+				reg = <0x2220000 0x20000>; /* 128KB */
+			};
+			partition@2240000 {
+				label = "SHA256";
+				reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
+				read-only;
+				lock;
+			};
+			partition@2280000 {

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts spi_flash: flash@0 { /* MT25QU512A */ · line 220

Quoted 10 lines
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +7 -0
+				label = "Secure OS Storage";
+				reg = <0x2280000 0x20000>; /* 128KB */
+			};
+			partition@22A0000 {
+				label = "User";
+				reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
+			};
  		};
  	};
  };

Applied.
M

Signature · 6 lines
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs