Add support for Intel SocFPGA DWC3 USB controller
Subsystems (3)
v2 cover Add support for Intel SocFPGA DWC3 USB controller
From: Adrian Ng Ho Yin <[email protected]>
This patch set adds binding for Intel SoCFPGA DWC3 controller.
The new binding differs from the existing binding intel,keembay-dwc3.yaml as the required properties are different.
This patch also adds compatible string for Intel Agilex5 in DWC3 simple glue driver.
---
V1-> V2:
- update commit title.
- update compatible string to match file name.
- update item description for clocks, reg and resets.
- removed defines for macro and update to use numbers.
- update node name to be generic.
Adrian Ng Ho Yin (2):
dt-bindings: usb: Add Intel SoCFPGA USB controller
usb: dwc3: of-simple: Add compatible string for Intel Agilex5 platform
.../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ drivers/usb/dwc3/dwc3-of-simple.c | 1 + 2 files changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml
Signature · 1 line
2.26.2
PATCH v2 1/2 dt-bindings: usb: Add Intel SoCFPGA USB controller
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.
--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +84 -0
@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties: + compatible: + items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3 + + reg: + description: Offset and length of DWC3 controller register + maxItems: 1 + + clocks: + items: + - description: Controller Master/Core clock + - description: Controller Suspend clock + + ranges: true + + resets: + description: A list of phandles for resets listed in reset-names + maxItems: 2 + + reset-names: + items: + - const: dwc3 + - const: dwc3-ecc + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + +# Required child node: + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: snps,dwc3.yaml# + +required: + - compatible + - reg + - clocks + - resets + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/reset/altr,rst-mgr.h> + + usb@11000000 { + compatible = "intel,agilex5-dwc3", "intel,socfpga-dwc3"; + reg = <0x11000000 0x100000>; + ranges; + clocks = <&clkmgr 54>, + <&clkmgr 55>; + resets = <&rst USB0_RESET>, <&rst USB1_RESET>; + reset-names = "dwc3", "dwc3-ecc"; + #address-cells = <1>; + #size-cells = <1>; + + usb@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + }; + }; +
Signature · 1 line
2.26.2
Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
Quoted 26 lines · On 24/07/2023 08:36, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlDocumentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +7
-0@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 17
Quoted 10 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +10
-0+ +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties: + compatible: + items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3
So you did not even wait for my answer? What happened here with this compatible? I asked you to change file name, not add intel,socfpga-dwc3. Again - why using different style for Agilex? Which style is correct?
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 20
Quoted 3 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +3
-0+ + reg: + description: Offset and length of DWC3 controller register
What happened here? It wasn't here before.
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 31
Quoted 11 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +11
-0+ maxItems: 1 + + clocks: + items: + - description: Controller Master/Core clock + - description: Controller Suspend clock + + ranges: true + + resets: + description: A list of phandles for resets listed in reset-names
Neither was this useless description, it is obvious.
Quoted 26 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +26
-0+ maxItems: 2 + + reset-names: + items: + - const: dwc3 + - const: dwc3-ecc + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + +# Required child node: + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: snps,dwc3.yaml# + +required: + - compatible + - reg + - clocks + - resets + - ranges +
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 67
Quoted 10 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +10
-0+additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/reset/altr,rst-mgr.h> + + usb@11000000 { + compatible = "intel,agilex5-dwc3", "intel,socfpga-dwc3";
Still wrong indentation....
Quoted 7 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +7
-0+ reg = <0x11000000 0x100000>; + ranges; + clocks = <&clkmgr 54>, + <&clkmgr 55>; + resets = <&rst USB0_RESET>, <&rst USB1_RESET>; + reset-names = "dwc3", "dwc3-ecc"; + #address-cells = <1>;
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 84
Quoted 10 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +10
-0+ #size-cells = <1>; + + usb@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + }; + }; +
Drop trailing line.
Instead of resending just after your reply, allow for reviewer to respond.
Best regards,
Krzysztof
RE: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
Quoted 44 lines
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 3:05 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 34 lines · On 24/07/2023 08:36, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamldiff --git
a/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlb/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlnew file mode 100644
index 000000000000..e36b087c2651Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +12
-0@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties: + compatible:
Quoted 9 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 17
Quoted 4 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +4
-0+ items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3So you did not even wait for my answer? What happened here with this compatible? I asked you to change file name, not add intel,socfpga-dwc3. Again - why using different style for Agilex? Which style is correct?
The intention is to use a common binding for Intel SoCFPGA products that is using DWC3 controller. This is done with reference to qcom,dwc3.yaml.
Quoted 5 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 20
Quoted 3 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +3
-0+ + reg: + description: Offset and length of DWC3 controller registerWhat happened here? It wasn't here before.
Remove unnecessary description in V3.
Quoted 14 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 31
Quoted 12 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +11
-0+ maxItems: 1 + + clocks: + items: + - description: Controller Master/Core clock + - description: Controller Suspend clock + + ranges: true + + resets: + description: A list of phandles for resets listed in reset-namesNeither was this useless description, it is obvious.
Remove unnecessary description in V3.
Quoted 31 lines
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +30
-0+ maxItems: 2 + + reset-names: + items: + - const: dwc3 + - const: dwc3-ecc + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + +# Required child node: + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: snps,dwc3.yaml# + +required: + - compatible + - reg + - clocks + - resets + - ranges + +additionalProperties: false + +examples: + - |
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 67
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +6
-0+ #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/reset/altr,rst-mgr.h> + + usb@11000000 { + compatible = "intel,agilex5-dwc3", "intel,socfpga-dwc3";Still wrong indentation....
Update indentation in V3
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +11
-0+ reg = <0x11000000 0x100000>; + ranges; + clocks = <&clkmgr 54>, + <&clkmgr 55>; + resets = <&rst USB0_RESET>, <&rst USB1_RESET>; + reset-names = "dwc3", "dwc3-ecc"; + #address-cells = <1>; + #size-cells = <1>; + + usb@11000000 { + compatible = "snps,dwc3";
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 84
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +6
-0+ reg = <0x11000000 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + }; + }; +Drop trailing line.
Drop trailing line in V3.
Quoted 3 lines
Instead of resending just after your reply, allow for reviewer to respond.
My apologies will wait for reply.
Thank You
Adrian
Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
Quoted 54 lines · Adrian Ho Yin
Quoted 44 lines
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 3:05 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 34 lines · On 24/07/2023 08:36, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamldiff --git
a/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlb/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlnew file mode 100644
index 000000000000..e36b087c2651Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +12
-0@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties: + compatible:Quoted 9 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 17
Quoted 4 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +4
-0+ items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3So you did not even wait for my answer? What happened here with this compatible? I asked you to change file name, not add intel,socfpga-dwc3. Again - why using different style for Agilex? Which style is correct?
Quoted 2 lines
The intention is to use a common binding for Intel SoCFPGA products that is using DWC3 controller. This is done with reference to qcom,dwc3.yaml.
Nope, your driver change does not match it at all. Your explanation does not make any sense.
Don't answer only half of my questions. So third time - the last: since you add new style for Agilex, which style of Agilex compatibles is correct?
Best regards,
Krzysztof
RE: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
Quoted 67 lines
-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 3:28 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 55 lines · Adrian Ho Yin
Quoted 45 lines
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 3:05 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 34 lines · On 24/07/2023 08:36, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamldiff --git
a/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlb/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlnew file mode 100644
index 000000000000..e36b087c2651Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +12
-0@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties: + compatible:Quoted 9 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 17
Quoted 4 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +4
-0+ items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3So you did not even wait for my answer? What happened here with this compatible? I asked you to change file name, not add intel,socfpga-dwc3. Again - why using different style for Agilex? Which style is correct?
Quoted 1 line
The intention is to use a common binding for Intel SoCFPGA products that is
Quoted 9 lines
using DWC3 controller.
Quoted 1 line
This is done with reference to qcom,dwc3.yaml.
Nope, your driver change does not match it at all. Your explanation does not make any sense.
Don't answer only half of my questions. So third time - the last: since you add new style for Agilex, which style of Agilex compatibles is correct?
My apologies.
In your opinion which is the proper practice?
1. Create new binding for new products that is using the same controller.
2. Create a common binding that will be used by products using the same controller? Referring to the current bindings that are available the two options are being practiced at the moment.
If option 1 is the proper practice the correct Agilex compatible is intel,agilex5-dwc3. To rework the binding to cater for agilex5-dwc3 only. The compatible in glue driver will remain the same.
If option 2 is the proper practice then the correct Agilex compatible is intel,socfpga-dwc3. To update compatible in glue driver in V3.
Thank You
Adrian Ng
Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
Quoted 67 lines · Adrian Ho Yin
Quoted 67 lines
-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 3:28 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 56 lines · Adrian Ho Yin
Quoted 45 lines
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 3:05 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 34 lines · On 24/07/2023 08:36, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamldiff --git
a/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlb/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlnew file mode 100644
index 000000000000..e36b087c2651Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +12
-0@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties: + compatible:Quoted 9 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 17
Quoted 4 lines
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +4
-0+ items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3So you did not even wait for my answer? What happened here with this compatible? I asked you to change file name, not add intel,socfpga-dwc3. Again - why using different style for Agilex? Which style is correct?
The intention is to use a common binding for Intel SoCFPGA products that is
Quoted 8 lines
Quoted 8 lines
using DWC3 controller.
Quoted 1 line
This is done with reference to qcom,dwc3.yaml.
Nope, your driver change does not match it at all. Your explanation does not make any sense.
Don't answer only half of my questions. So third time - the last: since you add new style for Agilex, which style of Agilex compatibles is correct?
I still did not receive here answer. Which style, naming convention for agilex is correct for your platform?
Why this:
git grep agilex | grep intel,
gives different compatibles than you start here? I assume Intel/Altera knows better the platform so will provide here some guidance. If unsure, please consult your colleagues.
Quoted 5 lines
Quoted 1 line
My apologies.
In your opinion which is the proper practice?
1. Create new binding for new products that is using the same controller.
What is "new binding"? What do you mean by that? New file, then not.
Quoted 9 lines
2. Create a common binding that will be used by products using the same controller? Referring to the current bindings that are available the two options are being practiced at the moment.
If option 1 is the proper practice the correct Agilex compatible is intel,agilex5-dwc3. To rework the binding to cater for agilex5-dwc3 only. The compatible in glue driver will remain the same.
If option 2 is the proper practice then the correct Agilex compatible is intel,socfpga-dwc3. To update compatible in glue driver in V3.
Recommended practice is to use specific compatible for both: your device and as fallback for any future devices. In certain cases, option 2 is okay.
Best regards,
Krzysztof
RE: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
Quoted 99 lines
-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 4:55 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 25 lines · Adrian Ho Yin
Quoted 25 lines
-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 3:28 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 13 lines · Adrian Ho Yin
Quoted 13 lines
From: Krzysztof Kozlowski <[email protected]>
Sent: Monday, 24 July, 2023 3:05 PM
To: Ng, Adrian Ho Yin <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 2 lines · On 24/07/2023 08:36, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
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Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices. Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.
Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84+++++++++++++++++++
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Documentation/devicetree/bindings/usb/intel,socfpga-
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1 file changed, 84 insertions(+) create mode 100644
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamldiff --git
a/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlb/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlnew file mode 100644
index 000000000000..e36b087c2651Documentation/devicetree/bindings/usb/intel,socfpga- new file +0
-0dwc3.yam
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Documentation/devicetree/bindings/usb/intel,socfpga- new file +12
-0@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML +1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties:Quoted 8 lines
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Documentation/devicetree/bindings/usb/intel,socfpga- line 17
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Documentation/devicetree/bindings/usb/intel,socfpga- new file +5
-0+ compatible: + items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3So you did not even wait for my answer? What happened here with this compatible? I asked you to change file name, not add intel,socfpga-
dwc3.
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Again - why using different style for Agilex? Which style is correct?
The intention is to use a common binding for Intel SoCFPGA products that is
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using DWC3 controller.
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This is done with reference to qcom,dwc3.yaml.
Nope, your driver change does not match it at all. Your explanation does not make any sense.
Don't answer only half of my questions. So third time - the last:
since you add new style for Agilex, which style of Agilex compatibles iscorrect?
I still did not receive here answer. Which style, naming convention for agilex is correct for your platform?
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Why this:
git grep agilex | grep intel,gives different compatibles than you start here? I assume Intel/Altera knows better the platform so will provide here some guidance. If unsure, please consult your colleagues.
Noted. Will consult Intel Linux group to get the correct naming convention and go through another round of internal review prior to address the issues/concerns raised before submitting the revised patches.
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My apologies.
In your opinion which is the proper practice?
1. Create new binding for new products that is using the same controller.What is "new binding"? What do you mean by that? New file, then not.
Yes. New Binding means new file. Will not proceed with option 1.
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2. Create a common binding that will be used by products using the same
controller?
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Referring to the current bindings that are available the two options are
being practiced at the moment.
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If option 1 is the proper practice the correct Agilex compatible is
intel,agilex5-dwc3.
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To rework the binding to cater for agilex5-dwc3 only. The compatible in
glue driver will remain the same.
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If option 2 is the proper practice then the correct Agilex compatible is
intel,socfpga-dwc3.
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To update compatible in glue driver in V3.
Recommended practice is to use specific compatible for both: your device and as fallback for any future devices. In certain cases, option 2 is okay.
Noted. Thank you for the feedback.
Thank You
Adrian Ng
Greg KH
maintainerRe: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
In reply to [email protected]Quoted 7 lines · On Mon, Jul 24, 2023 at 02:36:58PM +0800, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.
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Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml
You don't seem to have followed the rules that your employer has for kernel contributions, so we can't take this, sorry. Please work with the Intel Linux kernel group to resolve those issues first, and then resubmit the patches properly.
thanks,
greg k-h
RE: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
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-----Original Message-----
From: Greg KH <[email protected]>
Sent: Tuesday, 25 July, 2023 9:26 PM
To: Ng, Adrian Ho Yin <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 7 lines · On Mon, Jul 24, 2023 at 02:36:58PM +0800, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.Quoted 6 lines
Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml
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You don't seem to have followed the rules that your employer has for kernel contributions, so we can't take this, sorry. Please work with the Intel Linux kernel group to resolve those issues first, and then resubmit the patches properly.
Noted. Will work with the intel Linux group to resolve the issues/concerns prior to resubmitting the patches. Thank You for the feedback and sorry for the inconveniences.
Thank You.
Adrian Ng
Rob Herring
maintainerRe: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
In reply to [email protected]Quoted 58 lines · On Mon, Jul 24, 2023 at 02:36:58PM +0800, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlDocumentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +39
-0@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties: + compatible: + items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3 + + reg: + description: Offset and length of DWC3 controller register + maxItems: 1 + + clocks: + items: + - description: Controller Master/Core clock + - description: Controller Suspend clock + + ranges: true + + resets: + description: A list of phandles for resets listed in reset-names + maxItems: 2 + + reset-names: + items: + - const: dwc3 + - const: dwc3-ecc + + '#address-cells':
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 49
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +10
-0+ enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + +# Required child node: + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: snps,dwc3.yaml#
One node, no wrapper node and dwc3 child node please unless you have actual registers for the wrapper. Based on the example having the same register addresses in both nodes, you don't need the wrapper.
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +9
-0+ +required: + - compatible + - reg + - clocks + - resets + - ranges + +additionalProperties: false
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 68
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +10
-0+ +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/reset/altr,rst-mgr.h> + + usb@11000000 { + compatible = "intel,agilex5-dwc3", "intel,socfpga-dwc3"; + reg = <0x11000000 0x100000>;
You really have 1MB worth of registers? That chews up 1MB of kernel virtual space. Not a big deal for 64-bit, but it is a problem on 32-bit systems. Define the length to just what you need.
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 75
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +7
-0+ ranges; + clocks = <&clkmgr 54>, + <&clkmgr 55>; + resets = <&rst USB0_RESET>, <&rst USB1_RESET>; + reset-names = "dwc3", "dwc3-ecc"; + #address-cells = <1>; + #size-cells = <1>;
BTW, this implies that you can only DMA 32-bit bits. Not sure if the dwc3 supports more.
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +9
-0+ + usb@11000000 { + compatible = "snps,dwc3"; + reg = <0x11000000 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + }; + }; +Signature · 1 line
2.26.2
RE: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controller
Quoted 78 lines
-----Original Message-----
From: Rob Herring <[email protected]>
Sent: Thursday, 27 July, 2023 12:29 AM
To: Ng, Adrian Ho Yin <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v2 1/2] dt-bindings: usb: Add Intel SoCFPGA USB controllerQuoted 66 lines · On Mon, Jul 24, 2023 at 02:36:58PM +0800, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Existing binding intel,keembay-dwc3.yaml does not have the required properties for Intel SoCFPGA devices.
Introduce new binding description for Intel SoCFPGA USB controller which will be used for current and future SoCFPGA devices.Signed-off-by Adrian Ng Ho Yin <[email protected]>--- .../bindings/usb/intel,socfpga-dwc3.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644
Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamldiff --git
a/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlb/Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yamlnew file mode 100644
index 000000000000..e36b087c2651Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +44
-0@@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,socfpga-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA DWC3 USB controller + +maintainers: + - Adrian Ng Ho Yin <[email protected]> + +properties: + compatible: + items: + - enum: + - intel,agilex5-dwc3 + - const: intel,socfpga-dwc3 + + reg: + description: Offset and length of DWC3 controller register + maxItems: 1 + + clocks: + items: + - description: Controller Master/Core clock + - description: Controller Suspend clock + + ranges: true + + resets: + description: A list of phandles for resets listed in reset-names + maxItems: 2 + + reset-names: + items: + - const: dwc3 + - const: dwc3-ecc + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + +# Required child node:
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 49
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +4
-0+ +patternProperties: + "^usb@[0-9a-f]+$": + $ref: snps,dwc3.yaml#One node, no wrapper node and dwc3 child node please unless you have actual registers for the wrapper. Based on the example having the same register addresses in both nodes, you don't need the wrapper.
Noted. To remove child node in next patch submission.
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +15
-0+ +required: + - compatible + - reg + - clocks + - resets + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/reset/altr,rst-mgr.h>
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 68
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +4
-0+ + usb@11000000 { + compatible = "intel,agilex5-dwc3", "intel,socfpga-dwc3"; + reg = <0x11000000 0x100000>;You really have 1MB worth of registers? That chews up 1MB of kernel virtual space. Not a big deal for 64-bit, but it is a problem on 32-bit systems. Define the length to just what you need.
To update reg length in next patch submission.
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml line 75
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Documentation/devicetree/bindings/usb/intel,socfpga-dwc3.yaml new file +7
-0+ ranges; + clocks = <&clkmgr 54>, + <&clkmgr 55>; + resets = <&rst USB0_RESET>, <&rst USB1_RESET>; + reset-names = "dwc3", "dwc3-ecc"; + #address-cells = <1>; + #size-cells = <1>;BTW, this implies that you can only DMA 32-bit bits. Not sure if the dwc3 supports more.
DWC3 supports DMA 64 bits.
In properties address-cells support value 1 and 2. To update example to indicate 64-bit DMA support.
Thank You.
Adrian Ng
PATCH v2 2/2 usb: dwc3: of-simple: Add compatible string for Intel Agilex5 platform
In reply to [email protected]From: Adrian Ng Ho Yin <[email protected]>
Add compatible string to use this generic glue layer to support Intel Agilex5 dwc3 controller.
--- drivers/usb/dwc3/dwc3-of-simple.c | 1 + 1 file changed, 1 insertion(+)
drivers/usb/dwc3/dwc3-of-simple.c +1 -0
@@ -175,6 +175,7 @@ static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "allwinner,sun50i-h6-dwc3" }, { .compatible = "hisilicon,hi3670-dwc3" }, { .compatible = "intel,keembay-dwc3" }, + { .compatible = "intel,agilex5-dwc3" }, {/* Sentinel */ } };MODULE_DEVICE_TABLE (of, of_dwc3_simple_match);
Signature · 1 line
2.26.2
Re: [PATCH v2 2/2] usb: dwc3: of-simple: Add compatible string for Intel Agilex5 platform
Quoted 15 lines · On 24/07/2023 08:37, [email protected] wrote:
From: Adrian Ng Ho Yin <[email protected]>
Add compatible string to use this generic glue layer to support Intel Agilex5 dwc3 controller.
Signed-off-by Adrian Ng Ho Yin <[email protected]>--- drivers/usb/dwc3/dwc3-of-simple.c | 1 + 1 file changed, 1 insertion(+)drivers/usb/dwc3/dwc3-of-simple.c +0
-0
drivers/usb/dwc3/dwc3-of-simple.c static const struct of_device_id of_dwc3_simple_match[] = { · line 178
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drivers/usb/dwc3/dwc3-of-simple.c +1
-0@@ -175,6 +175,7 @@ static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "allwinner,sun50i-h6-dwc3" }, { .compatible = "hisilicon,hi3670-dwc3" }, { .compatible = "intel,keembay-dwc3" }, + { .compatible = "intel,agilex5-dwc3" },
NAK. Your binding says something entirely different. Explanation you gave me also says different.
Best regards,
Krzysztof