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arm64: dts: renesas: r8a779h0: Add full CA76 CPU core support

PATCH New Geert Uytterhoeven 1 participant 6 messages Feb 1, 2024

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Device tree bindings Arm/RISC-V/Renesas architecture
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Geert Uytterhoeven

author maintainer
#0 lore raw

cover arm64: dts: renesas: r8a779h0: Add full CA76 CPU core support

Hi all,

This patch series adds full support for the four Cortex-A76 CPU cores on the Renesas R-Car V4M (R8A779H0) Soc. It has been tested on the Gray Hawk Single development board.

I intend to queue this in renesas-devel for v6.9.

Thanks for your comments!

Duy Nguyen (5):
arm64: dts: renesas: r8a779h0: Add L3 cache controller
arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores
arm64: dts: renesas: r8a779h0: Add CPUIdle support
arm64: dts: renesas: r8a779h0: Add CPU core clocks
arm64: dts: renesas: r8a779h0: Add CA76 operating points

 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 99 +++++++++++++++++++++++
 1 file changed, 99 insertions(+)
Signature · 12 lines
2.34.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds
author maintainer
#1 lore raw

PATCH 1/5 arm64: dts: renesas: r8a779h0: Add L3 cache controller

From: Duy Nguyen <[email protected]>

Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by Duy Nguyen <[email protected]>
Signed-off-by Geert Uytterhoeven <[email protected]>

---
Changes compared to the BSP:
- Rename L3_CA76_0 label to L3_CA76,
- Rename cache-controller-0 node to cache-controller.

---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/renesas/r8a779h0.dtsi +8 -0
index eb555cbf51a41001..f47695158d991288 100644
@@ -23,6 +23,14 @@ a76_0: cpu@0 {
 			reg = <0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
+			next-level-cache = <&L3_CA76>;
+		};
+
+		L3_CA76: cache-controller {
+			compatible = "cache";
+			power-domains = <&sysc R8A779H0_PD_A2E0D0>;
+			cache-unified;
+			cache-level = <3>;
 		};
 	};
Signature · 1 line
2.34.1
author maintainer
#2 lore raw

PATCH 2/5 arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores

In reply to Geert Uytterhoeven

From: Duy Nguyen <[email protected]>

Complete the description of the Cortex-A76 CPU cores and L3 cache controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU topology and PSCI support for enabling CPU cores.

Signed-off-by Duy Nguyen <[email protected]>
Signed-off-by Geert Uytterhoeven <[email protected]>

---
Changes compared to the BSP:
- Rename L3_CA76_0 label to L3_CA76,
- Move psci node to preserve sort order (alphabetical),
- Drop GIC_CPU_MASK_SIMPLE changes, as GICv3 PPI interrupt specifiers have no such masks.

---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 50 +++++++++++++++++++++++
 1 file changed, 50 insertions(+)
arch/arm64/boot/dts/renesas/r8a779h0.dtsi +50 -0
index f47695158d991288..88c5dcbc38d59dab 100644
@@ -18,12 +18,57 @@ cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a76_0>;
+				};
+				core1 {
+					cpu = <&a76_1>;
+				};
+				core2 {
+					cpu = <&a76_2>;
+				};
+				core3 {
+					cpu = <&a76_3>;
+				};
+			};
+		};
+
 		a76_0: cpu@0 {
 			compatible = "arm,cortex-a76";
 			reg = <0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
 			next-level-cache = <&L3_CA76>;
+			enable-method = "psci";
+		};
+
+		a76_1: cpu@100 {
+			compatible = "arm,cortex-a76";
+			reg = <0x100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
+			next-level-cache = <&L3_CA76>;
+			enable-method = "psci";
+		};
+
+		a76_2: cpu@200 {
+			compatible = "arm,cortex-a76";
+			reg = <0x200>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
+			next-level-cache = <&L3_CA76>;
+			enable-method = "psci";
+		};
+
+		a76_3: cpu@300 {
+			compatible = "arm,cortex-a76";
+			reg = <0x300>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
+			next-level-cache = <&L3_CA76>;
+			enable-method = "psci";
 		};
 
 		L3_CA76: cache-controller {

@@ -53,6 +98,11 @@ pmu-a76 {
 		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
 	/* External SCIF clock - to be overridden by boards that provide it */
 	scif_clk: scif-clk {
 		compatible = "fixed-clock";
Signature · 1 line
2.34.1
author maintainer
#3 lore raw

PATCH 3/5 arm64: dts: renesas: r8a779h0: Add CPUIdle support

In reply to Geert Uytterhoeven

From: Duy Nguyen <[email protected]>

Support CPUIdle for ARM Cortex-A76 on R-Car V4M.

Signed-off-by Duy Nguyen <[email protected]>
Signed-off-by Geert Uytterhoeven <[email protected]>
---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
arch/arm64/boot/dts/renesas/r8a779h0.dtsi +17 -0
index 88c5dcbc38d59dab..b3255bba69e3e6da 100644
@@ -42,6 +42,7 @@ a76_0: cpu@0 {
 			power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
 			next-level-cache = <&L3_CA76>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_1: cpu@100 {

@@ -51,6 +52,7 @@ a76_1: cpu@100 {
 			power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
 			next-level-cache = <&L3_CA76>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_2: cpu@200 {

@@ -60,6 +62,7 @@ a76_2: cpu@200 {
 			power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
 			next-level-cache = <&L3_CA76>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_3: cpu@300 {

@@ -69,6 +72,20 @@ a76_3: cpu@300 {
 			power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
 			next-level-cache = <&L3_CA76>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <400>;
+				exit-latency-us = <500>;
+				min-residency-us = <4000>;
+			};
 		};
 
 		L3_CA76: cache-controller {
Signature · 1 line
2.34.1
author maintainer
#4 lore raw

PATCH 4/5 arm64: dts: renesas: r8a779h0: Add CPU core clocks

In reply to Geert Uytterhoeven

From: Duy Nguyen <[email protected]>

Describe the clocks for the four Cortex-A76 CPU cores. CA76 CPU cores 0,1,2,3 are clocked by ZC0,ZC1,ZC2,ZC3.

Signed-off-by Duy Nguyen <[email protected]>
Signed-off-by Geert Uytterhoeven <[email protected]>
---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/renesas/r8a779h0.dtsi +4 -0
index b3255bba69e3e6da..622775f6160f55bd 100644
@@ -43,6 +43,7 @@ a76_0: cpu@0 {
 			next-level-cache = <&L3_CA76>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
 		};
 
 		a76_1: cpu@100 {

@@ -53,6 +54,7 @@ a76_1: cpu@100 {
 			next-level-cache = <&L3_CA76>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
 		};
 
 		a76_2: cpu@200 {

@@ -63,6 +65,7 @@ a76_2: cpu@200 {
 			next-level-cache = <&L3_CA76>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
 		};
 
 		a76_3: cpu@300 {

@@ -73,6 +76,7 @@ a76_3: cpu@300 {
 			next-level-cache = <&L3_CA76>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
 		};
 
 		idle-states {
Signature · 1 line
2.34.1
author maintainer
#5 lore raw

PATCH 5/5 arm64: dts: renesas: r8a779h0: Add CA76 operating points

In reply to Geert Uytterhoeven

From: Duy Nguyen <[email protected]>

Add operating points for running the Cortex-A76 CPU cores on R-Car V4M at various speeds, up to the Normal (1.0 GHz).

Signed-off-by Duy Nguyen <[email protected]>
Signed-off-by Geert Uytterhoeven <[email protected]>
---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
arch/arm64/boot/dts/renesas/r8a779h0.dtsi +20 -0
index 622775f6160f55bd..4e9e487ec51661fd 100644
@@ -14,6 +14,22 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <825000>;
+			clock-latency-ns = <500000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <825000>;
+			clock-latency-ns = <500000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -44,6 +60,7 @@ a76_0: cpu@0 {
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		a76_1: cpu@100 {

@@ -55,6 +72,7 @@ a76_1: cpu@100 {
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		a76_2: cpu@200 {

@@ -66,6 +84,7 @@ a76_2: cpu@200 {
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		a76_3: cpu@300 {

@@ -77,6 +96,7 @@ a76_3: cpu@300 {
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		idle-states {
Signature · 1 line
2.34.1