arm64: Add support for Airoha EN7581 Soc
Subsystems (4)
v2 cover arm64: Add support for Airoha EN7581 Soc
Introduce basic support for Airoha EN7581 Soc and EN7581 Evaluation Board.
Changes since v1:
- add missing en7581 entry in airoha binding
- fix checkpatch errors
Daniel Danzberger (3):
arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board
arm64: add Airoha EN7581 platform
arm64: defconfig: enable Airoha platform
Lorenzo Bianconi (1):
dt-bindings: arm64: dts: airoha: Add en7581 series
.../devicetree/bindings/arm/airoha.yaml | 4 + arch/arm64/Kconfig.platforms | 13 ++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/airoha/Makefile | 2 + arch/arm64/boot/dts/airoha/en7581-evb.dts | 27 ++++ arch/arm64/boot/dts/airoha/en7581.dtsi | 137 ++++++++++++++++++ arch/arm64/configs/defconfig | 1 + 7 files changed, 185 insertions(+) create mode 100644 arch/arm64/boot/dts/airoha/Makefile create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi
Signature · 1 line
2.43.2
PATCH v2 1/4 dt-bindings: arm64: dts: airoha: Add en7581 series
Introduce Airoha EN7581 entry in Airoha dts binding.
--- Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/arm/airoha.yaml +4 -0
@@ -22,6 +22,10 @@ properties: - enum: - airoha,en7523-evb - const: airoha,en7523 + - items: + - enum: + - airoha,en7581-evb + - const: airoha,en7581 additionalProperties: true
Signature · 1 line
2.43.2
Re: [PATCH v2 1/4] dt-bindings: arm64: dts: airoha: Add en7581 series
Quoted 7 lines · Lorenzo Bianconi
Introduce Airoha EN7581 entry in Airoha dts binding.
Signed-off-by Lorenzo Bianconi <[email protected]>--- Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++ 1 file changed, 4 insertions(+)
Best regards,
Krzysztof
PATCH v2 2/4 arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board
In reply to Lorenzo BianconiFrom: Daniel Danzberger <[email protected]>
Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles.
--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/airoha/Makefile | 2 + arch/arm64/boot/dts/airoha/en7581-evb.dts | 27 +++++ arch/arm64/boot/dts/airoha/en7581.dtsi | 137 ++++++++++++++++++++++ 4 files changed, 167 insertions(+) create mode 100644 arch/arm64/boot/dts/airoha/Makefile create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi
arch/arm64/boot/dts/Makefile +1 -0
@@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += actions +subdir-y += airoha subdir-y += allwinner subdir-y += altera subdir-y += amazon
arch/arm64/boot/dts/airoha/Makefile new file +2 -0
@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +27 -0
@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7581.dtsi" + +/ { + model = "Airoha EN7581 Evaluation Board"; + compatible = "airoha,en7581-evb", "airoha,en7581"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +};
arch/arm64/boot/dts/airoha/en7581.dtsi new file +137 -0
137 lines not on this page · raw message
Signature · 1 line
2.43.2
Re: [PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board
Quoted 50 lines · Lorenzo Bianconi
From: Daniel Danzberger <[email protected]>
Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles.
Signed-off-by Daniel Danzberger <[email protected]>Signed-off-by Lorenzo Bianconi <[email protected]>--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/airoha/Makefile | 2 + arch/arm64/boot/dts/airoha/en7581-evb.dts | 27 +++++ arch/arm64/boot/dts/airoha/en7581.dtsi | 137 ++++++++++++++++++++++ 4 files changed, 167 insertions(+) create mode 100644 arch/arm64/boot/dts/airoha/Makefile create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsiarch/arm64/boot/dts/Makefile +1
-0@@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += actions +subdir-y += airoha subdir-y += allwinner subdir-y += altera subdir-y += amazonarch/arm64/boot/dts/airoha/Makefile new file +2
-0@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtbarch/arm64/boot/dts/airoha/en7581-evb.dts new file +8
-0@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7581.dtsi" +
arch/arm64/boot/dts/airoha/en7581-evb.dts line 18
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +10
-0+/ { + model = "Airoha EN7581 Evaluation Board"; + compatible = "airoha,en7581-evb", "airoha,en7581"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon";
You have console below. You don't need earlycon for mainline, broad usage, because it is purely debugging part, so drop entire bootargs.
Quoted 21 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +9
-0+ stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +};arch/arm64/boot/dts/airoha/en7581.dtsi new file +6
-0@@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ {
arch/arm64/boot/dts/airoha/en7581.dtsi line 16
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + npu_binary@84000000 {
No underscores in nodenames.
...
arch/arm64/boot/dts/airoha/en7581.dtsi line 18
Quoted 2 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +2
-0+ + L2_0: l2-cache0 {
Nodename: l2-cache
arch/arm64/boot/dts/airoha/en7581.dtsi line 105
Quoted 7 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +7
-0+ compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + gic: interrupt-controller@9000000 {
Why this is outside of SoC? Where is your SoC node BTW?
It does not look like you tested the DTS against bindings. Please run make dtbs_check W=1 (see Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Quoted 13 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +13
-0+ compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x09000000 0x0 0x20000>, + <0x0 0x09080000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x2000>, + <0x0 0x09500000 0x0 0x2000>, + <0x0 0x09600000 0x0 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; +
arch/arm64/boot/dts/airoha/en7581.dtsi line 128
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + uart1: serial@1fbf0000 {
This cannot be outside of SoC.
arch/arm64/boot/dts/airoha/en7581.dtsi line 135
Quoted 7 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +7
-0+ compatible = "ns16550"; + reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + status = "okay";
Drop
Best regards,
Krzysztof
Re: [PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board
Quoted 56 lines · Lorenzo Bianconi
Quoted 55 lines
From: Daniel Danzberger <[email protected]>
Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles.
Signed-off-by Daniel Danzberger <[email protected]>Signed-off-by Lorenzo Bianconi <[email protected]>--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/airoha/Makefile | 2 + arch/arm64/boot/dts/airoha/en7581-evb.dts | 27 +++++ arch/arm64/boot/dts/airoha/en7581.dtsi | 137 ++++++++++++++++++++++ 4 files changed, 167 insertions(+) create mode 100644 arch/arm64/boot/dts/airoha/Makefile create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsiarch/arm64/boot/dts/Makefile +1
-0@@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += actions +subdir-y += airoha subdir-y += allwinner subdir-y += altera subdir-y += amazonarch/arm64/boot/dts/airoha/Makefile new file +2
-0@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtbarch/arm64/boot/dts/airoha/en7581-evb.dts new file +13
-0@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7581.dtsi" + +/ { + model = "Airoha EN7581 Evaluation Board"; + compatible = "airoha,en7581-evb", "airoha,en7581"; + + aliases {
Quoted 8 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts line 18
Quoted 5 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +5
-0+ serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon";You have console below. You don't need earlycon for mainline, broad usage, because it is purely debugging part, so drop entire bootargs.
ack, I will fix it in v3.
Quoted 27 lines
Quoted 27 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +9
-0+ stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +};arch/arm64/boot/dts/airoha/en7581.dtsi new file +11
-0@@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory {
Quoted 9 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 16
Quoted 5 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +5
-0+ #address-cells = <2>; + #size-cells = <2>; + ranges; + + npu_binary@84000000 {No underscores in nodenames.
...
ack, I will fix it in v3.
Quoted 5 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 18
Quoted 2 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +2
-0+ + L2_0: l2-cache0 {Nodename: l2-cache
ack, I will fix it in v3.
Quoted 9 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 105
Quoted 7 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +7
-0+ compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + gic: interrupt-controller@9000000 {Why this is outside of SoC? Where is your SoC node BTW?
ack, I will fix it in v3.
Quoted 24 lines
It does not look like you tested the DTS against bindings. Please run
make dtbs_check W=1(seeDocumentation/devicetree/bindings/writing-schema.rstor
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).Quoted 17 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +17
-0+ compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x09000000 0x0 0x20000>, + <0x0 0x09080000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x2000>, + <0x0 0x09500000 0x0 0x2000>, + <0x0 0x09600000 0x0 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
Quoted 8 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 128
Quoted 6 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +6
-0+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + uart1: serial@1fbf0000 {This cannot be outside of SoC.
ack, I will fix it in v3.
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 135
Quoted 8 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +7
-0+ compatible = "ns16550"; + reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + status = "okay";Drop
ack, I will fix it in v3.
Regards,
Lorenzo
Quoted 5 lines
Best regards,
Krzysztof
AngeloGioacchino Del Regno
maintainerRe: [PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board
In reply to Lorenzo BianconiIl 21/02/24 01:04, Lorenzo Bianconi ha scritto:
Quoted 57 lines
From: Daniel Danzberger <[email protected]>
Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles.
Signed-off-by Daniel Danzberger <[email protected]>Signed-off-by Lorenzo Bianconi <[email protected]>--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/airoha/Makefile | 2 + arch/arm64/boot/dts/airoha/en7581-evb.dts | 27 +++++ arch/arm64/boot/dts/airoha/en7581.dtsi | 137 ++++++++++++++++++++++ 4 files changed, 167 insertions(+)create mode 100644
arch/arm64/boot/dts/airoha/Makefilecreate mode 100644arch/arm64/boot/dts/airoha/en7581-evb.dtscreate mode 100644arch/arm64/boot/dts/airoha/en7581.dtsiarch/arm64/boot/dts/Makefile +1
-0@@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += actions +subdir-y += airoha subdir-y += allwinner subdir-y += altera subdir-y += amazonarch/arm64/boot/dts/airoha/Makefile new file +2
-0@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtbarch/arm64/boot/dts/airoha/en7581-evb.dts new file +15
-0@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7581.dtsi" + +/ { + model = "Airoha EN7581 Evaluation Board"; + compatible = "airoha,en7581-evb", "airoha,en7581"; + + aliases { + serial0 = &uart1; + };
arch/arm64/boot/dts/airoha/en7581-evb.dts line 25
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +10
-0+ + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>;
Is your bootloader really not filling the size for the memory node?
Can you please verify?
If it doesn't, it's not a problem of course.
Quoted 14 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +2
-0+ }; +};arch/arm64/boot/dts/airoha/en7581.dtsi new file +6
-0@@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ {
arch/arm64/boot/dts/airoha/en7581.dtsi line 16
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + npu_binary@84000000 {
npu-binary@...
Quoted 17 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +17
-0+ no-map; + reg = <0x0 0x84000000 0x0 0xA00000>; + }; + + npu_flag@84B0000 { + no-map; + reg = <0x0 0x84B00000 0x0 0x100000>; + }; + + npu_pkt@85000000 { + no-map; + reg = <0x0 0x85000000 0x0 0x1A00000>; + }; + + npu_phyaddr@86B00000 { + no-map; + reg = <0x0 0x86B00000 0x0 0x100000>;
arch/arm64/boot/dts/airoha/en7581.dtsi line 43
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ }; + + npu_rxdesc@86D00000 { + no-map; + reg = <0x0 0x86D00000 0x0 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-0.2";
Not the first time I comment that (in general - not specifically to you): are you sure that your platform supports PSCI v0.2 and not a later version?
Please check your kernel log, you should see a message like
[ 0.000000] psci: PSCIv1.1 detected in firmware.
(with the right version)
...then use the right compatible string :-)
Quoted 5 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +5
-0+ method = "smc"; + }; + + cpus { + #address-cells = <1>;
arch/arm64/boot/dts/airoha/en7581.dtsi line 58
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + };
Your cluster contains only two cores, this means that the other two are in a parallel reality? :-P :-P
Jokes apart, this cpu-map looks wrong.
Check what the topology is supposed to be for real, clusterized or DynamIQ? In the first case, you get X clusters with Y CPUs each - in the second case, you get *one* single cluster with all CPUs inside.
Quoted 33 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +33
-0+ }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53";
arch/arm64/boot/dts/airoha/en7581.dtsi line 101
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ reg = <0x3>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified;
Do you know what is the l2 cache size, line size, sets? cache-size = < ... >
cache-line-size = < ... >
cache-sets = < ... >
arch/arm64/boot/dts/airoha/en7581.dtsi line 104
Quoted 3 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +3
-0+ }; + }; +
All iospace addressable nodes must go into a soc node, others go in the root node.
soc {
gic: interrupt-controller@9000000 {
....
}
uart0: serial@ ....};
Quoted 21 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +21
-0+ gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x09000000 0x0 0x20000>, + <0x0 0x09080000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x2000>, + <0x0 0x09500000 0x0 0x2000>, + <0x0 0x09600000 0x0 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
arch/arm64/boot/dts/airoha/en7581.dtsi line 135
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + status = "okay";
status is okay by default, you don't need that.
arch/arm64/boot/dts/airoha/en7581.dtsi line 137
Quoted 2 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +2
-0+ }; +};
Cheers,
Angelo
Re: [PATCH v2 2/4] arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board
Quoted 61 lines
Quoted 61 lines
From: Daniel Danzberger <[email protected]>
Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles.
Signed-off-by Daniel Danzberger <[email protected]>Signed-off-by Lorenzo Bianconi <[email protected]>--- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/airoha/Makefile | 2 + arch/arm64/boot/dts/airoha/en7581-evb.dts | 27 +++++ arch/arm64/boot/dts/airoha/en7581.dtsi | 137 ++++++++++++++++++++++ 4 files changed, 167 insertions(+)create mode 100644
arch/arm64/boot/dts/airoha/Makefilecreate mode 100644arch/arm64/boot/dts/airoha/en7581-evb.dtscreate mode 100644arch/arm64/boot/dts/airoha/en7581.dtsiarch/arm64/boot/dts/Makefile +1
-0@@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += actions +subdir-y += airoha subdir-y += allwinner subdir-y += altera subdir-y += amazonarch/arm64/boot/dts/airoha/Makefile new file +2
-0@@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtbarch/arm64/boot/dts/airoha/en7581-evb.dts new file +19
-0@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7581.dtsi" + +/ { + model = "Airoha EN7581 Evaluation Board"; + compatible = "airoha,en7581-evb", "airoha,en7581"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8";
Quoted 8 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts line 25
Quoted 6 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +6
-0+ linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>;Is your bootloader really not filling the size for the memory node?
is the size 0x200000000? Am I missing something?
Quoted 22 lines
Can you please verify?
If it doesn't, it's not a problem of course.Quoted 18 lines
arch/arm64/boot/dts/airoha/en7581-evb.dts new file +2
-0+ }; +};arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0@@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; +
Quoted 8 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 16
Quoted 6 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +6
-0+ reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + npu_binary@84000000 {npu-binary@...
ack, I will fix it.
Quoted 32 lines
Quoted 18 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +17
-0+ no-map; + reg = <0x0 0x84000000 0x0 0xA00000>; + }; + + npu_flag@84B0000 { + no-map; + reg = <0x0 0x84B00000 0x0 0x100000>; + }; + + npu_pkt@85000000 { + no-map; + reg = <0x0 0x85000000 0x0 0x1A00000>; + }; + + npu_phyaddr@86B00000 { + no-map; + reg = <0x0 0x86B00000 0x0 0x100000>;arch/arm64/boot/dts/airoha/en7581.dtsi line 43
Quoted 10 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ }; + + npu_rxdesc@86D00000 { + no-map; + reg = <0x0 0x86D00000 0x0 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-0.2";Not the first time I comment that (in general - not specifically to you): are you sure that your platform supports PSCI v0.2 and not a later version?
Quoted 7 lines
Please check your kernel log, you should see a message like
[ 0.000000] psci: PSCIv1.1 detected in firmware.(with the right version)
...then use the right compatible string :-)
ack, I will fix it.
Quoted 11 lines
Quoted 11 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +10
-0+ method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 {
Quoted 8 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 58
Quoted 5 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +5
-0+ cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + };Your cluster contains only two cores, this means that the other two are in a parallel reality? :-P :-P
I think this has been copied from vendor sdk. I will fix moving back 2 missing cpu from the 'parallel reality' :)
Quoted 6 lines
Jokes apart, this cpu-map looks wrong.
Check what the topology is supposed to be for real, clusterized or DynamIQ? In the first case, you get X clusters with Y CPUs each - in the second case, you get *one* single cluster with all CPUs inside.
I think it is just a linear architecture, but I will check with airoha folks.
Quoted 41 lines
Quoted 41 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +40
-0+ }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 {
Quoted 8 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 101
Quoted 3 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +3
-0+ compatible = "cache"; + cache-level = <2>; + cache-unified;Do you know what is the l2 cache size, line size, sets? cache-size = < ... >
cache-line-size = < ... >
cache-sets = < ... >
not sure about them, I will sync with airoha folks.
Quoted 6 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 104
Quoted 4 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +3
-0+ }; + }; +All iospace addressable nodes must go into a soc node, others go in the root node.
ack, I will fix it.
Quoted 35 lines
soc { gic: interrupt-controller@9000000 { .... } uart0: serial@ ....};
Quoted 25 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +25
-0+ gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x09000000 0x0 0x20000>, + <0x0 0x09080000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x2000>, + <0x0 0x09500000 0x0 0x2000>, + <0x0 0x09600000 0x0 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550";
Quoted 8 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 135
Quoted 6 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +6
-0+ reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + status = "okay";status is okay by default, you don't need that.
ack, I will fix it.
Regards,
Lorenzo
Quoted 6 lines
arch/arm64/boot/dts/airoha/en7581.dtsi line 137
Quoted 3 lines
arch/arm64/boot/dts/airoha/en7581.dtsi new file +2
-0+ }; +};Cheers,
Angelo
PATCH v2 3/4 arm64: add Airoha EN7581 platform
In reply to Lorenzo BianconiFrom: Daniel Danzberger <[email protected]>
Introduce the Kconfig entry for the Airoha EN7581 multicore architecture available in the Airoha EN7581 evaluation board.
--- arch/arm64/Kconfig.platforms | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm64/Kconfig.platforms +13 -0
@@ -8,6 +8,19 @@ config ARCH_ACTIONS help This enables support for the Actions Semiconductor S900 SoC family. +config ARCH_AIROHA + bool "Airoha SoC Support" + select ARM_AMBA + select ARM_GIC + select ARM_GIC_V3 + select ARM_PSCI + select HAVE_ARM_ARCH_TIMER + select COMMON_CLK + help + This enables support for Airoha EN7581 multicore architecture + available on the following SoCs: + - Airoha EN7581 Evaluation Board + config ARCH_SUNXI bool "Allwinner sunxi 64-bit SoC Family" select ARCH_HAS_RESET_CONTROLLER
Signature · 1 line
2.43.2
PATCH v2 4/4 arm64: defconfig: enable Airoha platform
In reply to Lorenzo BianconiFrom: Daniel Danzberger <[email protected]>
Enables the ARCH_AIROHA config by default.
--- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm64/configs/defconfig +1 -0
@@ -50,6 +50,7 @@ CONFIG_ARCH_LG1K=y CONFIG_ARCH_HISI=y CONFIG_ARCH_KEEMBAY=y CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_AIROHA=y CONFIG_ARCH_MESON=y CONFIG_ARCH_MVEBU=y CONFIG_ARCH_NXP=y
Signature · 1 line
2.43.2
Re: [PATCH v2 4/4] arm64: defconfig: enable Airoha platform
Quoted 15 lines · Lorenzo Bianconi
From: Daniel Danzberger <[email protected]>
Enables the
ARCH_AIROHAconfig by default.Signed-off-by Daniel Danzberger <[email protected]>Signed-off-by Lorenzo Bianconi <[email protected]>--- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)arch/arm64/configs/defconfig +0
-0
arch/arm64/configs/defconfig CONFIG_ARCH_LG1K=y · line 53
Quoted 4 lines
arch/arm64/configs/defconfig +1
-0@@ -50,6 +50,7 @@ CONFIG_ARCH_LG1K=y CONFIG_ARCH_HISI=y CONFIG_ARCH_KEEMBAY=y CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_AIROHA=y
Are you sure it is placed in correct order? Looks a bit random, not according to Kconfig ordering (savedefconfig).
Best regards,
Krzysztof