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Introduce EN7581 ethernet support

PATCH Superseded Lorenzo Bianconi 4 participants 10 messages Jun 29, 2024 – Jul 3, 2024

Subsystems (5)

v4 of 8 Superseded Latest is v8 →

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Lorenzo Bianconi

author maintainer
#0 lore raw

v4 cover Introduce EN7581 ethernet support

Add airoha_eth driver in order to introduce ethernet support for Airoha EN7581 SoC available on EN7581 development board. EN7581 mac controller is mainly composed by Frame Engine (FE) and QoS-DMA (QDMA) modules. FE is used for traffic offloading (just basic functionalities are supported now) while QDMA is used for DMA operation and QOS functionalities between mac layer and the dsa switch (hw QoS is not available yet and it will be added in the future). Currently only hw lan features are available, hw wan will be added with subsequent patches.

Changes since v3:
- rework architecture to allow future gdm{1,4} support
- read REG_INT_ENABLE() register in airoha_qdma_set_irqmask() to guarantee airoha_qdma_wr() complete in the spinlock critical section - thx Arnd for the clarification
- remove unnecessary wmb()
- remove debugfs
- move register definitions in .c and remove .h
- fix warnings
- enable NAPI thread by default
Changes since v2:
- rename airoha,en7581.yaml in airoha,en7581-eth.yaml
- remove reset dependency in airoha,en7581-eth.yaml
- remove airoha_dev_change_mtu() callback
Changes since v1:
- drop patch 2/3
- remove queue lock for rx queues
- add bql support
- add ethtool stats support
- fix possible infinite loop in airoha_qdma_rx_process routine
- always destroy page_pool in case of error during initialization
- cosmetics

Lorenzo Bianconi (2):
dt-bindings: net: airoha: Add EN7581 ethernet controller
net: airoha: Introduce ethernet support for EN7581 SoC

 .../bindings/net/airoha,en7581-eth.yaml       |  171 ++
 MAINTAINERS                                   |    9 +
 drivers/net/ethernet/mediatek/Kconfig         |   11 +-
 drivers/net/ethernet/mediatek/Makefile        |    1 +
 drivers/net/ethernet/mediatek/airoha_eth.c    | 2709 +++++++++++++++++
 5 files changed, 2900 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
 create mode 100644 drivers/net/ethernet/mediatek/airoha_eth.c
Signature · 1 line
2.45.2
author maintainer
#1 lore raw

PATCH v4 1/2 dt-bindings: net: airoha: Add EN7581 ethernet controller

Introduce device-tree binding documentation for Airoha EN7581 ethernet mac controller.

---
 .../bindings/net/airoha,en7581-eth.yaml       | 171 ++++++++++++++++++
 1 file changed, 171 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +171 -0
new file mode 100644
index 000000000000..e2c0da02ccf2
@@ -0,0 +1,171 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 Frame Engine Ethernet controller
+
+allOf:
+  - $ref: ethernet-controller.yaml#
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+
+description:
+  The frame engine ethernet controller can be found on Airoha SoCs.
+  These SoCs have dual GMAC ports.
+
+properties:
+  compatible:
+    enum:
+      - airoha,en7581-eth
+
+  reg:
+    items:
+      - description: Frame engine base address
+      - description: QDMA0 base address
+      - description: QDMA1 base address
+
+  reg-names:
+    items:
+      - const: fe
+      - const: qdma0
+      - const: qdma1
+
+  interrupts:
+    items:
+      - description: QDMA lan irq0
+      - description: QDMA lan irq1
+      - description: QDMA lan irq2
+      - description: QDMA lan irq3
+      - description: QDMA wan irq0
+      - description: QDMA wan irq1
+      - description: QDMA wan irq2
+      - description: QDMA wan irq3
+      - description: FE error irq
+      - description: PDMA irq
+
+  resets:
+    maxItems: 8
+
+  reset-names:
+    items:
+      - const: fe
+      - const: pdma
+      - const: qdma
+      - const: xsi-mac
+      - const: hsi0-mac
+      - const: hsi1-mac
+      - const: hsi-mac
+      - const: xfp-mac
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^mac@[1-4]$":
+    type: object
+    unevaluatedProperties: false
+    allOf:
+      - $ref: ethernet-controller.yaml#
+    description:
+      Ethernet MAC node
+    properties:
+      compatible:
+        const: airoha,eth-mac
+
+      reg:
+        maxItems: 1
+
+    required:
+      - reg
+      - compatible
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - resets
+  - reset-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/en7523-clk.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      eth0: ethernet@1fb50000 {
+        compatible = "airoha,en7581-eth";
+        reg = <0 0x1fb50000 0 0x2600>,
+              <0 0x1fb54000 0 0x2000>,
+              <0 0x1fb56000 0 0x2000>;
+        reg-names = "fe", "qdma0", "qdma1";
+
+        resets = <&scuclk 44>,
+                 <&scuclk 30>,
+                 <&scuclk 31>,
+                 <&scuclk 6>,
+                 <&scuclk 15>,
+                 <&scuclk 16>,
+                 <&scuclk 17>,
+                 <&scuclk 26>;
+        reset-names = "fe", "pdma", "qdma", "xsi-mac",
+                      "hsi0-mac", "hsi1-mac", "hsi-mac",
+                      "xfp-mac";
+
+        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        mac1: mac@1 {
+          compatible = "airoha,eth-mac";
+          reg = <1>;
+          phy-mode = "2500base-x";
+          phy-handle = <&phy0>;
+        };
+
+        mac2: mac@2 {
+          compatible = "airoha,eth-mac";
+          reg = <2>;
+          phy-mode = "2500base-x";
+          phy-handle = <&phy1>;
+        };
+      };
+
+      mdio: mdio-bus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        phy0: ethernet-phy@0 {
+            compatible = "ethernet-phy-id67c9.de0a";
+            reg = <0>;
+            phy-mode = "2500base-x";
+        };
+
+        phy1: ethernet-phy@1 {
+            compatible = "ethernet-phy-id67c9.de0a";
+            reg = <1>;
+            phy-mode = "2500base-x";
+        };
+      };
+    };
Signature · 1 line
2.45.2
maintainer
#2 lore raw

Re: [PATCH v4 1/2] dt-bindings: net: airoha: Add EN7581 ethernet controller

Quoted 75 lines · Lorenzo Bianconi

Introduce device-tree binding documentation for Airoha EN7581 ethernet mac controller.

---
 .../bindings/net/airoha,en7581-eth.yaml       | 171 ++++++++++++++++++
 1 file changed, 171 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +60 -0
new file mode 100644
index 000000000000..e2c0da02ccf2
@@ -0,0 +1,171 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 Frame Engine Ethernet controller
+
+allOf:
+  - $ref: ethernet-controller.yaml#
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+
+description:
+  The frame engine ethernet controller can be found on Airoha SoCs.
+  These SoCs have dual GMAC ports.
+
+properties:
+  compatible:
+    enum:
+      - airoha,en7581-eth
+
+  reg:
+    items:
+      - description: Frame engine base address
+      - description: QDMA0 base address
+      - description: QDMA1 base address
+
+  reg-names:
+    items:
+      - const: fe
+      - const: qdma0
+      - const: qdma1
+
+  interrupts:
+    items:
+      - description: QDMA lan irq0
+      - description: QDMA lan irq1
+      - description: QDMA lan irq2
+      - description: QDMA lan irq3
+      - description: QDMA wan irq0
+      - description: QDMA wan irq1
+      - description: QDMA wan irq2
+      - description: QDMA wan irq3
+      - description: FE error irq
+      - description: PDMA irq
+
+  resets:
+    maxItems: 8
+
+  reset-names:
+    items:
+      - const: fe
+      - const: pdma
+      - const: qdma
+      - const: xsi-mac
+      - const: hsi0-mac
+      - const: hsi1-mac
+      - const: hsi-mac

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 70

Quoted 10 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +10 -0
+      - const: xfp-mac
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^mac@[1-4]$":

ethernet@

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 73

Quoted 3 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +3 -0
+    type: object
+    unevaluatedProperties: false
+    allOf:

Can drop 'allOf'

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 74

Quoted 1 line
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +1 -0
+      - $ref: ethernet-controller.yaml#

Which node represents an ethernet controller? This one or the parent? Most likely it is not both.

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 82

Quoted 8 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +8 -0
+    description:
+      Ethernet MAC node
+    properties:
+      compatible:
+        const: airoha,eth-mac
+
+      reg:
+        maxItems: 1

Based on the unit-address, you need instead:

minimum: 1
maximum: 4

But what does 1-4 represent? There are no MMIO registers associated with the MACs? Please describe.

Quoted 63 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +63 -0
+
+    required:
+      - reg
+      - compatible
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - resets
+  - reset-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/en7523-clk.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      eth0: ethernet@1fb50000 {
+        compatible = "airoha,en7581-eth";
+        reg = <0 0x1fb50000 0 0x2600>,
+              <0 0x1fb54000 0 0x2000>,
+              <0 0x1fb56000 0 0x2000>;
+        reg-names = "fe", "qdma0", "qdma1";
+
+        resets = <&scuclk 44>,
+                 <&scuclk 30>,
+                 <&scuclk 31>,
+                 <&scuclk 6>,
+                 <&scuclk 15>,
+                 <&scuclk 16>,
+                 <&scuclk 17>,
+                 <&scuclk 26>;
+        reset-names = "fe", "pdma", "qdma", "xsi-mac",
+                      "hsi0-mac", "hsi1-mac", "hsi-mac",
+                      "xfp-mac";
+
+        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        mac1: mac@1 {
+          compatible = "airoha,eth-mac";
+          reg = <1>;
+          phy-mode = "2500base-x";
+          phy-handle = <&phy0>;
+        };

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 155

Quoted 10 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +10 -0
+
+        mac2: mac@2 {
+          compatible = "airoha,eth-mac";
+          reg = <2>;
+          phy-mode = "2500base-x";
+          phy-handle = <&phy1>;
+        };
+      };
+
+      mdio: mdio-bus {

mdio {

But really, drop this if it is not part of this device (binding). What is the control interface for this MDIO bus? If it is part of this device, then the mdio node needs to be within the device's node.

Quoted 19 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +16 -0
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        phy0: ethernet-phy@0 {
+            compatible = "ethernet-phy-id67c9.de0a";
+            reg = <0>;
+            phy-mode = "2500base-x";
+        };
+
+        phy1: ethernet-phy@1 {
+            compatible = "ethernet-phy-id67c9.de0a";
+            reg = <1>;
+            phy-mode = "2500base-x";
+        };
+      };
+    };
Signature · 1 line
2.45.2
author maintainer
#3 lore raw

Re: [PATCH v4 1/2] dt-bindings: net: airoha: Add EN7581 ethernet controller

Quoted 80 lines · Lorenzo Bianconi
Quoted 79 lines

Introduce device-tree binding documentation for Airoha EN7581 ethernet mac controller.

---
 .../bindings/net/airoha,en7581-eth.yaml       | 171 ++++++++++++++++++
 1 file changed, 171 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +64 -0
new file mode 100644
index 000000000000..e2c0da02ccf2
@@ -0,0 +1,171 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 Frame Engine Ethernet controller
+
+allOf:
+  - $ref: ethernet-controller.yaml#
+
+maintainers:
+  - Lorenzo Bianconi <[email protected]>
+
+description:
+  The frame engine ethernet controller can be found on Airoha SoCs.
+  These SoCs have dual GMAC ports.
+
+properties:
+  compatible:
+    enum:
+      - airoha,en7581-eth
+
+  reg:
+    items:
+      - description: Frame engine base address
+      - description: QDMA0 base address
+      - description: QDMA1 base address
+
+  reg-names:
+    items:
+      - const: fe
+      - const: qdma0
+      - const: qdma1
+
+  interrupts:
+    items:
+      - description: QDMA lan irq0
+      - description: QDMA lan irq1
+      - description: QDMA lan irq2
+      - description: QDMA lan irq3
+      - description: QDMA wan irq0
+      - description: QDMA wan irq1
+      - description: QDMA wan irq2
+      - description: QDMA wan irq3
+      - description: FE error irq
+      - description: PDMA irq
+
+  resets:
+    maxItems: 8
+
+  reset-names:
+    items:
+      - const: fe
+      - const: pdma
+      - const: qdma
+      - const: xsi-mac
+      - const: hsi0-mac
+      - const: hsi1-mac
+      - const: hsi-mac
+      - const: xfp-mac
+
+  "#address-cells":
+    const: 1
Quoted 8 lines

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 70

Quoted 6 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +6 -0
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^mac@[1-4]$":

ethernet@

Should it be like mtk_eth_soc binding?
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/net/mediatek%2Cnet.yaml#L371

Quoted 6 lines

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 73

Quoted 4 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +3 -0
+    type: object
+    unevaluatedProperties: false
+    allOf:

Can drop 'allOf'

ack, I will fix it in v5

Quoted 5 lines

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 74

Quoted 2 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +1 -0
+      - $ref: ethernet-controller.yaml#

Which node represents an ethernet controller? This one or the parent? Most likely it is not both.

This node reprensts the GMAC port associated to the parent enternet controller.

Quoted 10 lines

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 82

Quoted 9 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +8 -0
+    description:
+      Ethernet MAC node
+    properties:
+      compatible:
+        const: airoha,eth-mac
+
+      reg:
+        maxItems: 1
Quoted 4 lines

Based on the unit-address, you need instead:

minimum: 1
maximum: 4

ack, I will fix it in v5

Quoted 3 lines

But what does 1-4 represent? There are no MMIO registers associated with the MACs? Please describe.

This is the GMAC port ID.

Quoted 77 lines
Quoted 64 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +63 -0
+
+    required:
+      - reg
+      - compatible
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - resets
+  - reset-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/en7523-clk.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      eth0: ethernet@1fb50000 {
+        compatible = "airoha,en7581-eth";
+        reg = <0 0x1fb50000 0 0x2600>,
+              <0 0x1fb54000 0 0x2000>,
+              <0 0x1fb56000 0 0x2000>;
+        reg-names = "fe", "qdma0", "qdma1";
+
+        resets = <&scuclk 44>,
+                 <&scuclk 30>,
+                 <&scuclk 31>,
+                 <&scuclk 6>,
+                 <&scuclk 15>,
+                 <&scuclk 16>,
+                 <&scuclk 17>,
+                 <&scuclk 26>;
+        reset-names = "fe", "pdma", "qdma", "xsi-mac",
+                      "hsi0-mac", "hsi1-mac", "hsi-mac",
+                      "xfp-mac";
+
+        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        mac1: mac@1 {
+          compatible = "airoha,eth-mac";
+          reg = <1>;
+          phy-mode = "2500base-x";
+          phy-handle = <&phy0>;
+        };

Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml line 155

Quoted 10 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +10 -0
+
+        mac2: mac@2 {
+          compatible = "airoha,eth-mac";
+          reg = <2>;
+          phy-mode = "2500base-x";
+          phy-handle = <&phy1>;
+        };
+      };
+
+      mdio: mdio-bus {

mdio {

Quoted 3 lines

But really, drop this if it is not part of this device (binding). What is the control interface for this MDIO bus? If it is part of this device, then the mdio node needs to be within the device's node.

ack, I will drop it in v5.

Regards,
Lorenzo

Quoted 20 lines
Quoted 20 lines
Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml new file +16 -0
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        phy0: ethernet-phy@0 {
+            compatible = "ethernet-phy-id67c9.de0a";
+            reg = <0>;
+            phy-mode = "2500base-x";
+        };
+
+        phy1: ethernet-phy@1 {
+            compatible = "ethernet-phy-id67c9.de0a";
+            reg = <1>;
+            phy-mode = "2500base-x";
+        };
+      };
+    };
Signature · 1 line
2.45.2
author maintainer
#4 lore raw

PATCH v4 2/2 net: airoha: Introduce ethernet support for EN7581 SoC

In reply to Lorenzo Bianconi

Add airoha_eth driver in order to introduce ethernet support for Airoha EN7581 SoC available on EN7581 development board (en7581-evb). en7581-evb networking architecture is composed by airoha_eth as mac controller (cpu port) and a mt7530 dsa based switch.
EN7581 mac controller is mainly composed by Frame Engine (FE) and QoS-DMA (QDMA) modules. FE is used for traffic offloading (just basic functionalities are supported now) while QDMA is used for DMA operation and QOS functionalities between mac layer and the dsa switch (hw QoS is not available yet and it will be added in the future). Currently only hw lan features are available, hw wan will be added with subsequent patches.

---
 MAINTAINERS                                |    9 +
 drivers/net/ethernet/mediatek/Kconfig      |   11 +-
 drivers/net/ethernet/mediatek/Makefile     |    1 +
 drivers/net/ethernet/mediatek/airoha_eth.c | 2709 ++++++++++++++++++++
 4 files changed, 2729 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/ethernet/mediatek/airoha_eth.c
MAINTAINERS +9 -0
index 22328600cfd0..3423566d9587 100644
@@ -682,6 +682,15 @@ S:	Supported
 F:	fs/aio.c
 F:	include/linux/*aio*.h
 
+AIROHA ETHERNET DRIVER
+M:	Lorenzo Bianconi <[email protected]>
+L:	[email protected] (moderated for non-subscribers)
+L:	[email protected] (moderated for non-subscribers)
+L:	[email protected]
+S:	Maintained
+F:	Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
+F:	drivers/net/ethernet/mediatek/airoha_eth.c
+
 AIROHA SPI SNFI DRIVER
 M:	Lorenzo Bianconi <[email protected]>
 M:	Ray Liu <[email protected]>
drivers/net/ethernet/mediatek/Kconfig +10 -1
index da0db417ab69..e16d0ea5d418 100644
@@ -1,12 +1,21 @@
 # SPDX-License-Identifier: GPL-2.0-only
 config NET_VENDOR_MEDIATEK
 	bool "MediaTek devices"
-	depends on ARCH_MEDIATEK || SOC_MT7621 || SOC_MT7620 || COMPILE_TEST
+	depends on ARCH_MEDIATEK || ARCH_AIROHA || SOC_MT7621 || SOC_MT7620 || COMPILE_TEST
 	help
 	  If you have a Mediatek SoC with ethernet, say Y.
 
 if NET_VENDOR_MEDIATEK
 
+config NET_AIROHA
+	tristate "Airoha SoC Gigabit Ethernet support"
+	depends on NET_DSA || !NET_DSA
+	select PAGE_POOL
+	select PAGE_POOL_STATS
+	help
+	  This driver supports the gigabit ethernet MACs in the
+	  Airoha SoC family.
+
 config NET_MEDIATEK_SOC_WED
 	depends on ARCH_MEDIATEK || COMPILE_TEST
 	def_bool NET_MEDIATEK_SOC != n
drivers/net/ethernet/mediatek/Makefile +1 -0
index 03e008fbc859..ddbb7f4a516c 100644
@@ -11,3 +11,4 @@ mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
 endif
 obj-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_ops.o
 obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o
+obj-$(CONFIG_NET_AIROHA) += airoha_eth.o
drivers/net/ethernet/mediatek/airoha_eth.c new file +2709 -0

2,709 lines not on this page · raw message

Signature · 1 line
2.45.2
reviewer
#5 lore raw

Re: [PATCH v4 2/2] net: airoha: Introduce ethernet support for EN7581 SoC

Quoted 12 lines · Lorenzo Bianconi

Add airoha_eth driver in order to introduce ethernet support for Airoha EN7581 SoC available on EN7581 development board (en7581-evb). en7581-evb networking architecture is composed by airoha_eth as mac controller (cpu port) and a mt7530 dsa based switch.
EN7581 mac controller is mainly composed by Frame Engine (FE) and QoS-DMA (QDMA) modules. FE is used for traffic offloading (just basic functionalities are supported now) while QDMA is used for DMA operation and QOS functionalities between mac layer and the dsa switch (hw QoS is not available yet and it will be added in the future). Currently only hw lan features are available, hw wan will be added with subsequent patches.

Quoted 2 lines

Hi Lorenzo,

Some minor feedback from my side.

Quoted 7 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +7 -0
+static void airoha_qdma_set_irqmask(struct airoha_eth *eth, int index,
+				    u32 clear, u32 set)
+{
+	unsigned long flags;
+
+	if (WARN_ON_ONCE(index >= ARRAY_SIZE(eth->irqmask)))
+		return;

drivers/net/ethernet/mediatek/airoha_eth.c line 848

Quoted 10 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +10 -0
+
+	spin_lock_irqsave(&eth->irq_lock, flags);
+
+	eth->irqmask[index] &= ~clear;
+	eth->irqmask[index] |= set;
+	airoha_qdma_wr(eth, REG_INT_ENABLE(index), eth->irqmask[index]);
+	/* Read irq_enable register in order to guarantee the update above
+	 * completes in the spinlock critical section.
+	 */
+	airoha_rr(eth, REG_INT_ENABLE(index));

airoha_rr() expects an __iomem pointer as it's first argument, but the type of eth is struct airoha_eth *eth.

Should this be using airoha_qdma_rr() instead?

Flagged by Sparse.

Quoted 3 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +3 -0
+
+	spin_unlock_irqrestore(&eth->irq_lock, flags);
+}

...

Quoted 6 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +6 -0
+static void airoha_ethtool_get_strings(struct net_device *dev, u32 sset,
+				       u8 *data)
+{
+	int i;
+
+	if (sset != ETH_SS_STATS)

drivers/net/ethernet/mediatek/airoha_eth.c line 2301

Quoted 10 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +10 -0
+		return;
+
+	for (i = 0; i < ARRAY_SIZE(airoha_ethtool_stats_name); i++) {
+		memcpy(data + i * ETH_GSTRING_LEN,
+		       airoha_ethtool_stats_name[i], ETH_GSTRING_LEN);
+	}
+
+	data += ETH_GSTRING_LEN * ARRAY_SIZE(airoha_ethtool_stats_name);
+	page_pool_ethtool_stats_get_strings(data);
+}

W=1 allmodconfig builds on x86_64 with gcc-13 complain about the use of memcpy above because the source is (often?) less than ETH_GSTRING_LEN bytes long.

I think the preferred solution is to use ethtool_puts(), something like this (compile tested only!):

@@ -2291,12 +2291,9 @@ static void airoha_ethtool_get_strings(struct net_device *dev, u32 sset,
if (sset != ETH_SS_STATS)
return;

- for (i = 0; i < ARRAY_SIZE(airoha_ethtool_stats_name); i++) {
- memcpy(data + i * ETH_GSTRING_LEN,
- airoha_ethtool_stats_name[i], ETH_GSTRING_LEN);
- }
+ for (i = 0; i < ARRAY_SIZE(airoha_ethtool_stats_name); i++)
+ ethtool_puts(&data, airoha_ethtool_stats_name[i]);

- data += ETH_GSTRING_LEN * ARRAY_SIZE(airoha_ethtool_stats_name);
page_pool_ethtool_stats_get_strings(data);
}

...

drivers/net/ethernet/mediatek/airoha_eth.c line 2502

Quoted 5 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +5 -0
+static int airoha_alloc_gdm_port(struct airoha_eth *eth, struct device_node *np)
+{
+	const __be32 *id_ptr = of_get_property(np, "reg", NULL);
+	struct net_device *dev;
+	struct airoha_gdm_port *port;

nit: reverse xmas tree

Quoted 2 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +2 -0
+	int err, index;
+	u32 id;

...

Signature · 1 line
pw-bot: changes-requested
author maintainer
#6 lore raw

Re: [PATCH v4 2/2] net: airoha: Introduce ethernet support for EN7581 SoC

Quoted 13 lines · Lorenzo Bianconi
Quoted 12 lines

Add airoha_eth driver in order to introduce ethernet support for Airoha EN7581 SoC available on EN7581 development board (en7581-evb). en7581-evb networking architecture is composed by airoha_eth as mac controller (cpu port) and a mt7530 dsa based switch.
EN7581 mac controller is mainly composed by Frame Engine (FE) and QoS-DMA (QDMA) modules. FE is used for traffic offloading (just basic functionalities are supported now) while QDMA is used for DMA operation and QOS functionalities between mac layer and the dsa switch (hw QoS is not available yet and it will be added in the future). Currently only hw lan features are available, hw wan will be added with subsequent patches.

Quoted 6 lines
Quoted 2 lines

Hi Lorenzo,

Some minor feedback from my side.

Hi Simon,

Quoted 22 lines
Quoted 8 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +7 -0
+static void airoha_qdma_set_irqmask(struct airoha_eth *eth, int index,
+				    u32 clear, u32 set)
+{
+	unsigned long flags;
+
+	if (WARN_ON_ONCE(index >= ARRAY_SIZE(eth->irqmask)))
+		return;

drivers/net/ethernet/mediatek/airoha_eth.c line 848

Quoted 10 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +10 -0
+
+	spin_lock_irqsave(&eth->irq_lock, flags);
+
+	eth->irqmask[index] &= ~clear;
+	eth->irqmask[index] |= set;
+	airoha_qdma_wr(eth, REG_INT_ENABLE(index), eth->irqmask[index]);
+	/* Read irq_enable register in order to guarantee the update above
+	 * completes in the spinlock critical section.
+	 */
+	airoha_rr(eth, REG_INT_ENABLE(index));

airoha_rr() expects an __iomem pointer as it's first argument, but the type of eth is struct airoha_eth *eth.

Quoted 1 line

Should this be using airoha_qdma_rr() instead?

ack, right. Thx for pointing this out. I will fix it in v5.

Quoted 38 lines

Flagged by Sparse.

Quoted 3 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +3 -0
+
+	spin_unlock_irqrestore(&eth->irq_lock, flags);
+}

...

Quoted 6 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +6 -0
+static void airoha_ethtool_get_strings(struct net_device *dev, u32 sset,
+				       u8 *data)
+{
+	int i;
+
+	if (sset != ETH_SS_STATS)

drivers/net/ethernet/mediatek/airoha_eth.c line 2301

Quoted 10 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +10 -0
+		return;
+
+	for (i = 0; i < ARRAY_SIZE(airoha_ethtool_stats_name); i++) {
+		memcpy(data + i * ETH_GSTRING_LEN,
+		       airoha_ethtool_stats_name[i], ETH_GSTRING_LEN);
+	}
+
+	data += ETH_GSTRING_LEN * ARRAY_SIZE(airoha_ethtool_stats_name);
+	page_pool_ethtool_stats_get_strings(data);
+}

W=1 allmodconfig builds on x86_64 with gcc-13 complain about the use of memcpy above because the source is (often?) less than ETH_GSTRING_LEN bytes long.

I think the preferred solution is to use ethtool_puts(), something like this (compile tested only!):

(quoted diff) +0 -1
@@ -2291,12 +2291,9 @@ static void airoha_ethtool_get_strings(struct net_device *dev, u32 sset,
 	if (sset != ETH_SS_STATS)
 		return;
 
-	for (i = 0; i < ARRAY_SIZE(airoha_ethtool_stats_name); i++) {

Review static void airoha_ethtool_get_strings(struct net_device *dev, u32 sset, · line 2299

Quoted 10 lines
(quoted diff) +2 -4
-		memcpy(data + i * ETH_GSTRING_LEN,
-		       airoha_ethtool_stats_name[i], ETH_GSTRING_LEN);
-	}
+	for (i = 0; i < ARRAY_SIZE(airoha_ethtool_stats_name); i++)
+		ethtool_puts(&data, airoha_ethtool_stats_name[i]);
 
-	data += ETH_GSTRING_LEN * ARRAY_SIZE(airoha_ethtool_stats_name);
 	page_pool_ethtool_stats_get_strings(data);
 }
 

ack, I will fix it in v5.

Quoted 10 lines

...

drivers/net/ethernet/mediatek/airoha_eth.c line 2502

Quoted 5 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +5 -0
+static int airoha_alloc_gdm_port(struct airoha_eth *eth, struct device_node *np)
+{
+	const __be32 *id_ptr = of_get_property(np, "reg", NULL);
+	struct net_device *dev;
+	struct airoha_gdm_port *port;

nit: reverse xmas tree

ack, I will fix it in v5.

Regards,
Lorenzo

Quoted 8 lines
Quoted 3 lines
drivers/net/ethernet/mediatek/airoha_eth.c new file +2 -0
+	int err, index;
+	u32 id;

...

Signature · 1 line
pw-bot: changes-requested
reviewer
#7 lore raw

Re: [PATCH v4 2/2] net: airoha: Introduce ethernet support for EN7581 SoC

In reply to Lorenzo Bianconi

On Sat, Jun 29, 2024 at 05:01:38PM +0200, Lorenzo Bianconi wrote:

...

Quoted 1 line
drivers/net/ethernet/mediatek/airoha_eth.c +0 -0

...

drivers/net/ethernet/mediatek/airoha_eth.c line 462

Quoted 9 lines
drivers/net/ethernet/mediatek/airoha_eth.c +9 -0
+#define INT_IDX4_MASK						\
+	(TX8_COHERENT_INT_MASK | TX9_COHERENT_INT_MASK |	\
+	 TX10_COHERENT_INT_MASK | TX11_COHERENT_INT_MASK |	\
+	 TX12_COHERENT_INT_MASK | TX13_COHERENT_INT_MASK |	\
+	 TX14_COHERENT_INT_MASK | TX15_COHERENT_INT_MASK |	\
+	 TX16_COHERENT_INT_MASK | TX17_COHERENT_INT_MASK |	\
+	 TX18_COHERENT_INT_MASK | TX19_COHERENT_INT_MASK |	\
+	 TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK |	\
+	 TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK |	\

Hi Lorenzo,

One more thing that I forgot to note yesterday:
the two lines above appear to be duplicates of each other.

Flagged by Coccinelle.

Quoted 5 lines
drivers/net/ethernet/mediatek/airoha_eth.c +5 -0
+	 TX22_COHERENT_INT_MASK | TX23_COHERENT_INT_MASK |	\
+	 TX24_COHERENT_INT_MASK | TX25_COHERENT_INT_MASK |	\
+	 TX26_COHERENT_INT_MASK | TX27_COHERENT_INT_MASK |	\
+	 TX28_COHERENT_INT_MASK | TX29_COHERENT_INT_MASK |	\
+	 TX30_COHERENT_INT_MASK | TX31_COHERENT_INT_MASK)

...

author maintainer
#8 lore raw

Re: [PATCH v4 2/2] net: airoha: Introduce ethernet support for EN7581 SoC

Quoted 20 lines · Lorenzo Bianconi

...

Quoted 1 line
drivers/net/ethernet/mediatek/airoha_eth.c +0 -0

...

drivers/net/ethernet/mediatek/airoha_eth.c line 462

Quoted 9 lines
drivers/net/ethernet/mediatek/airoha_eth.c +9 -0
+#define INT_IDX4_MASK						\
+	(TX8_COHERENT_INT_MASK | TX9_COHERENT_INT_MASK |	\
+	 TX10_COHERENT_INT_MASK | TX11_COHERENT_INT_MASK |	\
+	 TX12_COHERENT_INT_MASK | TX13_COHERENT_INT_MASK |	\
+	 TX14_COHERENT_INT_MASK | TX15_COHERENT_INT_MASK |	\
+	 TX16_COHERENT_INT_MASK | TX17_COHERENT_INT_MASK |	\
+	 TX18_COHERENT_INT_MASK | TX19_COHERENT_INT_MASK |	\
+	 TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK |	\
+	 TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK |	\

Hi Lorenzo,

Quoted 2 lines

One more thing that I forgot to note yesterday:
the two lines above appear to be duplicates of each other.

ack, thx. I will fix it in v5.

Regards,
Lorenzo

Quoted 10 lines

Flagged by Coccinelle.

Quoted 5 lines
drivers/net/ethernet/mediatek/airoha_eth.c +5 -0
+	 TX22_COHERENT_INT_MASK | TX23_COHERENT_INT_MASK |	\
+	 TX24_COHERENT_INT_MASK | TX25_COHERENT_INT_MASK |	\
+	 TX26_COHERENT_INT_MASK | TX27_COHERENT_INT_MASK |	\
+	 TX28_COHERENT_INT_MASK | TX29_COHERENT_INT_MASK |	\
+	 TX30_COHERENT_INT_MASK | TX31_COHERENT_INT_MASK)

...

#9 lore raw

Re: [PATCH v4 2/2] net: airoha: Introduce ethernet support for EN7581 SoC

In reply to Lorenzo Bianconi
kernel test robot noticed the following build warnings:

Hi Lorenzo,

kernel test robot noticed the following build warnings:

[auto build test WARNING on net/main]
[also build test WARNING on net-next/main linus/master v6.10-rc6] [cannot apply to horms-ipvs/master next-20240703]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Lorenzo-Bianconi/dt-bindings-net-airoha-Add-EN7581-ethernet-controller/20240630-185836
base:   net/main
patch link:    https://lore.kernel.org/r/56f57f37b80796e9706555503e5b4cf194f69479.1719672695.git.lorenzo%40kernel.org
patch subject: [PATCH v4 2/2] net: airoha: Introduce ethernet support for EN7581 SoC
config: arm-randconfig-r123-20240703 (https://download.01.org/0day-ci/archive/20240703/[email protected]/config)
compiler: arm-linux-gnueabi-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240703/[email protected]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

sparse warnings: (new ones prefixed by >>)

>> drivers/net/ethernet/mediatek/airoha_eth.c:848:19: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void [noderef] __iomem *base @@     got struct airoha_eth *eth @@

drivers/net/ethernet/mediatek/airoha_eth.c:848:19: sparse: expected void [noderef] __iomem *base
drivers/net/ethernet/mediatek/airoha_eth.c:848:19: sparse: got struct airoha_eth *eth
drivers/net/ethernet/mediatek/airoha_eth.c: note: in included file (through include/linux/mmzone.h, include/linux/gfp.h, include/linux/xarray.h, ...):
include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false

vim +848 drivers/net/ethernet/mediatek/airoha_eth.c

809
810 #define airoha_fe_rr(eth, offset) \
811 airoha_rr((eth)->fe_regs, (offset))
812 #define airoha_fe_wr(eth, offset, val) \
813 airoha_wr((eth)->fe_regs, (offset), (val))
814 #define airoha_fe_rmw(eth, offset, mask, val) \
815 airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
816 #define airoha_fe_set(eth, offset, val) \
817 airoha_rmw((eth)->fe_regs, (offset), 0, (val))
818 #define airoha_fe_clear(eth, offset, val) \
819 airoha_rmw((eth)->fe_regs, (offset), (val), 0)
820
821 #define airoha_qdma_rr(eth, offset) \
822 airoha_rr((eth)->qdma_regs, (offset))
823 #define airoha_qdma_wr(eth, offset, val) \
824 airoha_wr((eth)->qdma_regs, (offset), (val))
825 #define airoha_qdma_rmw(eth, offset, mask, val) \
826 airoha_rmw((eth)->qdma_regs, (offset), (mask), (val))
827 #define airoha_qdma_set(eth, offset, val) \
828 airoha_rmw((eth)->qdma_regs, (offset), 0, (val))
829 #define airoha_qdma_clear(eth, offset, val) \
830 airoha_rmw((eth)->qdma_regs, (offset), (val), 0)
831
832 static void airoha_qdma_set_irqmask(struct airoha_eth *eth, int index,
833 u32 clear, u32 set)
834 {
835 unsigned long flags;
836
837 if (WARN_ON_ONCE(index >= ARRAY_SIZE(eth->irqmask)))
838 return;
839
840 spin_lock_irqsave(&eth->irq_lock, flags);
841
842 eth->irqmask[index] &= ~clear;
843 eth->irqmask[index] |= set;
844 airoha_qdma_wr(eth, REG_INT_ENABLE(index), eth->irqmask[index]);
845 /* Read irq_enable register in order to guarantee the update above
846 * completes in the spinlock critical section.
847 */

 > 848		airoha_rr(eth, REG_INT_ENABLE(index));

849
850 spin_unlock_irqrestore(&eth->irq_lock, flags);
851 }
852

Signature · 2 lines
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki