Skip to contentSkip to conversation

SAMA7D65 Add support for Crypto, CAN and PWM

PATCH Applied [email protected] 4 participants 16 messages Jun 11, 2025 – Jun 24, 2025

Subsystems (4)
Device tree bindings Crypto API Arm/Microchip (AT91) SoC support Hardware random number generator core
lore
Share & tools
lore

[email protected]

author
#0 lore raw

v2 cover SAMA7D65 Add support for Crypto, CAN and PWM

From: Ryan Wanner <[email protected]>

This set adds support for the SAMA7D65 SoC crypto subsystem and enabling them in the device tree. This set also adds PWM to the device tree, and adds and enables the CAN bus system for the SAMA7D65 SoC.

Changes v1 -> v2:
- Clean up formatting issues in the device tree and DT bindings.
- Add a description of the capabilities for the cyrpto IPs for this SoC.

Ryan Wanner (10):
dt-bindings: crypto: add sama7d65 in Atmel AES
dt-bindings: crypto: add sama7d65 in Atmel SHA
dt-bindings: crypto: add sama7d65 in Atmel TDES
dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
crypto: atmel - add support for AES and SHA IPs available on sama7d65
SoC
ARM: dts: microchip: sama7d65: Add crypto support
ARM: dts: microchip: sama7d65: Add PWM support
ARM: dts: microchip: sama7d65: Add CAN bus support
ARM: dts: microchip: sama7d65: Clean up extra space
ARM: dts: microchip: sama7d65: Enable CAN bus

 .../crypto/atmel,at91sam9g46-aes.yaml         |   4 +-
 .../crypto/atmel,at91sam9g46-sha.yaml         |   4 +-
 .../crypto/atmel,at91sam9g46-tdes.yaml        |   4 +-
 .../bindings/rng/atmel,at91-trng.yaml         |   1 +
 .../dts/microchip/at91-sama7d65_curiosity.dts |  35 +++++
 arch/arm/boot/dts/microchip/sama7d65.dtsi     | 128 ++++++++++++++++++
 drivers/crypto/atmel-aes.c                    |   1 +
 drivers/crypto/atmel-sha.c                    |   1 +
 8 files changed, 175 insertions(+), 3 deletions(-)
Signature · 1 line
2.43.0
author
#1 lore raw

PATCH v2 1/10 dt-bindings: crypto: add sama7d65 in Atmel AES

From: Ryan Wanner <[email protected]>

Add DT bindings for SAMA7D65 SoC in atmel AES.

The SAMA7D65 similar to the SAM9x75 SoC supports HMAC, dual buffer, and GCM. And similar all 3 it supports CBC, CFB, CTR, ECB, and XTS.

Signed-off-by Ryan Wanner <[email protected]>
---
 .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml     | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +3 -1
index 7dc0748444fd..19010f90198a 100644
@@ -15,7 +15,9 @@ properties:
     oneOf:
       - const: atmel,at91sam9g46-aes
       - items:
-          - const: microchip,sam9x7-aes
+          - enum:
+              - microchip,sam9x7-aes
+              - microchip,sama7d65-aes
           - const: atmel,at91sam9g46-aes
 
   reg:
Signature · 1 line
2.43.0
Acked-by on v2 1/10
#2 lore raw

Re: [PATCH v2 01/10] dt-bindings: crypto: add sama7d65 in Atmel AES

Quoted 8 lines · On Wed, Jun 11, 2025 at 12:47:25PM GMT, [email protected] wrote:

From: Ryan Wanner <[email protected]>

Add DT bindings for SAMA7D65 SoC in atmel AES.

The SAMA7D65 similar to the SAM9x75 SoC supports HMAC, dual buffer, and GCM. And similar all 3 it supports CBC, CFB, CTR, ECB, and XTS.

Signed-off-by Ryan Wanner <[email protected]>
Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

author
#3 lore raw

PATCH v2 2/10 dt-bindings: crypto: add sama7d65 in Atmel SHA

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Add DT bindings for SAMA7D65 SoC Atmel SHA.

The SAMA7D65 similar to the SAM9x75 SoC supports SHA1/224/256/384/512 and supports HMAC for the same hashes. They both also support automatic padding as well as double buffering.

Signed-off-by Ryan Wanner <[email protected]>
---
 .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml     | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +3 -1
index d378c53314dd..39e076b275b3 100644
@@ -15,7 +15,9 @@ properties:
     oneOf:
       - const: atmel,at91sam9g46-sha
       - items:
-          - const: microchip,sam9x7-sha
+          - enum:
+              - microchip,sam9x7-sha
+              - microchip,sama7d65-sha
           - const: atmel,at91sam9g46-sha
 
   reg:
Signature · 1 line
2.43.0
Acked-by on v2 2/10
#4 lore raw

Re: [PATCH v2 02/10] dt-bindings: crypto: add sama7d65 in Atmel SHA

Quoted 4 lines · On Wed, Jun 11, 2025 at 12:47:26PM GMT, [email protected] wrote:

From: Ryan Wanner <[email protected]>

Add DT bindings for SAMA7D65 SoC Atmel SHA.

Quoted 8 lines

The SAMA7D65 similar to the SAM9x75 SoC supports SHA1/224/256/384/512 and supports HMAC for the same hashes. They both also support automatic padding as well as double buffering.

Signed-off-by Ryan Wanner <[email protected]>
---
 .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml     | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

author
#5 lore raw

PATCH v2 3/10 dt-bindings: crypto: add sama7d65 in Atmel TDES

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Add DT bindings for SAMA7D65 SoC Atmel TDES.

The SAMA7D65 SoC has the same capability as the SAM9x75 SoC.

Signed-off-by Ryan Wanner <[email protected]>
---
 .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml    | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml +3 -1
index 6a441f79efea..6f16008c4251 100644
@@ -15,7 +15,9 @@ properties:
     oneOf:
       - const: atmel,at91sam9g46-tdes
       - items:
-          - const: microchip,sam9x7-tdes
+          - enum:
+              - microchip,sam9x7-tdes
+              - microchip,sama7d65-tdes
           - const: atmel,at91sam9g46-tdes
 
   reg:
Signature · 1 line
2.43.0
Acked-by on v2 3/10
#6 lore raw

Re: [PATCH v2 03/10] dt-bindings: crypto: add sama7d65 in Atmel TDES

Quoted 9 lines · On Wed, Jun 11, 2025 at 12:47:27PM GMT, [email protected] wrote:

From: Ryan Wanner <[email protected]>

Add DT bindings for SAMA7D65 SoC Atmel TDES.

The SAMA7D65 SoC has the same capability as the SAM9x75 SoC.

Signed-off-by Ryan Wanner <[email protected]>
---
 .../devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml    | 4 +++-
Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

author
#7 lore raw

PATCH v2 4/10 dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Add compatible for Microchip SAMA7D65 SoC TRNG.

Signed-off-by Ryan Wanner <[email protected]>
Reviewed-by Claudiu Beznea <[email protected]>
Acked-by Rob Herring (Arm) <[email protected]>
---
 Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml +1 -0
index b38f8252342e..f78614100ea8 100644
@@ -24,6 +24,7 @@ properties:
       - items:
           - enum:
               - microchip,sam9x7-trng
+              - microchip,sama7d65-trng
           - const: microchip,sam9x60-trng
 
   clocks:
Signature · 1 line
2.43.0
author
#8 lore raw

PATCH v2 5/10 crypto: atmel - add support for AES and SHA IPs available on sama7d65 SoC

In reply to [email protected]

From: Ryan Wanner <[email protected]>

This patch adds support for hardware version of AES and SHA IPs available on SAMA7D65 SoC.

Signed-off-by Ryan Wanner <[email protected]>
---
 drivers/crypto/atmel-aes.c | 1 +
 drivers/crypto/atmel-sha.c | 1 +
 2 files changed, 2 insertions(+)
drivers/crypto/atmel-aes.c +1 -0
index 14bf86957d31..4a3db3dca272 100644
@@ -2296,6 +2296,7 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
 
 	/* keep only major version number */
 	switch (dd->hw_version & 0xff0) {
+	case 0x800:
 	case 0x700:
 	case 0x600:
 	case 0x500:
drivers/crypto/atmel-sha.c +1 -0
index 67a170608566..f7021925349e 100644
@@ -2532,6 +2532,7 @@ static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
 
 	/* keep only major version number */
 	switch (dd->hw_version & 0xff0) {
+	case 0x800:
 	case 0x700:
 	case 0x600:
 	case 0x510:
Signature · 1 line
2.43.0
author
#9 lore raw

PATCH v2 6/10 ARM: dts: microchip: sama7d65: Add crypto support

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Add and enable SHA, AES, TDES, and TRNG for SAMA7D65 SoC.

Signed-off-by Ryan Wanner <[email protected]>
Reviewed-by Claudiu Beznea <[email protected]>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 39 +++++++++++++++++++++++
 1 file changed, 39 insertions(+)
arch/arm/boot/dts/microchip/sama7d65.dtsi +39 -0
index d08d773b1cc5..90cbea576d91 100644
@@ -186,6 +186,45 @@ sdmmc1: mmc@e1208000 {
 			status = "disabled";
 		};
 
+		aes: crypto@e1600000 {
+			compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes";
+			reg = <0xe1600000 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
+			clock-names = "aes_clk";
+			dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
+			       <&dma0 AT91_XDMAC_DT_PERID(2)>;
+			dma-names = "tx", "rx";
+		};
+
+		sha: crypto@e1604000 {
+			compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha";
+			reg = <0xe1604000 0x100>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 78>;
+			clock-names = "sha_clk";
+			dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
+			dma-names = "tx";
+		};
+
+		tdes: crypto@e1608000 {
+			compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes";
+			reg = <0xe1608000 0x100>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 91>;
+			clock-names = "tdes_clk";
+			dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
+			       <&dma0 AT91_XDMAC_DT_PERID(53)>;
+			dma-names = "tx", "rx";
+		};
+
+		trng: rng@e160c000 {
+			compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng";
+			reg = <0xe160c000 0x100>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 92>;
+		};
+
 		dma0: dma-controller@e1610000 {
 			compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
 			reg = <0xe1610000 0x1000>;
Signature · 1 line
2.43.0
author
#10 lore raw

PATCH v2 7/10 ARM: dts: microchip: sama7d65: Add PWM support

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Add support for PWMs to the SAMA7D65 SoC.

Signed-off-by Ryan Wanner <[email protected]>
Reviewed-by Claudiu Beznea <[email protected]>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/boot/dts/microchip/sama7d65.dtsi +9 -0
index 90cbea576d91..796909fa2368 100644
@@ -293,6 +293,15 @@ pit64b1: timer@e1804000 {
 			clock-names = "pclk", "gclk";
 		};
 
+		pwm: pwm@e1818000 {
+			compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm";
+			reg = <0xe1818000 0x500>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 72>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
 		flx0: flexcom@e1820000 {
 			compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
 			reg = <0xe1820000 0x200>;
Signature · 1 line
2.43.0
author
#11 lore raw

PATCH v2 8/10 ARM: dts: microchip: sama7d65: Add CAN bus support

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Add support for CAN bus to the SAMA7D65 SoC.

Signed-off-by Ryan Wanner <[email protected]>
Reviewed-by Claudiu Beznea <[email protected]>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 80 +++++++++++++++++++++++
 1 file changed, 80 insertions(+)
arch/arm/boot/dts/microchip/sama7d65.dtsi +80 -0
index 796909fa2368..a62d2ef9fcab 100644
@@ -163,6 +163,86 @@ chipid@e0020000 {
 			reg = <0xe0020000 0x8>;
 		};
 
+		can0: can@e0828000 {
+			compatible = "bosch,m_can";
+			reg = <0xe0828000 0x200>, <0x100000 0x7800>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 58>;
+			assigned-clock-rates = <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can1: can@e082c000 {
+			compatible = "bosch,m_can";
+			reg = <0xe082c000 0x200>, <0x100000 0xbc00>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 59>;
+			assigned-clock-rates = <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can2: can@e0830000 {
+			compatible = "bosch,m_can";
+			reg = <0xe0830000 0x200>, <0x100000 0x10000>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 60>;
+			assigned-clock-rates = <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can3: can@e0834000 {
+			compatible = "bosch,m_can";
+			reg = <0xe0834000 0x200>, <0x110000 0x4400>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
+			assigned-clock-rates = <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can4: can@e0838000 {
+			compatible = "bosch,m_can";
+			reg = <0xe0838000 0x200>, <0x110000 0x8800>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
+			assigned-clock-rates = <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
 		dma2: dma-controller@e1200000 {
 			compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
 			reg = <0xe1200000 0x1000>;
Signature · 1 line
2.43.0
author
#12 lore raw

PATCH v2 9/10 ARM: dts: microchip: sama7d65: Clean up extra space

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Remove the extra space that causes formatting issues.

Signed-off-by Ryan Wanner <[email protected]>
---
 arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts | 1 -
 1 file changed, 1 deletion(-)
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +0 -1
index 53a657cf4efb..759b963d987c 100644
@@ -38,7 +38,6 @@ reg_5v: regulator-5v {
 		regulator-max-microvolt = <5000000>;
 		regulator-always-on;
 	};
-
 };
 
 &dma0 {
Signature · 1 line
2.43.0
author
#13 lore raw

PATCH v2 10/10 ARM: dts: microchip: sama7d65: Enable CAN bus

In reply to [email protected]

From: Ryan Wanner <[email protected]>

Enable CAN bus for SAMA7D65 curiosity board.

Signed-off-by Ryan Wanner <[email protected]>
Reviewed-by Claudiu Beznea <[email protected]>
---
 .../dts/microchip/at91-sama7d65_curiosity.dts | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +36 -0
index 759b963d987c..7eaf6ca233ec 100644
@@ -40,6 +40,24 @@ reg_5v: regulator-5v {
 	};
 };
 
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_default>;
+	status = "okay";
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can2_default>;
+	status = "okay";
+};
+
+&can3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can3_default>;
+	status = "okay";
+};
+
 &dma0 {
 	status = "okay";
 };

@@ -277,6 +295,24 @@ &main_xtal {
 };
 
 &pioa {
+	pinctrl_can1_default: can1-default {
+		pinmux = <PIN_PD10__CANTX1>,
+			 <PIN_PD11__CANRX1>;
+		bias-disable;
+	};
+
+	pinctrl_can2_default: can2-default {
+		pinmux = <PIN_PD12__CANTX2>,
+			 <PIN_PD13__CANRX2>;
+		bias-disable;
+	};
+
+	pinctrl_can3_default: can3-default {
+		pinmux = <PIN_PD14__CANTX3>,
+			 <PIN_PD15__CANRX3>;
+		bias-disable;
+	};
+
 	pinctrl_gmac0_default: gmac0-default {
 		pinmux = <PIN_PA26__G0_TX0>,
 			 <PIN_PA27__G0_TX1>,
Signature · 1 line
2.43.0
maintainer
#14 lore raw
In reply to [email protected]
Quoted 23 lines · On Wed, Jun 11, 2025 at 12:47:24PM -0700, [email protected] wrote:

From: Ryan Wanner <[email protected]>

This set adds support for the SAMA7D65 SoC crypto subsystem and enabling them in the device tree. This set also adds PWM to the device tree, and adds and enables the CAN bus system for the SAMA7D65 SoC.

Changes v1 -> v2:
- Clean up formatting issues in the device tree and DT bindings.
- Add a description of the capabilities for the cyrpto IPs for this SoC.

Ryan Wanner (10):
dt-bindings: crypto: add sama7d65 in Atmel AES
dt-bindings: crypto: add sama7d65 in Atmel SHA
dt-bindings: crypto: add sama7d65 in Atmel TDES
dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
crypto: atmel - add support for AES and SHA IPs available on sama7d65
SoC
ARM: dts: microchip: sama7d65: Add crypto support
ARM: dts: microchip: sama7d65: Add PWM support
ARM: dts: microchip: sama7d65: Add CAN bus support
ARM: dts: microchip: sama7d65: Clean up extra space
ARM: dts: microchip: sama7d65: Enable CAN bus

Quoted 12 lines
 .../crypto/atmel,at91sam9g46-aes.yaml         |   4 +-
 .../crypto/atmel,at91sam9g46-sha.yaml         |   4 +-
 .../crypto/atmel,at91sam9g46-tdes.yaml        |   4 +-
 .../bindings/rng/atmel,at91-trng.yaml         |   1 +
 .../dts/microchip/at91-sama7d65_curiosity.dts |  35 +++++
 arch/arm/boot/dts/microchip/sama7d65.dtsi     | 128 ++++++++++++++++++
 drivers/crypto/atmel-aes.c                    |   1 +
 drivers/crypto/atmel-sha.c                    |   1 +
 8 files changed, 175 insertions(+), 3 deletions(-)
Signature · 1 line
2.43.0

Patches 1-5 applied. Thanks.

Signature · 3 lines
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
maintainer Applied
#15 lore raw
In reply to [email protected]
Quoted 5 lines · On 11.06.2025 22:47, [email protected] wrote:

ARM: dts: microchip: sama7d65: Add crypto support
ARM: dts: microchip: sama7d65: Add PWM support
ARM: dts: microchip: sama7d65: Add CAN bus support
ARM: dts: microchip: sama7d65: Clean up extra space
ARM: dts: microchip: sama7d65: Enable CAN bus

Applied to at91-dt, thanks!