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riscv: dts: sophgo: add more sg2042 isa extension support

PATCH Applied Han Gao 4 participants 11 messages Jul 5, 2025 – Jul 10, 2025

Subsystems (3)
Device tree bindings RISC-V Sophgo devicetrees and drivers
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Han Gao

author
#0 lore raw

v3 cover riscv: dts: sophgo: add more sg2042 isa extension support

Add xtheadvector & ziccrse & zfh for sg2042

Thanks,
Han

---

Changes in v3:
remove zfh in riscv,isa

Changes in v2:
add zfh for sg2042

v2: https://lore.kernel.org/linux-riscv/[email protected]/
v1: https://lore.kernel.org/linux-riscv/[email protected]/

Han Gao (3):
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
riscv: dts: sophgo: add ziccrse for sg2042
riscv: dts: sophgo: add zfh for sg2042

 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 384 +++++++++++++-------
 1 file changed, 256 insertions(+), 128 deletions(-)
Signature · 1 line
2.47.2
author
#1 lore raw

PATCH v3 1/3 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree

The sg2042 SoCs support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].

This can be tested by passing the "mitigations=off" kernel parameter.

Link https://lore.kernel.org/linux-riscv/[email protected]/ [1] open here
Link https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] open here
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
---
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
 1 file changed, 128 insertions(+), 64 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +128 -64
index b136b6c4128c..dcc984965b6b 100644
@@ -260,7 +260,8 @@ cpu0: cpu@0 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -285,7 +286,8 @@ cpu1: cpu@1 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -310,7 +312,8 @@ cpu2: cpu@2 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -335,7 +338,8 @@ cpu3: cpu@3 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -360,7 +364,8 @@ cpu4: cpu@4 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <4>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -385,7 +390,8 @@ cpu5: cpu@5 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <5>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -410,7 +416,8 @@ cpu6: cpu@6 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <6>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -435,7 +442,8 @@ cpu7: cpu@7 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <7>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -460,7 +468,8 @@ cpu8: cpu@8 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <8>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -485,7 +494,8 @@ cpu9: cpu@9 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <9>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -510,7 +520,8 @@ cpu10: cpu@10 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <10>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -535,7 +546,8 @@ cpu11: cpu@11 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <11>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -560,7 +572,8 @@ cpu12: cpu@12 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <12>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -585,7 +598,8 @@ cpu13: cpu@13 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <13>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -610,7 +624,8 @@ cpu14: cpu@14 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <14>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -635,7 +650,8 @@ cpu15: cpu@15 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <15>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -660,7 +676,8 @@ cpu16: cpu@16 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <16>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -685,7 +702,8 @@ cpu17: cpu@17 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <17>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -710,7 +728,8 @@ cpu18: cpu@18 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <18>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -735,7 +754,8 @@ cpu19: cpu@19 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <19>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -760,7 +780,8 @@ cpu20: cpu@20 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <20>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -785,7 +806,8 @@ cpu21: cpu@21 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <21>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -810,7 +832,8 @@ cpu22: cpu@22 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <22>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -835,7 +858,8 @@ cpu23: cpu@23 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <23>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -860,7 +884,8 @@ cpu24: cpu@24 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <24>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -885,7 +910,8 @@ cpu25: cpu@25 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <25>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -910,7 +936,8 @@ cpu26: cpu@26 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <26>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -935,7 +962,8 @@ cpu27: cpu@27 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <27>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -960,7 +988,8 @@ cpu28: cpu@28 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <28>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -985,7 +1014,8 @@ cpu29: cpu@29 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <29>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <30>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <31>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <32>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <33>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <34>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <35>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <36>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <37>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <38>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <39>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <40>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <41>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <42>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <43>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <44>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <45>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <46>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <47>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <48>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <49>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <50>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <51>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <52>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <53>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <54>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <55>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <56>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <57>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <58>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <59>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <60>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <61>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <62>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <63>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
Signature · 1 line
2.47.2
Reviewed-by on v3 1/3
#2 lore raw

Re: [PATCH v3 1/3] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree

Quoted 10 lines · Han Gao

The sg2042 SoCs support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].

This can be tested by passing the "mitigations=off" kernel parameter.

Link https://lore.kernel.org/linux-riscv/[email protected]/ [1] open here
Link https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] open here
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
Reviewed-by Chen Wang <[email protected]>
Quoted 648 lines
---
  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
  1 file changed, 128 insertions(+), 64 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +128 -64
index b136b6c4128c..dcc984965b6b 100644
@@ -260,7 +260,8 @@ cpu0: cpu@0 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <0>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -285,7 +286,8 @@ cpu1: cpu@1 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <1>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -310,7 +312,8 @@ cpu2: cpu@2 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <2>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -335,7 +338,8 @@ cpu3: cpu@3 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <3>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -360,7 +364,8 @@ cpu4: cpu@4 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <4>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -385,7 +390,8 @@ cpu5: cpu@5 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <5>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -410,7 +416,8 @@ cpu6: cpu@6 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <6>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -435,7 +442,8 @@ cpu7: cpu@7 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <7>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -460,7 +468,8 @@ cpu8: cpu@8 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <8>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -485,7 +494,8 @@ cpu9: cpu@9 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <9>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -510,7 +520,8 @@ cpu10: cpu@10 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <10>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -535,7 +546,8 @@ cpu11: cpu@11 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <11>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -560,7 +572,8 @@ cpu12: cpu@12 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <12>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -585,7 +598,8 @@ cpu13: cpu@13 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <13>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -610,7 +624,8 @@ cpu14: cpu@14 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <14>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -635,7 +650,8 @@ cpu15: cpu@15 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <15>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -660,7 +676,8 @@ cpu16: cpu@16 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <16>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -685,7 +702,8 @@ cpu17: cpu@17 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <17>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -710,7 +728,8 @@ cpu18: cpu@18 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <18>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -735,7 +754,8 @@ cpu19: cpu@19 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <19>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -760,7 +780,8 @@ cpu20: cpu@20 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <20>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -785,7 +806,8 @@ cpu21: cpu@21 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <21>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -810,7 +832,8 @@ cpu22: cpu@22 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <22>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -835,7 +858,8 @@ cpu23: cpu@23 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <23>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -860,7 +884,8 @@ cpu24: cpu@24 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <24>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -885,7 +910,8 @@ cpu25: cpu@25 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <25>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -910,7 +936,8 @@ cpu26: cpu@26 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <26>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -935,7 +962,8 @@ cpu27: cpu@27 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <27>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -960,7 +988,8 @@ cpu28: cpu@28 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <28>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -985,7 +1014,8 @@ cpu29: cpu@29 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <29>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <30>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <31>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <32>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <33>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <34>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <35>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <36>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <37>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <38>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <39>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <40>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <41>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <42>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <43>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <44>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <45>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <46>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <47>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <48>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <49>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <50>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <51>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <52>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <53>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <54>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <55>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <56>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <57>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <58>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <59>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <60>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <61>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <62>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <63>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;
Reviewed-by on v3 1/3
#3 lore raw

Re: [PATCH v3 1/3] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree

In reply to Han Gao
Quoted 10 lines · Han Gao

The sg2042 SoCs support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].

This can be tested by passing the "mitigations=off" kernel parameter.

Link https://lore.kernel.org/linux-riscv/[email protected]/ [1] open here
Link https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] open here
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
Reviewed-by Nutty Liu<[email protected]>

Thanks,
Nutty

Quoted 648 lines
---
  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
  1 file changed, 128 insertions(+), 64 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +128 -64
index b136b6c4128c..dcc984965b6b 100644
@@ -260,7 +260,8 @@ cpu0: cpu@0 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <0>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -285,7 +286,8 @@ cpu1: cpu@1 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <1>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -310,7 +312,8 @@ cpu2: cpu@2 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <2>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -335,7 +338,8 @@ cpu3: cpu@3 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <3>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -360,7 +364,8 @@ cpu4: cpu@4 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <4>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -385,7 +390,8 @@ cpu5: cpu@5 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <5>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -410,7 +416,8 @@ cpu6: cpu@6 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <6>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -435,7 +442,8 @@ cpu7: cpu@7 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <7>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -460,7 +468,8 @@ cpu8: cpu@8 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <8>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -485,7 +494,8 @@ cpu9: cpu@9 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <9>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -510,7 +520,8 @@ cpu10: cpu@10 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <10>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -535,7 +546,8 @@ cpu11: cpu@11 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <11>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -560,7 +572,8 @@ cpu12: cpu@12 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <12>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -585,7 +598,8 @@ cpu13: cpu@13 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <13>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -610,7 +624,8 @@ cpu14: cpu@14 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <14>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -635,7 +650,8 @@ cpu15: cpu@15 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <15>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -660,7 +676,8 @@ cpu16: cpu@16 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <16>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -685,7 +702,8 @@ cpu17: cpu@17 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <17>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -710,7 +728,8 @@ cpu18: cpu@18 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <18>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -735,7 +754,8 @@ cpu19: cpu@19 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <19>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -760,7 +780,8 @@ cpu20: cpu@20 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <20>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -785,7 +806,8 @@ cpu21: cpu@21 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <21>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -810,7 +832,8 @@ cpu22: cpu@22 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <22>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -835,7 +858,8 @@ cpu23: cpu@23 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <23>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -860,7 +884,8 @@ cpu24: cpu@24 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <24>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -885,7 +910,8 @@ cpu25: cpu@25 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <25>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -910,7 +936,8 @@ cpu26: cpu@26 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <26>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -935,7 +962,8 @@ cpu27: cpu@27 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <27>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -960,7 +988,8 @@ cpu28: cpu@28 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <28>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -985,7 +1014,8 @@ cpu29: cpu@29 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <29>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <30>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <31>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <32>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <33>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <34>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <35>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <36>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <37>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <38>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <39>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <40>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <41>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <42>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <43>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <44>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <45>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <46>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <47>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <48>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <49>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <50>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <51>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <52>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <53>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <54>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <55>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <56>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <57>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <58>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <59>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <60>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <61>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <62>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;

@@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
  			reg = <63>;
  			i-cache-block-size = <64>;
  			i-cache-size = <65536>;
author
#4 lore raw

PATCH v3 2/3 riscv: dts: sophgo: add ziccrse for sg2042

In reply to Han Gao

sg2042 support Ziccrse ISA extension [1].

Link https://lore.kernel.org/all/[email protected]/ [1] open here
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
---
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 320 ++++++++++++--------
 1 file changed, 192 insertions(+), 128 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +192 -128
index dcc984965b6b..f483f62ab0c4 100644
@@ -259,8 +259,9 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <0>;
 			i-cache-block-size = <64>;

@@ -285,8 +286,9 @@ cpu1: cpu@1 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <1>;
 			i-cache-block-size = <64>;

@@ -311,8 +313,9 @@ cpu2: cpu@2 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <2>;
 			i-cache-block-size = <64>;

@@ -337,8 +340,9 @@ cpu3: cpu@3 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <3>;
 			i-cache-block-size = <64>;

@@ -363,8 +367,9 @@ cpu4: cpu@4 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <4>;
 			i-cache-block-size = <64>;

@@ -389,8 +394,9 @@ cpu5: cpu@5 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <5>;
 			i-cache-block-size = <64>;

@@ -415,8 +421,9 @@ cpu6: cpu@6 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <6>;
 			i-cache-block-size = <64>;

@@ -441,8 +448,9 @@ cpu7: cpu@7 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <7>;
 			i-cache-block-size = <64>;

@@ -467,8 +475,9 @@ cpu8: cpu@8 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <8>;
 			i-cache-block-size = <64>;

@@ -493,8 +502,9 @@ cpu9: cpu@9 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <9>;
 			i-cache-block-size = <64>;

@@ -519,8 +529,9 @@ cpu10: cpu@10 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <10>;
 			i-cache-block-size = <64>;

@@ -545,8 +556,9 @@ cpu11: cpu@11 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <11>;
 			i-cache-block-size = <64>;

@@ -571,8 +583,9 @@ cpu12: cpu@12 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <12>;
 			i-cache-block-size = <64>;

@@ -597,8 +610,9 @@ cpu13: cpu@13 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <13>;
 			i-cache-block-size = <64>;

@@ -623,8 +637,9 @@ cpu14: cpu@14 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <14>;
 			i-cache-block-size = <64>;

@@ -649,8 +664,9 @@ cpu15: cpu@15 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <15>;
 			i-cache-block-size = <64>;

@@ -675,8 +691,9 @@ cpu16: cpu@16 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <16>;
 			i-cache-block-size = <64>;

@@ -701,8 +718,9 @@ cpu17: cpu@17 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <17>;
 			i-cache-block-size = <64>;

@@ -727,8 +745,9 @@ cpu18: cpu@18 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <18>;
 			i-cache-block-size = <64>;

@@ -753,8 +772,9 @@ cpu19: cpu@19 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <19>;
 			i-cache-block-size = <64>;

@@ -779,8 +799,9 @@ cpu20: cpu@20 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <20>;
 			i-cache-block-size = <64>;

@@ -805,8 +826,9 @@ cpu21: cpu@21 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <21>;
 			i-cache-block-size = <64>;

@@ -831,8 +853,9 @@ cpu22: cpu@22 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <22>;
 			i-cache-block-size = <64>;

@@ -857,8 +880,9 @@ cpu23: cpu@23 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <23>;
 			i-cache-block-size = <64>;

@@ -883,8 +907,9 @@ cpu24: cpu@24 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <24>;
 			i-cache-block-size = <64>;

@@ -909,8 +934,9 @@ cpu25: cpu@25 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <25>;
 			i-cache-block-size = <64>;

@@ -935,8 +961,9 @@ cpu26: cpu@26 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <26>;
 			i-cache-block-size = <64>;

@@ -961,8 +988,9 @@ cpu27: cpu@27 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <27>;
 			i-cache-block-size = <64>;

@@ -987,8 +1015,9 @@ cpu28: cpu@28 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <28>;
 			i-cache-block-size = <64>;

@@ -1013,8 +1042,9 @@ cpu29: cpu@29 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <29>;
 			i-cache-block-size = <64>;

@@ -1039,8 +1069,9 @@ cpu30: cpu@30 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <30>;
 			i-cache-block-size = <64>;

@@ -1065,8 +1096,9 @@ cpu31: cpu@31 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <31>;
 			i-cache-block-size = <64>;

@@ -1091,8 +1123,9 @@ cpu32: cpu@32 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <32>;
 			i-cache-block-size = <64>;

@@ -1117,8 +1150,9 @@ cpu33: cpu@33 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <33>;
 			i-cache-block-size = <64>;

@@ -1143,8 +1177,9 @@ cpu34: cpu@34 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <34>;
 			i-cache-block-size = <64>;

@@ -1169,8 +1204,9 @@ cpu35: cpu@35 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <35>;
 			i-cache-block-size = <64>;

@@ -1195,8 +1231,9 @@ cpu36: cpu@36 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <36>;
 			i-cache-block-size = <64>;

@@ -1221,8 +1258,9 @@ cpu37: cpu@37 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <37>;
 			i-cache-block-size = <64>;

@@ -1247,8 +1285,9 @@ cpu38: cpu@38 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <38>;
 			i-cache-block-size = <64>;

@@ -1273,8 +1312,9 @@ cpu39: cpu@39 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <39>;
 			i-cache-block-size = <64>;

@@ -1299,8 +1339,9 @@ cpu40: cpu@40 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <40>;
 			i-cache-block-size = <64>;

@@ -1325,8 +1366,9 @@ cpu41: cpu@41 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <41>;
 			i-cache-block-size = <64>;

@@ -1351,8 +1393,9 @@ cpu42: cpu@42 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <42>;
 			i-cache-block-size = <64>;

@@ -1377,8 +1420,9 @@ cpu43: cpu@43 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <43>;
 			i-cache-block-size = <64>;

@@ -1403,8 +1447,9 @@ cpu44: cpu@44 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <44>;
 			i-cache-block-size = <64>;

@@ -1429,8 +1474,9 @@ cpu45: cpu@45 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <45>;
 			i-cache-block-size = <64>;

@@ -1455,8 +1501,9 @@ cpu46: cpu@46 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <46>;
 			i-cache-block-size = <64>;

@@ -1481,8 +1528,9 @@ cpu47: cpu@47 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <47>;
 			i-cache-block-size = <64>;

@@ -1507,8 +1555,9 @@ cpu48: cpu@48 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <48>;
 			i-cache-block-size = <64>;

@@ -1533,8 +1582,9 @@ cpu49: cpu@49 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <49>;
 			i-cache-block-size = <64>;

@@ -1559,8 +1609,9 @@ cpu50: cpu@50 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <50>;
 			i-cache-block-size = <64>;

@@ -1585,8 +1636,9 @@ cpu51: cpu@51 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <51>;
 			i-cache-block-size = <64>;

@@ -1611,8 +1663,9 @@ cpu52: cpu@52 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <52>;
 			i-cache-block-size = <64>;

@@ -1637,8 +1690,9 @@ cpu53: cpu@53 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <53>;
 			i-cache-block-size = <64>;

@@ -1663,8 +1717,9 @@ cpu54: cpu@54 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <54>;
 			i-cache-block-size = <64>;

@@ -1689,8 +1744,9 @@ cpu55: cpu@55 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <55>;
 			i-cache-block-size = <64>;

@@ -1715,8 +1771,9 @@ cpu56: cpu@56 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <56>;
 			i-cache-block-size = <64>;

@@ -1741,8 +1798,9 @@ cpu57: cpu@57 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <57>;
 			i-cache-block-size = <64>;

@@ -1767,8 +1825,9 @@ cpu58: cpu@58 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <58>;
 			i-cache-block-size = <64>;

@@ -1793,8 +1852,9 @@ cpu59: cpu@59 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <59>;
 			i-cache-block-size = <64>;

@@ -1819,8 +1879,9 @@ cpu60: cpu@60 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <60>;
 			i-cache-block-size = <64>;

@@ -1845,8 +1906,9 @@ cpu61: cpu@61 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <61>;
 			i-cache-block-size = <64>;

@@ -1871,8 +1933,9 @@ cpu62: cpu@62 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <62>;
 			i-cache-block-size = <64>;

@@ -1897,8 +1960,9 @@ cpu63: cpu@63 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <63>;
 			i-cache-block-size = <64>;
Signature · 1 line
2.47.2
Reviewed-by on v3 2/3
#5 lore raw

Re: [PATCH v3 2/3] riscv: dts: sophgo: add ziccrse for sg2042

Quoted 6 lines · Han Gao

sg2042 support Ziccrse ISA extension [1].

Link https://lore.kernel.org/all/[email protected]/ [1] open here
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
Reviewed-by Chen Wang <[email protected]>
Quoted 776 lines
---
  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 320 ++++++++++++--------
  1 file changed, 192 insertions(+), 128 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +192 -128
index dcc984965b6b..f483f62ab0c4 100644
@@ -259,8 +259,9 @@ cpu0: cpu@0 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <0>;
  			i-cache-block-size = <64>;

@@ -285,8 +286,9 @@ cpu1: cpu@1 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <1>;
  			i-cache-block-size = <64>;

@@ -311,8 +313,9 @@ cpu2: cpu@2 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <2>;
  			i-cache-block-size = <64>;

@@ -337,8 +340,9 @@ cpu3: cpu@3 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <3>;
  			i-cache-block-size = <64>;

@@ -363,8 +367,9 @@ cpu4: cpu@4 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <4>;
  			i-cache-block-size = <64>;

@@ -389,8 +394,9 @@ cpu5: cpu@5 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <5>;
  			i-cache-block-size = <64>;

@@ -415,8 +421,9 @@ cpu6: cpu@6 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <6>;
  			i-cache-block-size = <64>;

@@ -441,8 +448,9 @@ cpu7: cpu@7 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <7>;
  			i-cache-block-size = <64>;

@@ -467,8 +475,9 @@ cpu8: cpu@8 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <8>;
  			i-cache-block-size = <64>;

@@ -493,8 +502,9 @@ cpu9: cpu@9 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <9>;
  			i-cache-block-size = <64>;

@@ -519,8 +529,9 @@ cpu10: cpu@10 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <10>;
  			i-cache-block-size = <64>;

@@ -545,8 +556,9 @@ cpu11: cpu@11 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <11>;
  			i-cache-block-size = <64>;

@@ -571,8 +583,9 @@ cpu12: cpu@12 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <12>;
  			i-cache-block-size = <64>;

@@ -597,8 +610,9 @@ cpu13: cpu@13 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <13>;
  			i-cache-block-size = <64>;

@@ -623,8 +637,9 @@ cpu14: cpu@14 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <14>;
  			i-cache-block-size = <64>;

@@ -649,8 +664,9 @@ cpu15: cpu@15 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <15>;
  			i-cache-block-size = <64>;

@@ -675,8 +691,9 @@ cpu16: cpu@16 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <16>;
  			i-cache-block-size = <64>;

@@ -701,8 +718,9 @@ cpu17: cpu@17 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <17>;
  			i-cache-block-size = <64>;

@@ -727,8 +745,9 @@ cpu18: cpu@18 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <18>;
  			i-cache-block-size = <64>;

@@ -753,8 +772,9 @@ cpu19: cpu@19 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <19>;
  			i-cache-block-size = <64>;

@@ -779,8 +799,9 @@ cpu20: cpu@20 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <20>;
  			i-cache-block-size = <64>;

@@ -805,8 +826,9 @@ cpu21: cpu@21 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <21>;
  			i-cache-block-size = <64>;

@@ -831,8 +853,9 @@ cpu22: cpu@22 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <22>;
  			i-cache-block-size = <64>;

@@ -857,8 +880,9 @@ cpu23: cpu@23 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <23>;
  			i-cache-block-size = <64>;

@@ -883,8 +907,9 @@ cpu24: cpu@24 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <24>;
  			i-cache-block-size = <64>;

@@ -909,8 +934,9 @@ cpu25: cpu@25 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <25>;
  			i-cache-block-size = <64>;

@@ -935,8 +961,9 @@ cpu26: cpu@26 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <26>;
  			i-cache-block-size = <64>;

@@ -961,8 +988,9 @@ cpu27: cpu@27 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <27>;
  			i-cache-block-size = <64>;

@@ -987,8 +1015,9 @@ cpu28: cpu@28 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <28>;
  			i-cache-block-size = <64>;

@@ -1013,8 +1042,9 @@ cpu29: cpu@29 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <29>;
  			i-cache-block-size = <64>;

@@ -1039,8 +1069,9 @@ cpu30: cpu@30 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <30>;
  			i-cache-block-size = <64>;

@@ -1065,8 +1096,9 @@ cpu31: cpu@31 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <31>;
  			i-cache-block-size = <64>;

@@ -1091,8 +1123,9 @@ cpu32: cpu@32 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <32>;
  			i-cache-block-size = <64>;

@@ -1117,8 +1150,9 @@ cpu33: cpu@33 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <33>;
  			i-cache-block-size = <64>;

@@ -1143,8 +1177,9 @@ cpu34: cpu@34 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <34>;
  			i-cache-block-size = <64>;

@@ -1169,8 +1204,9 @@ cpu35: cpu@35 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <35>;
  			i-cache-block-size = <64>;

@@ -1195,8 +1231,9 @@ cpu36: cpu@36 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <36>;
  			i-cache-block-size = <64>;

@@ -1221,8 +1258,9 @@ cpu37: cpu@37 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <37>;
  			i-cache-block-size = <64>;

@@ -1247,8 +1285,9 @@ cpu38: cpu@38 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <38>;
  			i-cache-block-size = <64>;

@@ -1273,8 +1312,9 @@ cpu39: cpu@39 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <39>;
  			i-cache-block-size = <64>;

@@ -1299,8 +1339,9 @@ cpu40: cpu@40 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <40>;
  			i-cache-block-size = <64>;

@@ -1325,8 +1366,9 @@ cpu41: cpu@41 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <41>;
  			i-cache-block-size = <64>;

@@ -1351,8 +1393,9 @@ cpu42: cpu@42 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <42>;
  			i-cache-block-size = <64>;

@@ -1377,8 +1420,9 @@ cpu43: cpu@43 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <43>;
  			i-cache-block-size = <64>;

@@ -1403,8 +1447,9 @@ cpu44: cpu@44 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <44>;
  			i-cache-block-size = <64>;

@@ -1429,8 +1474,9 @@ cpu45: cpu@45 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <45>;
  			i-cache-block-size = <64>;

@@ -1455,8 +1501,9 @@ cpu46: cpu@46 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <46>;
  			i-cache-block-size = <64>;

@@ -1481,8 +1528,9 @@ cpu47: cpu@47 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <47>;
  			i-cache-block-size = <64>;

@@ -1507,8 +1555,9 @@ cpu48: cpu@48 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <48>;
  			i-cache-block-size = <64>;

@@ -1533,8 +1582,9 @@ cpu49: cpu@49 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <49>;
  			i-cache-block-size = <64>;

@@ -1559,8 +1609,9 @@ cpu50: cpu@50 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <50>;
  			i-cache-block-size = <64>;

@@ -1585,8 +1636,9 @@ cpu51: cpu@51 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <51>;
  			i-cache-block-size = <64>;

@@ -1611,8 +1663,9 @@ cpu52: cpu@52 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <52>;
  			i-cache-block-size = <64>;

@@ -1637,8 +1690,9 @@ cpu53: cpu@53 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <53>;
  			i-cache-block-size = <64>;

@@ -1663,8 +1717,9 @@ cpu54: cpu@54 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <54>;
  			i-cache-block-size = <64>;

@@ -1689,8 +1744,9 @@ cpu55: cpu@55 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <55>;
  			i-cache-block-size = <64>;

@@ -1715,8 +1771,9 @@ cpu56: cpu@56 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <56>;
  			i-cache-block-size = <64>;

@@ -1741,8 +1798,9 @@ cpu57: cpu@57 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <57>;
  			i-cache-block-size = <64>;

@@ -1767,8 +1825,9 @@ cpu58: cpu@58 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <58>;
  			i-cache-block-size = <64>;

@@ -1793,8 +1852,9 @@ cpu59: cpu@59 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <59>;
  			i-cache-block-size = <64>;

@@ -1819,8 +1879,9 @@ cpu60: cpu@60 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <60>;
  			i-cache-block-size = <64>;

@@ -1845,8 +1906,9 @@ cpu61: cpu@61 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <61>;
  			i-cache-block-size = <64>;

@@ -1871,8 +1933,9 @@ cpu62: cpu@62 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <62>;
  			i-cache-block-size = <64>;

@@ -1897,8 +1960,9 @@ cpu63: cpu@63 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <63>;
  			i-cache-block-size = <64>;
Reviewed-by on v3 2/3
#6 lore raw

Re: [PATCH v3 2/3] riscv: dts: sophgo: add ziccrse for sg2042

In reply to Han Gao
Quoted 6 lines · Han Gao

sg2042 support Ziccrse ISA extension [1].

Link https://lore.kernel.org/all/[email protected]/ [1] open here
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
Reviewed-by Nutty Liu<[email protected]>

Thanks,
Nutty

Quoted 776 lines
---
  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 320 ++++++++++++--------
  1 file changed, 192 insertions(+), 128 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +192 -128
index dcc984965b6b..f483f62ab0c4 100644
@@ -259,8 +259,9 @@ cpu0: cpu@0 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <0>;
  			i-cache-block-size = <64>;

@@ -285,8 +286,9 @@ cpu1: cpu@1 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <1>;
  			i-cache-block-size = <64>;

@@ -311,8 +313,9 @@ cpu2: cpu@2 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <2>;
  			i-cache-block-size = <64>;

@@ -337,8 +340,9 @@ cpu3: cpu@3 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <3>;
  			i-cache-block-size = <64>;

@@ -363,8 +367,9 @@ cpu4: cpu@4 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <4>;
  			i-cache-block-size = <64>;

@@ -389,8 +394,9 @@ cpu5: cpu@5 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <5>;
  			i-cache-block-size = <64>;

@@ -415,8 +421,9 @@ cpu6: cpu@6 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <6>;
  			i-cache-block-size = <64>;

@@ -441,8 +448,9 @@ cpu7: cpu@7 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <7>;
  			i-cache-block-size = <64>;

@@ -467,8 +475,9 @@ cpu8: cpu@8 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <8>;
  			i-cache-block-size = <64>;

@@ -493,8 +502,9 @@ cpu9: cpu@9 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <9>;
  			i-cache-block-size = <64>;

@@ -519,8 +529,9 @@ cpu10: cpu@10 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <10>;
  			i-cache-block-size = <64>;

@@ -545,8 +556,9 @@ cpu11: cpu@11 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <11>;
  			i-cache-block-size = <64>;

@@ -571,8 +583,9 @@ cpu12: cpu@12 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <12>;
  			i-cache-block-size = <64>;

@@ -597,8 +610,9 @@ cpu13: cpu@13 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <13>;
  			i-cache-block-size = <64>;

@@ -623,8 +637,9 @@ cpu14: cpu@14 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <14>;
  			i-cache-block-size = <64>;

@@ -649,8 +664,9 @@ cpu15: cpu@15 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <15>;
  			i-cache-block-size = <64>;

@@ -675,8 +691,9 @@ cpu16: cpu@16 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <16>;
  			i-cache-block-size = <64>;

@@ -701,8 +718,9 @@ cpu17: cpu@17 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <17>;
  			i-cache-block-size = <64>;

@@ -727,8 +745,9 @@ cpu18: cpu@18 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <18>;
  			i-cache-block-size = <64>;

@@ -753,8 +772,9 @@ cpu19: cpu@19 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <19>;
  			i-cache-block-size = <64>;

@@ -779,8 +799,9 @@ cpu20: cpu@20 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <20>;
  			i-cache-block-size = <64>;

@@ -805,8 +826,9 @@ cpu21: cpu@21 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <21>;
  			i-cache-block-size = <64>;

@@ -831,8 +853,9 @@ cpu22: cpu@22 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <22>;
  			i-cache-block-size = <64>;

@@ -857,8 +880,9 @@ cpu23: cpu@23 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <23>;
  			i-cache-block-size = <64>;

@@ -883,8 +907,9 @@ cpu24: cpu@24 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <24>;
  			i-cache-block-size = <64>;

@@ -909,8 +934,9 @@ cpu25: cpu@25 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <25>;
  			i-cache-block-size = <64>;

@@ -935,8 +961,9 @@ cpu26: cpu@26 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <26>;
  			i-cache-block-size = <64>;

@@ -961,8 +988,9 @@ cpu27: cpu@27 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <27>;
  			i-cache-block-size = <64>;

@@ -987,8 +1015,9 @@ cpu28: cpu@28 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <28>;
  			i-cache-block-size = <64>;

@@ -1013,8 +1042,9 @@ cpu29: cpu@29 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <29>;
  			i-cache-block-size = <64>;

@@ -1039,8 +1069,9 @@ cpu30: cpu@30 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <30>;
  			i-cache-block-size = <64>;

@@ -1065,8 +1096,9 @@ cpu31: cpu@31 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <31>;
  			i-cache-block-size = <64>;

@@ -1091,8 +1123,9 @@ cpu32: cpu@32 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <32>;
  			i-cache-block-size = <64>;

@@ -1117,8 +1150,9 @@ cpu33: cpu@33 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <33>;
  			i-cache-block-size = <64>;

@@ -1143,8 +1177,9 @@ cpu34: cpu@34 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <34>;
  			i-cache-block-size = <64>;

@@ -1169,8 +1204,9 @@ cpu35: cpu@35 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <35>;
  			i-cache-block-size = <64>;

@@ -1195,8 +1231,9 @@ cpu36: cpu@36 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <36>;
  			i-cache-block-size = <64>;

@@ -1221,8 +1258,9 @@ cpu37: cpu@37 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <37>;
  			i-cache-block-size = <64>;

@@ -1247,8 +1285,9 @@ cpu38: cpu@38 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <38>;
  			i-cache-block-size = <64>;

@@ -1273,8 +1312,9 @@ cpu39: cpu@39 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <39>;
  			i-cache-block-size = <64>;

@@ -1299,8 +1339,9 @@ cpu40: cpu@40 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <40>;
  			i-cache-block-size = <64>;

@@ -1325,8 +1366,9 @@ cpu41: cpu@41 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <41>;
  			i-cache-block-size = <64>;

@@ -1351,8 +1393,9 @@ cpu42: cpu@42 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <42>;
  			i-cache-block-size = <64>;

@@ -1377,8 +1420,9 @@ cpu43: cpu@43 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <43>;
  			i-cache-block-size = <64>;

@@ -1403,8 +1447,9 @@ cpu44: cpu@44 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <44>;
  			i-cache-block-size = <64>;

@@ -1429,8 +1474,9 @@ cpu45: cpu@45 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <45>;
  			i-cache-block-size = <64>;

@@ -1455,8 +1501,9 @@ cpu46: cpu@46 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <46>;
  			i-cache-block-size = <64>;

@@ -1481,8 +1528,9 @@ cpu47: cpu@47 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <47>;
  			i-cache-block-size = <64>;

@@ -1507,8 +1555,9 @@ cpu48: cpu@48 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <48>;
  			i-cache-block-size = <64>;

@@ -1533,8 +1582,9 @@ cpu49: cpu@49 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <49>;
  			i-cache-block-size = <64>;

@@ -1559,8 +1609,9 @@ cpu50: cpu@50 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <50>;
  			i-cache-block-size = <64>;

@@ -1585,8 +1636,9 @@ cpu51: cpu@51 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <51>;
  			i-cache-block-size = <64>;

@@ -1611,8 +1663,9 @@ cpu52: cpu@52 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <52>;
  			i-cache-block-size = <64>;

@@ -1637,8 +1690,9 @@ cpu53: cpu@53 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <53>;
  			i-cache-block-size = <64>;

@@ -1663,8 +1717,9 @@ cpu54: cpu@54 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <54>;
  			i-cache-block-size = <64>;

@@ -1689,8 +1744,9 @@ cpu55: cpu@55 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <55>;
  			i-cache-block-size = <64>;

@@ -1715,8 +1771,9 @@ cpu56: cpu@56 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <56>;
  			i-cache-block-size = <64>;

@@ -1741,8 +1798,9 @@ cpu57: cpu@57 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <57>;
  			i-cache-block-size = <64>;

@@ -1767,8 +1825,9 @@ cpu58: cpu@58 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <58>;
  			i-cache-block-size = <64>;

@@ -1793,8 +1852,9 @@ cpu59: cpu@59 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <59>;
  			i-cache-block-size = <64>;

@@ -1819,8 +1879,9 @@ cpu60: cpu@60 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <60>;
  			i-cache-block-size = <64>;

@@ -1845,8 +1906,9 @@ cpu61: cpu@61 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <61>;
  			i-cache-block-size = <64>;

@@ -1871,8 +1933,9 @@ cpu62: cpu@62 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <62>;
  			i-cache-block-size = <64>;

@@ -1897,8 +1960,9 @@ cpu63: cpu@63 {
  			riscv,isa = "rv64imafdc";
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
-					       "zihpm", "xtheadvector";
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <63>;
  			i-cache-block-size = <64>;
author
#7 lore raw

PATCH v3 3/3 riscv: dts: sophgo: add zfh for sg2042

In reply to Han Gao

sg2042 support Zfh ISA extension [1].

Link https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
---
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
 1 file changed, 64 insertions(+), 64 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +64 -64
index f483f62ab0c4..77ded5304272 100644
@@ -260,7 +260,7 @@ cpu0: cpu@0 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <0>;

@@ -287,7 +287,7 @@ cpu1: cpu@1 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <1>;

@@ -314,7 +314,7 @@ cpu2: cpu@2 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <2>;

@@ -341,7 +341,7 @@ cpu3: cpu@3 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <3>;

@@ -368,7 +368,7 @@ cpu4: cpu@4 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <4>;

@@ -395,7 +395,7 @@ cpu5: cpu@5 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <5>;

@@ -422,7 +422,7 @@ cpu6: cpu@6 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <6>;

@@ -449,7 +449,7 @@ cpu7: cpu@7 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <7>;

@@ -476,7 +476,7 @@ cpu8: cpu@8 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <8>;

@@ -503,7 +503,7 @@ cpu9: cpu@9 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <9>;

@@ -530,7 +530,7 @@ cpu10: cpu@10 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <10>;

@@ -557,7 +557,7 @@ cpu11: cpu@11 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <11>;

@@ -584,7 +584,7 @@ cpu12: cpu@12 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <12>;

@@ -611,7 +611,7 @@ cpu13: cpu@13 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <13>;

@@ -638,7 +638,7 @@ cpu14: cpu@14 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <14>;

@@ -665,7 +665,7 @@ cpu15: cpu@15 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <15>;

@@ -692,7 +692,7 @@ cpu16: cpu@16 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <16>;

@@ -719,7 +719,7 @@ cpu17: cpu@17 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <17>;

@@ -746,7 +746,7 @@ cpu18: cpu@18 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <18>;

@@ -773,7 +773,7 @@ cpu19: cpu@19 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <19>;

@@ -800,7 +800,7 @@ cpu20: cpu@20 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <20>;

@@ -827,7 +827,7 @@ cpu21: cpu@21 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <21>;

@@ -854,7 +854,7 @@ cpu22: cpu@22 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <22>;

@@ -881,7 +881,7 @@ cpu23: cpu@23 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <23>;

@@ -908,7 +908,7 @@ cpu24: cpu@24 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <24>;

@@ -935,7 +935,7 @@ cpu25: cpu@25 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <25>;

@@ -962,7 +962,7 @@ cpu26: cpu@26 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <26>;

@@ -989,7 +989,7 @@ cpu27: cpu@27 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <27>;

@@ -1016,7 +1016,7 @@ cpu28: cpu@28 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <28>;

@@ -1043,7 +1043,7 @@ cpu29: cpu@29 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <29>;

@@ -1070,7 +1070,7 @@ cpu30: cpu@30 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <30>;

@@ -1097,7 +1097,7 @@ cpu31: cpu@31 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <31>;

@@ -1124,7 +1124,7 @@ cpu32: cpu@32 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <32>;

@@ -1151,7 +1151,7 @@ cpu33: cpu@33 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <33>;

@@ -1178,7 +1178,7 @@ cpu34: cpu@34 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <34>;

@@ -1205,7 +1205,7 @@ cpu35: cpu@35 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <35>;

@@ -1232,7 +1232,7 @@ cpu36: cpu@36 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <36>;

@@ -1259,7 +1259,7 @@ cpu37: cpu@37 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <37>;

@@ -1286,7 +1286,7 @@ cpu38: cpu@38 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <38>;

@@ -1313,7 +1313,7 @@ cpu39: cpu@39 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <39>;

@@ -1340,7 +1340,7 @@ cpu40: cpu@40 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <40>;

@@ -1367,7 +1367,7 @@ cpu41: cpu@41 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <41>;

@@ -1394,7 +1394,7 @@ cpu42: cpu@42 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <42>;

@@ -1421,7 +1421,7 @@ cpu43: cpu@43 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <43>;

@@ -1448,7 +1448,7 @@ cpu44: cpu@44 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <44>;

@@ -1475,7 +1475,7 @@ cpu45: cpu@45 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <45>;

@@ -1502,7 +1502,7 @@ cpu46: cpu@46 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <46>;

@@ -1529,7 +1529,7 @@ cpu47: cpu@47 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <47>;

@@ -1556,7 +1556,7 @@ cpu48: cpu@48 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <48>;

@@ -1583,7 +1583,7 @@ cpu49: cpu@49 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <49>;

@@ -1610,7 +1610,7 @@ cpu50: cpu@50 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <50>;

@@ -1637,7 +1637,7 @@ cpu51: cpu@51 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <51>;

@@ -1664,7 +1664,7 @@ cpu52: cpu@52 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <52>;

@@ -1691,7 +1691,7 @@ cpu53: cpu@53 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <53>;

@@ -1718,7 +1718,7 @@ cpu54: cpu@54 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <54>;

@@ -1745,7 +1745,7 @@ cpu55: cpu@55 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <55>;

@@ -1772,7 +1772,7 @@ cpu56: cpu@56 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <56>;

@@ -1799,7 +1799,7 @@ cpu57: cpu@57 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <57>;

@@ -1826,7 +1826,7 @@ cpu58: cpu@58 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <58>;

@@ -1853,7 +1853,7 @@ cpu59: cpu@59 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <59>;

@@ -1880,7 +1880,7 @@ cpu60: cpu@60 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <60>;

@@ -1907,7 +1907,7 @@ cpu61: cpu@61 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <61>;

@@ -1934,7 +1934,7 @@ cpu62: cpu@62 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <62>;

@@ -1961,7 +1961,7 @@ cpu63: cpu@63 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <63>;
Signature · 1 line
2.47.2
Reviewed-by on v3 3/3
#8 lore raw

Re: [PATCH v3 3/3] riscv: dts: sophgo: add zfh for sg2042

Quoted 6 lines · Han Gao

sg2042 support Zfh ISA extension [1].

Link https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
Reviewed-by Chen Wang <[email protected]>
Quoted 584 lines
---
  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
  1 file changed, 64 insertions(+), 64 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +64 -64
index f483f62ab0c4..77ded5304272 100644
@@ -260,7 +260,7 @@ cpu0: cpu@0 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <0>;

@@ -287,7 +287,7 @@ cpu1: cpu@1 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <1>;

@@ -314,7 +314,7 @@ cpu2: cpu@2 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <2>;

@@ -341,7 +341,7 @@ cpu3: cpu@3 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <3>;

@@ -368,7 +368,7 @@ cpu4: cpu@4 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <4>;

@@ -395,7 +395,7 @@ cpu5: cpu@5 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <5>;

@@ -422,7 +422,7 @@ cpu6: cpu@6 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <6>;

@@ -449,7 +449,7 @@ cpu7: cpu@7 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <7>;

@@ -476,7 +476,7 @@ cpu8: cpu@8 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <8>;

@@ -503,7 +503,7 @@ cpu9: cpu@9 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <9>;

@@ -530,7 +530,7 @@ cpu10: cpu@10 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <10>;

@@ -557,7 +557,7 @@ cpu11: cpu@11 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <11>;

@@ -584,7 +584,7 @@ cpu12: cpu@12 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <12>;

@@ -611,7 +611,7 @@ cpu13: cpu@13 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <13>;

@@ -638,7 +638,7 @@ cpu14: cpu@14 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <14>;

@@ -665,7 +665,7 @@ cpu15: cpu@15 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <15>;

@@ -692,7 +692,7 @@ cpu16: cpu@16 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <16>;

@@ -719,7 +719,7 @@ cpu17: cpu@17 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <17>;

@@ -746,7 +746,7 @@ cpu18: cpu@18 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <18>;

@@ -773,7 +773,7 @@ cpu19: cpu@19 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <19>;

@@ -800,7 +800,7 @@ cpu20: cpu@20 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <20>;

@@ -827,7 +827,7 @@ cpu21: cpu@21 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <21>;

@@ -854,7 +854,7 @@ cpu22: cpu@22 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <22>;

@@ -881,7 +881,7 @@ cpu23: cpu@23 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <23>;

@@ -908,7 +908,7 @@ cpu24: cpu@24 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <24>;

@@ -935,7 +935,7 @@ cpu25: cpu@25 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <25>;

@@ -962,7 +962,7 @@ cpu26: cpu@26 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <26>;

@@ -989,7 +989,7 @@ cpu27: cpu@27 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <27>;

@@ -1016,7 +1016,7 @@ cpu28: cpu@28 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <28>;

@@ -1043,7 +1043,7 @@ cpu29: cpu@29 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <29>;

@@ -1070,7 +1070,7 @@ cpu30: cpu@30 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <30>;

@@ -1097,7 +1097,7 @@ cpu31: cpu@31 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <31>;

@@ -1124,7 +1124,7 @@ cpu32: cpu@32 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <32>;

@@ -1151,7 +1151,7 @@ cpu33: cpu@33 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <33>;

@@ -1178,7 +1178,7 @@ cpu34: cpu@34 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <34>;

@@ -1205,7 +1205,7 @@ cpu35: cpu@35 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <35>;

@@ -1232,7 +1232,7 @@ cpu36: cpu@36 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <36>;

@@ -1259,7 +1259,7 @@ cpu37: cpu@37 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <37>;

@@ -1286,7 +1286,7 @@ cpu38: cpu@38 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <38>;

@@ -1313,7 +1313,7 @@ cpu39: cpu@39 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <39>;

@@ -1340,7 +1340,7 @@ cpu40: cpu@40 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <40>;

@@ -1367,7 +1367,7 @@ cpu41: cpu@41 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <41>;

@@ -1394,7 +1394,7 @@ cpu42: cpu@42 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <42>;

@@ -1421,7 +1421,7 @@ cpu43: cpu@43 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <43>;

@@ -1448,7 +1448,7 @@ cpu44: cpu@44 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <44>;

@@ -1475,7 +1475,7 @@ cpu45: cpu@45 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <45>;

@@ -1502,7 +1502,7 @@ cpu46: cpu@46 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <46>;

@@ -1529,7 +1529,7 @@ cpu47: cpu@47 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <47>;

@@ -1556,7 +1556,7 @@ cpu48: cpu@48 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <48>;

@@ -1583,7 +1583,7 @@ cpu49: cpu@49 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <49>;

@@ -1610,7 +1610,7 @@ cpu50: cpu@50 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <50>;

@@ -1637,7 +1637,7 @@ cpu51: cpu@51 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <51>;

@@ -1664,7 +1664,7 @@ cpu52: cpu@52 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <52>;

@@ -1691,7 +1691,7 @@ cpu53: cpu@53 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <53>;

@@ -1718,7 +1718,7 @@ cpu54: cpu@54 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <54>;

@@ -1745,7 +1745,7 @@ cpu55: cpu@55 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <55>;

@@ -1772,7 +1772,7 @@ cpu56: cpu@56 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <56>;

@@ -1799,7 +1799,7 @@ cpu57: cpu@57 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <57>;

@@ -1826,7 +1826,7 @@ cpu58: cpu@58 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <58>;

@@ -1853,7 +1853,7 @@ cpu59: cpu@59 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <59>;

@@ -1880,7 +1880,7 @@ cpu60: cpu@60 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <60>;

@@ -1907,7 +1907,7 @@ cpu61: cpu@61 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <61>;

@@ -1934,7 +1934,7 @@ cpu62: cpu@62 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <62>;

@@ -1961,7 +1961,7 @@ cpu63: cpu@63 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <63>;
Reviewed-by on v3 3/3
#9 lore raw

Re: [PATCH v3 3/3] riscv: dts: sophgo: add zfh for sg2042

In reply to Han Gao
Quoted 6 lines · Han Gao

sg2042 support Zfh ISA extension [1].

Link https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Signed-off-by Han Gao <[email protected]>
Reviewed-by Inochi Amaoto <[email protected]>
Reviewed-by Nutty Liu<[email protected]>

Thanks,
Nutty

Quoted 584 lines
---
  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
  1 file changed, 64 insertions(+), 64 deletions(-)
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +64 -64
index f483f62ab0c4..77ded5304272 100644
@@ -260,7 +260,7 @@ cpu0: cpu@0 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <0>;

@@ -287,7 +287,7 @@ cpu1: cpu@1 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <1>;

@@ -314,7 +314,7 @@ cpu2: cpu@2 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <2>;

@@ -341,7 +341,7 @@ cpu3: cpu@3 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <3>;

@@ -368,7 +368,7 @@ cpu4: cpu@4 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <4>;

@@ -395,7 +395,7 @@ cpu5: cpu@5 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <5>;

@@ -422,7 +422,7 @@ cpu6: cpu@6 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <6>;

@@ -449,7 +449,7 @@ cpu7: cpu@7 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <7>;

@@ -476,7 +476,7 @@ cpu8: cpu@8 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <8>;

@@ -503,7 +503,7 @@ cpu9: cpu@9 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <9>;

@@ -530,7 +530,7 @@ cpu10: cpu@10 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <10>;

@@ -557,7 +557,7 @@ cpu11: cpu@11 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <11>;

@@ -584,7 +584,7 @@ cpu12: cpu@12 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <12>;

@@ -611,7 +611,7 @@ cpu13: cpu@13 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <13>;

@@ -638,7 +638,7 @@ cpu14: cpu@14 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <14>;

@@ -665,7 +665,7 @@ cpu15: cpu@15 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <15>;

@@ -692,7 +692,7 @@ cpu16: cpu@16 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <16>;

@@ -719,7 +719,7 @@ cpu17: cpu@17 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <17>;

@@ -746,7 +746,7 @@ cpu18: cpu@18 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <18>;

@@ -773,7 +773,7 @@ cpu19: cpu@19 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <19>;

@@ -800,7 +800,7 @@ cpu20: cpu@20 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <20>;

@@ -827,7 +827,7 @@ cpu21: cpu@21 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <21>;

@@ -854,7 +854,7 @@ cpu22: cpu@22 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <22>;

@@ -881,7 +881,7 @@ cpu23: cpu@23 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <23>;

@@ -908,7 +908,7 @@ cpu24: cpu@24 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <24>;

@@ -935,7 +935,7 @@ cpu25: cpu@25 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <25>;

@@ -962,7 +962,7 @@ cpu26: cpu@26 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <26>;

@@ -989,7 +989,7 @@ cpu27: cpu@27 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <27>;

@@ -1016,7 +1016,7 @@ cpu28: cpu@28 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <28>;

@@ -1043,7 +1043,7 @@ cpu29: cpu@29 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <29>;

@@ -1070,7 +1070,7 @@ cpu30: cpu@30 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <30>;

@@ -1097,7 +1097,7 @@ cpu31: cpu@31 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <31>;

@@ -1124,7 +1124,7 @@ cpu32: cpu@32 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <32>;

@@ -1151,7 +1151,7 @@ cpu33: cpu@33 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <33>;

@@ -1178,7 +1178,7 @@ cpu34: cpu@34 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <34>;

@@ -1205,7 +1205,7 @@ cpu35: cpu@35 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <35>;

@@ -1232,7 +1232,7 @@ cpu36: cpu@36 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <36>;

@@ -1259,7 +1259,7 @@ cpu37: cpu@37 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <37>;

@@ -1286,7 +1286,7 @@ cpu38: cpu@38 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <38>;

@@ -1313,7 +1313,7 @@ cpu39: cpu@39 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <39>;

@@ -1340,7 +1340,7 @@ cpu40: cpu@40 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <40>;

@@ -1367,7 +1367,7 @@ cpu41: cpu@41 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <41>;

@@ -1394,7 +1394,7 @@ cpu42: cpu@42 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <42>;

@@ -1421,7 +1421,7 @@ cpu43: cpu@43 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <43>;

@@ -1448,7 +1448,7 @@ cpu44: cpu@44 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <44>;

@@ -1475,7 +1475,7 @@ cpu45: cpu@45 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <45>;

@@ -1502,7 +1502,7 @@ cpu46: cpu@46 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <46>;

@@ -1529,7 +1529,7 @@ cpu47: cpu@47 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <47>;

@@ -1556,7 +1556,7 @@ cpu48: cpu@48 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <48>;

@@ -1583,7 +1583,7 @@ cpu49: cpu@49 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <49>;

@@ -1610,7 +1610,7 @@ cpu50: cpu@50 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <50>;

@@ -1637,7 +1637,7 @@ cpu51: cpu@51 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <51>;

@@ -1664,7 +1664,7 @@ cpu52: cpu@52 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <52>;

@@ -1691,7 +1691,7 @@ cpu53: cpu@53 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <53>;

@@ -1718,7 +1718,7 @@ cpu54: cpu@54 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <54>;

@@ -1745,7 +1745,7 @@ cpu55: cpu@55 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <55>;

@@ -1772,7 +1772,7 @@ cpu56: cpu@56 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <56>;

@@ -1799,7 +1799,7 @@ cpu57: cpu@57 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <57>;

@@ -1826,7 +1826,7 @@ cpu58: cpu@58 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <58>;

@@ -1853,7 +1853,7 @@ cpu59: cpu@59 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <59>;

@@ -1880,7 +1880,7 @@ cpu60: cpu@60 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <60>;

@@ -1907,7 +1907,7 @@ cpu61: cpu@61 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <61>;

@@ -1934,7 +1934,7 @@ cpu62: cpu@62 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <62>;

@@ -1961,7 +1961,7 @@ cpu63: cpu@63 {
  			riscv,isa-base = "rv64i";
  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
  					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
  					       "xtheadvector";
  			thead,vlenb = <16>;
  			reg = <63>;
maintainer Applied
#10 lore raw
In reply to Han Gao
Quoted 5 lines · Han Gao

Add xtheadvector & ziccrse & zfh for sg2042

Thanks,
Han

Applied to for-next, thanks!

[1/3] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree

      https://github.com/sophgo/linux/commit/d82362d92328c5391312df3a948077f5d651b598
[2/3] riscv: dts: sophgo: add ziccrse for sg2042
      https://github.com/sophgo/linux/commit/df5b30b7feef4a643e36fac74fa0e45c1b9f105a
[3/3] riscv: dts: sophgo: add zfh for sg2042
      https://github.com/sophgo/linux/commit/3eefd8e961cea639370df96b6553a52f638e02e8

Thanks,
Inochi