Support ROHM BD79112 ADC

PATCH Superseded Matti Vaittinen 6 participants 16 messages Sep 5, 2025 – Sep 9, 2025

Subsystems (4)

Device tree bindings GPIO IIO ROHM BD791xx ADC / GPO IC

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Matti Vaittinen

author maintainer

2025-09-05 06:41 UTC #0 lore raw

v3 cover Support ROHM BD79112 ADC

Support ROHM BD79112 ADC/GPIO

The ROHM BD79112 is a 12-bit, 32 channel SAR ADC / GPIO IC. Or, a "Signal Monitor Hub IC" as data-sheet describes it.

Data sheet states the maximum sampling rate to be 1 MSPS, but achieving this would probably require the SPI and samples to be processed by something else but the CPU running Linux. This could work with the "SPI offloading" which has recently landed upstream - but I have no HW to test this so nothing fancy is implemented here. It's still worth mentioning if someone needs the speed and wants to try implementing it :)

The SPI protocol is slightly peculiar. Accesses are done in 16-bit sequences, separated by releasing and re-aquiring the chip-select.

Register write takes 1 such sequence. The 8-bit register data to write, is stored in the last 8 bits. The high 8 bits contain register address and an I/O-bit which needs to be set for register accesses.

Register read consists of two 16-bit sequences (separated by chip-select). First sequence has again the register address and an IO bit in the high byte. Additionally, reads must have a 'read bit' set. The last 8 bits must be zero. The register data will be carried in the last 8 bits of the next 16-bit sequence while high bits in reply are zero.

ADC data reading is similar to register reading except:
- No R/W bit or I/O bit should be set.
- Register address is replaced by channel number (0 - 31).
- Reply data is carried in the 12 low bits (instead of 8 bits) of the reply sequence.

The protocol is implemented using custom regmap read() and write() operations.

Other than that, pretty standard device and driver.

Revision history:
v2 => v3:
- Mostly cosmetic changes to the driver
- dt-bindings and MAINTAINERS unchanged

v1 => v2:
- Plenty of fixes to the driver (thanks to reviewers, Andy and David)
- Add gpio-controller information to the device-tree bindings

See individual patches for more accurate changelog

---

Matti Vaittinen (3):
dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO
iio: adc: Support ROHM BD79112 ADC/GPIO
MAINTAINERS: Support ROHM BD79112 ADC

 .../bindings/iio/adc/rohm,bd79112.yaml        | 116 ++++
 MAINTAINERS                                   |   3 +-
 drivers/iio/adc/Kconfig                       |  10 +
 drivers/iio/adc/Makefile                      |   1 +
 drivers/iio/adc/rohm-bd79112.c                | 547 ++++++++++++++++++
 5 files changed, 676 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml
 create mode 100644 drivers/iio/adc/rohm-bd79112.c

base-commit: d1487b0b78720b86ec2a2ac7acc683ec90627e5b

Signature · 1 line

2.51.0

Matti Vaittinen

author maintainer

2025-09-05 06:42 UTC #1 lore raw

PATCH v3 1/3 dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO

The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.

The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.

Add a device tree binding document for the ROHM BD79112.

Signed-off-by Matti Vaittinen <[email protected]>

Acked-by Conor Dooley <[email protected]>

---
Revision history:
v1 => v2:
- BD79112 can act as a GPIO controller.

---
 .../bindings/iio/adc/rohm,bd79112.yaml        | 116 ++++++++++++++++++
 1 file changed, 116 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml

Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file +116 -0

new file mode 100644
index 000000000000..8aeac5b60880
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/rohm,bd79112.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD79112 ADC/GPO
+
+maintainers:
+  - Matti Vaittinen <[email protected]>
+
+description: |
+  The ROHM BD79112 is a 12-bit, 32-channel, SAR ADC. ADC input pins can be
+  also configured as general purpose inputs/outputs. SPI should use MODE 3.
+
+properties:
+  compatible:
+    const: rohm,bd79112
+
+  reg:
+    maxItems: 1
+
+  spi-cpha: true
+  spi-cpol: true
+
+  gpio-controller: true
+  "#gpio-cells":
+    const: 2
+
+  vdd-supply: true
+
+  iovdd-supply: true
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^channel@([0-9]|[12][0-9]|3[01])$":
+    type: object
+    $ref: /schemas/iio/adc/adc.yaml#
+    description: Represents ADC channel. Omitted channels' inputs are GPIOs.
+
+    properties:
+      reg:
+        description: AIN pin number
+        minimum: 0
+        maximum: 31
+
+    required:
+      - reg
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - iovdd-supply
+  - vdd-supply
+  - spi-cpha
+  - spi-cpol
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        adc: adc@0 {
+            compatible = "rohm,bd79112";
+            reg = <0x0>;
+
+            spi-cpha;
+            spi-cpol;
+
+            vdd-supply = <&dummyreg>;
+            iovdd-supply = <&dummyreg>;
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            gpio-controller;
+            #gpio-cells = <2>;
+
+            channel@0 {
+                reg = <0>;
+            };
+            channel@1 {
+                reg = <1>;
+            };
+            channel@2 {
+                reg = <2>;
+            };
+            channel@3 {
+                reg = <3>;
+            };
+            channel@4 {
+                reg = <4>;
+            };
+            channel@5 {
+                reg = <5>;
+            };
+            channel@6 {
+                reg = <6>;
+            };
+            channel@16 {
+                reg = <16>;
+            };
+            channel@20 {
+                reg = <20>;
+            };
+        };
+    };

Signature · 1 line

2.51.0

Linus Walleij

Reviewed-by on v3 1/3

2025-09-05 08:10 UTC #2 lore raw

Re: [PATCH v3 1/3] dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO

Quoted 11 lines · Matti Vaittinen

The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.
Add a device tree binding document for the ROHM BD79112.
Signed-off-by Matti Vaittinen <[email protected]>
Acked-by Conor Dooley <[email protected]>

Looking good!

Reviewed-by Linus Walleij <[email protected]>

Yours,
Linus Walleij

Jonathan Cameron

maintainer

2025-09-07 11:19 UTC #3 lore raw

Re: [PATCH v3 1/3] dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO

In reply to Matti Vaittinen

Quoted 11 lines · On Fri, 5 Sep 2025 09:42:18 +0300 Matti Vaittinen <[email protected]>…

The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.
Add a device tree binding document for the ROHM BD79112.
Signed-off-by Matti Vaittinen <[email protected]>
Acked-by Conor Dooley <[email protected]>

Trivial comment below. If everything else is good on this version it isn't worth a respin.

Quoted 22 lines

Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file +22 -0

+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        adc: adc@0 {
+            compatible = "rohm,bd79112";
+            reg = <0x0>;
+
+            spi-cpha;
+            spi-cpol;
+
+            vdd-supply = <&dummyreg>;
+            iovdd-supply = <&dummyreg>;
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            gpio-controller;
+            #gpio-cells = <2>;
+
+            channel@0 {

Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml line 98

Quoted 10 lines

Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file +10 -0

+                reg = <0>;
+            };
+            channel@1 {
+                reg = <1>;
+            };
+            channel@2 {
+                reg = <2>;
+            };
+            channel@3 {
+                reg = <3>;

Trivial point but I get bored scrolling.
Would a smaller set of channels allow you to provide same level of testing / documentation?

Quoted 18 lines

Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file +18 -0

+            };
+            channel@4 {
+                reg = <4>;
+            };
+            channel@5 {
+                reg = <5>;
+            };
+            channel@6 {
+                reg = <6>;
+            };
+            channel@16 {
+                reg = <16>;
+            };
+            channel@20 {
+                reg = <20>;
+            };
+        };
+    };

Matti Vaittinen

author maintainer

2025-09-07 12:37 UTC #4 lore raw

Re: [PATCH v3 1/3] dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO

Quoted 45 lines · Jonathan Cameron

Quoted 11 lines · On Fri, 5 Sep 2025 09:42:18 +0300 Matti Vaittinen <[email protected]>…
The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.
Add a device tree binding document for the ROHM BD79112.
Signed-off-by Matti Vaittinen <[email protected]>
Acked-by Conor Dooley <[email protected]>
Trivial comment below. If everything else is good on this version it isn't worth a respin.
Quoted 27 lines
Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file +27 -0
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        adc: adc@0 {
+            compatible = "rohm,bd79112";
+            reg = <0x0>;
+
+            spi-cpha;
+            spi-cpol;
+
+            vdd-supply = <&dummyreg>;
+            iovdd-supply = <&dummyreg>;
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            gpio-controller;
+            #gpio-cells = <2>;
+
+            channel@0 {
+                reg = <0>;
+            };
+            channel@1 {
+                reg = <1>;
+            };

Quoted 8 lines

Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml line 98
Quoted 5 lines
Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file +5 -0
+            channel@2 {
+                reg = <2>;
+            };
+            channel@3 {
+                reg = <3>;
Trivial point but I get bored scrolling.
Would a smaller set of channels allow you to provide same level of testing / documentation?

I suppose yes. Trimming this to maybe 3 channels would be just fine. I'll re-spin the series anyways so I'll crop this too.

Yours,
-- Matti

Matti Vaittinen

author maintainer

2025-09-05 06:42 UTC #5 lore raw

PATCH v3 2/3 iio: adc: Support ROHM BD79112 ADC/GPIO

In reply to Matti Vaittinen

The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.

The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.

The IC does also support CRC but it is not implemented in the driver.

Signed-off-by Matti Vaittinen <[email protected]>

---
Revision history:
v2 => v3: (mainly based on review by Andy, thanks!)
- fix broken indentiation
- re-order includes
- drop useless < 0 check for an unsigned offset
- use gc->ngpios instead of hard coded pincount in for_each_set_clump8()
- drop useless check for zero mask inside for_each_set_clump8() body
- reorder return value checks for the devm_iio_adc_device_alloc_chaninfo_se() as suggested by Andy. (Well, I am not 100% happy with it as it results an extra check in the hopefully most common 'success' -case. But yeah, probe is not exactly a fast path).

v1 => v2 (mainly based on reviews by Andy and David, thanks!)
- Fix Kconfig dependency to REGMAP_SPI instead of REGMAP_I2C
- Add a few header includes
- Drop unnecessary alignments
- plenty of styling
- use for_each_set_clump8 instead of open-coding it
- change order of direction setting writes to avoid receiving 'event' when direction is changed from input to output.
- fix data-sheet names and assigning of them to iio_dev

---
 drivers/iio/adc/Kconfig        |  10 +
 drivers/iio/adc/Makefile       |   1 +
 drivers/iio/adc/rohm-bd79112.c | 547 +++++++++++++++++++++++++++++++++
 3 files changed, 558 insertions(+)
 create mode 100644 drivers/iio/adc/rohm-bd79112.c

drivers/iio/adc/Kconfig +10 -0

index e3d3826c3357..64ce1eda78c4 100644
@@ -1309,6 +1309,16 @@ config RN5T618_ADC
 	  This driver can also be built as a module. If so, the module
 	  will be called rn5t618-adc.
 
+config ROHM_BD79112
+	tristate "Rohm BD79112 ADC driver"
+	depends on I2C && GPIOLIB
+	select REGMAP_SPI
+	select IIO_ADC_HELPER
+	help
+	  Say yes here to build support for the ROHM BD79112 ADC. The
+	  ROHM BD79112 is a 12-bit, 32-channel, SAR ADC, which analog
+	  inputs can also be used for GPIO.
+
 config ROHM_BD79124
 	tristate "Rohm BD79124 ADC driver"
 	depends on I2C

drivers/iio/adc/Makefile +1 -0

index 89d72bf9ce70..34b40c34cf71 100644
@@ -117,6 +117,7 @@ obj-$(CONFIG_QCOM_VADC_COMMON) += qcom-vadc-common.o
 obj-$(CONFIG_RCAR_GYRO_ADC) += rcar-gyroadc.o
 obj-$(CONFIG_RICHTEK_RTQ6056) += rtq6056.o
 obj-$(CONFIG_RN5T618_ADC) += rn5t618-adc.o
+obj-$(CONFIG_ROHM_BD79112) += rohm-bd79112.o
 obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124.o
 obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
 obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o

drivers/iio/adc/rohm-bd79112.c new file +547 -0

547 lines not on this page · raw message

Signature · 1 line

2.51.0

Andy Shevchenko

2025-09-05 06:55 UTC #6 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

Quoted 9 lines · Matti Vaittinen

The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.
The IC does also support CRC but it is not implemented in the driver.

...

drivers/iio/adc/Kconfig config RN5T618_ADC · line 1314

Quoted 3 lines

drivers/iio/adc/Kconfig +3 -0

+config ROHM_BD79112
+       tristate "Rohm BD79112 ADC driver"
+       depends on I2C && GPIOLIB

Still I2C?

drivers/iio/adc/Kconfig config RN5T618_ADC · line 1319

Quoted 5 lines

drivers/iio/adc/Kconfig +5 -0

+       select REGMAP_SPI
+       select IIO_ADC_HELPER
+       help
+         Say yes here to build support for the ROHM BD79112 ADC. The
+         ROHM BD79112 is a 12-bit, 32-channel, SAR ADC, which analog

which --> where

Quoted 1 line

+ inputs can also be used for GPIO.

...

Quoted 16 lines

+/*
+ * The data-sheet explains register I/O communication as follows:
+ *
+ * Read, two 16-bit sequences separated by CSB:
+ * MOSI:
+ * SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 9 .. 16 |
+ * data:| 0 | 0 |IOSET| RW (1) | ADDR | 8'b0 |
+ *
+ * MISO:
+ * SCK: | 1 .. 8 | 9 .. 16 |
+ * data:| 8'b0 | data |
+ *
+ * Note, CSB is shown to be released between writing the address (MOSI) and
+ * reading the register data (MISO).
+ *
+ * Write, single 16-bit sequence:

Quoted 8 lines

+ * MOSI:
+ * SCK: | 1 | 2 | 3 | 4 | 5 .. 8 |
+ * data:| 0 | 0 |IOSET| RW(0) | ADDR |
+ *
+ * MISO:
+ * SCK: | 1 .. 8 |
+ * data:| data |
+ */

What I meant in previous reviews is that the | are not aligned (in the same columns). Is it on purpose? If so, I can't read that as I don't understand the meaning of | in each case. For example, the data starts with 0, followed by 0, and the latter one is when SCL is #1? Okay, but how to read IOSET that overlaps 2 SCK cycles and is unaligned with times... I'm really quite confused by these charts.

...

drivers/iio/adc/rohm-bd79112.c line 271

Quoted 3 lines

drivers/iio/adc/rohm-bd79112.c new file +3 -0

+        * Ouch. Seems the pin is ADC input - shouldn't happen as changing mux
+        * at runtime is not supported and non GPIO pins should be invalidated
+        * by the valid_mask at probe. Maybe someone wrote register bypassing

wrote a

Quoted 1 line

+ * the driver?

Signature · 2 lines

With Best Regards,
Andy Shevchenko

Matti Vaittinen

author maintainer

2025-09-05 07:10 UTC #7 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

Quoted 11 lines · Andy Shevchenko

Quoted 9 lines · Matti Vaittinen
The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.
The IC does also support CRC but it is not implemented in the driver.

Quoted 7 lines

...
drivers/iio/adc/Kconfig config RN5T618_ADC · line 1314
Quoted 3 lines
drivers/iio/adc/Kconfig +3 -0
+config ROHM_BD79112
+       tristate "Rohm BD79112 ADC driver"
+       depends on I2C && GPIOLIB
Still I2C?

Thanks :) I didn't spot this @_@. I just switched the REGMAP_I2C to REGMAP_SPI. Will fix.

Quoted 8 lines

drivers/iio/adc/Kconfig config RN5T618_ADC · line 1319
Quoted 6 lines
drivers/iio/adc/Kconfig +5 -0
+       select REGMAP_SPI
+       select IIO_ADC_HELPER
+       help
+         Say yes here to build support for the ROHM BD79112 ADC. The
+         ROHM BD79112 is a 12-bit, 32-channel, SAR ADC, which analog
which --> where

I thought which (as a genetive case) would work here just fine?

Quoted 30 lines

Quoted 2 lines
+ inputs can also be used for GPIO.
...
Quoted 16 lines
+/*
+ * The data-sheet explains register I/O communication as follows:
+ *
+ * Read, two 16-bit sequences separated by CSB:
+ * MOSI:
+ * SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 9 .. 16 |
+ * data:| 0 | 0 |IOSET| RW (1) | ADDR | 8'b0 |
+ *
+ * MISO:
+ * SCK: | 1 .. 8 | 9 .. 16 |
+ * data:| 8'b0 | data |
+ *
+ * Note, CSB is shown to be released between writing the address (MOSI) and
+ * reading the register data (MISO).
+ *
+ * Write, single 16-bit sequence:
Quoted 8 lines
+ * MOSI:
+ * SCK: | 1 | 2 | 3 | 4 | 5 .. 8 |
+ * data:| 0 | 0 |IOSET| RW(0) | ADDR |
+ *
+ * MISO:
+ * SCK: | 1 .. 8 |
+ * data:| data |
+ */

Quoted 6 lines

What I meant in previous reviews is that the | are not aligned (in the same columns). Is it on purpose? If so, I can't read that as I don't understand the meaning of | in each case. For example, the data starts with 0, followed by 0, and the latter one is when SCL is #1? Okay, but how to read IOSET that overlaps 2 SCK cycles and is unaligned with times... I'm really quite confused by these charts.

Ah. I think I now know what you mean. Whitespaces are hard :) I see I have '\t' between the SCK: and first |.

Quoted 1 line

Quoted 1 line
+ * SCK: /* '\t' here */ | 1 | 2 | 3 | 4 | 5 .. 8 |

It works perfectly on my editor, which has tab width 8. Thus, all the '|' on SCK and data rows are perfectly aligned for me. My original thought has been to align the first '|' on all rows by tab, but since the " * data:" is already 8 chars I didn't add a tab for this row...

I now realize this will not work if tabs behave different from my setup. I will do replacing the '\t' with ' '. Does this make it better for your editor or do you see some other problem besides that?

Thanks for the patience explaining it.

Quoted 10 lines

...
drivers/iio/adc/rohm-bd79112.c line 271
Quoted 3 lines
drivers/iio/adc/rohm-bd79112.c new file +3 -0
+        * Ouch. Seems the pin is ADC input - shouldn't happen as changing mux
+        * at runtime is not supported and non GPIO pins should be invalidated
+        * by the valid_mask at probe. Maybe someone wrote register bypassing
wrote a
Quoted 1 line
+ * the driver?

Yours,
-- Matti

Andy Shevchenko

2025-09-05 12:53 UTC #8 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

Quoted 2 lines · Matti Vaittinen

Quoted 1 line · Andy Shevchenko
On Fri, Sep 5, 2025 at 9:42 AM Matti Vaittinen <[email protected]> wrote:

...

Quoted 36 lines

Quoted 25 lines
Quoted 16 lines
+/*
+ * The data-sheet explains register I/O communication as follows:
+ *
+ * Read, two 16-bit sequences separated by CSB:
+ * MOSI:
+ * SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 9 .. 16 |
+ * data:| 0 | 0 |IOSET| RW (1) | ADDR | 8'b0 |
+ *
+ * MISO:
+ * SCK: | 1 .. 8 | 9 .. 16 |
+ * data:| 8'b0 | data |
+ *
+ * Note, CSB is shown to be released between writing the address (MOSI) and
+ * reading the register data (MISO).
+ *
+ * Write, single 16-bit sequence:
Quoted 8 lines
+ * MOSI:
+ * SCK: | 1 | 2 | 3 | 4 | 5 .. 8 |
+ * data:| 0 | 0 |IOSET| RW(0) | ADDR |
+ *
+ * MISO:
+ * SCK: | 1 .. 8 |
+ * data:| data |
+ */
Quoted 6 lines
What I meant in previous reviews is that the | are not aligned (in the same columns). Is it on purpose? If so, I can't read that as I don't understand the meaning of | in each case. For example, the data starts with 0, followed by 0, and the latter one is when SCL is #1? Okay, but how to read IOSET that overlaps 2 SCK cycles and is unaligned with times... I'm really quite confused by these charts.
Ah. I think I now know what you mean. Whitespaces are hard :) I see I have '\t' between the SCK: and first |.
Quoted 1 line
Quoted 1 line
+ * SCK: /* '\t' here */ | 1 | 2 | 3 | 4 | 5 .. 8 |

Quoted 8 lines

It works perfectly on my editor, which has tab width 8. Thus, all the '|' on SCK and data rows are perfectly aligned for me. My original thought has been to align the first '|' on all rows by tab, but since the " * data:" is already 8 chars I didn't add a tab for this row...
I now realize this will not work if tabs behave different from my setup. I will do replacing the '\t' with ' '. Does this make it better for your editor or do you see some other problem besides that?

I can't answer before seeing. Can you reply with what you mean?

Quoted 1 line

Thanks for the patience explaining it.

You're welcome!

Signature · 2 lines

With Best Regards,
Andy Shevchenko

Jonathan Cameron

maintainer

2025-09-07 11:33 UTC #9 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

In reply to Matti Vaittinen

Quoted 30 lines · On Fri, 5 Sep 2025 10:10:55 +0300 Matti Vaittinen <[email protected]>…

Quoted 11 lines · Andy Shevchenko
Quoted 9 lines · Matti Vaittinen
The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.
The IC does also support CRC but it is not implemented in the driver.
Quoted 7 lines
...
drivers/iio/adc/Kconfig config RN5T618_ADC · line 1314
Quoted 3 lines
drivers/iio/adc/Kconfig +3 -0
+config ROHM_BD79112
+       tristate "Rohm BD79112 ADC driver"
+       depends on I2C && GPIOLIB  
Still I2C?
Thanks :) I didn't spot this @_@. I just switched the REGMAP_I2C to REGMAP_SPI. Will fix.
Quoted 7 lines
Quoted 6 lines
drivers/iio/adc/Kconfig +5 -0
+       select REGMAP_SPI
+       select IIO_ADC_HELPER
+       help
+         Say yes here to build support for the ROHM BD79112 ADC. The
+         ROHM BD79112 is a 12-bit, 32-channel, SAR ADC, which analog  

Quoted 3 lines

Quoted 1 line
which --> where
I thought which (as a genetive case) would work here just fine?

If you had 'on which' I think it would be fine.
With just 'which' it doesn't work. I'm too lazy to figure out exactly why though :(

I'd probably make it a separate sentence though. Analog inputs can also be used for GPIO.

Jonathan Cameron

maintainer

2025-09-07 11:42 UTC #10 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

In reply to Matti Vaittinen

Quoted 10 lines · On Fri, 5 Sep 2025 09:42:31 +0300 Matti Vaittinen <[email protected]>…

The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported.
The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS.
The IC does also support CRC but it is not implemented in the driver.
Signed-off-by Matti Vaittinen <[email protected]>

Hi Matti,

Just one trivial additional comment from me.

Jonathan

Quoted 13 lines

drivers/iio/adc/rohm-bd79112.c new file +3 -0

new file mode 100644
index 000000000000..8acd1e5f105d
 
 
 
 
 
+
+/* ADC channels as named in the data-sheet */
+static const char * const bd79112_chan_names[] = {

drivers/iio/adc/rohm-bd79112.c line 471

Quoted 10 lines

drivers/iio/adc/rohm-bd79112.c new file +9 -0

+	"AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", "AGIO4A",	/* 0 - 4 */
+	"AGIO5A", "AGIO6A", "AGIO7A", "AGIO8A", "AGIO9A",	/* 5 - 9 */
+	"AGIO10A", "AGIO11A", "AGIO12A", "AGIO13A", "AGIO14A",	/* 10 - 14 */
+	"AGIO15A", "AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B",	/* 15 - 19 */
+	"AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B", "AGIO8B",	/* 20 - 24 */
+	"AGIO9B", "AGIO10B", "AGIO11B", "AGIO12B", "AGIO13B",	/* 25 - 29 */
+	"AGIO14B", "AGIO15B",					/* 30 - 31 */
+};
 
+	/* Let's assign data-sheet names to channels */

Not seeing any value in this comment given the code that follows. Probably drop it

Quoted 5 lines

drivers/iio/adc/rohm-bd79112.c new file +5 -0

+	for (i = 0; i < iio_dev->num_channels; i++) {
+		unsigned int ch = cs[i].channel;
+
+		cs[i].datasheet_name = bd79112_chan_names[ch];
+	}

Andy Shevchenko

2025-09-07 20:56 UTC #11 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

Quoted 2 lines · Jonathan Cameron

On Fri, 5 Sep 2025 09:42:31 +0300
Matti Vaittinen <[email protected]> wrote:

...

Quoted 11 lines

Quoted 10 lines

drivers/iio/adc/rohm-bd79112.c new file +10 -0

+/* ADC channels as named in the data-sheet */
+static const char * const bd79112_chan_names[] = {
+     "AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", "AGIO4A",       /* 0 - 4 */
+     "AGIO5A", "AGIO6A", "AGIO7A", "AGIO8A", "AGIO9A",       /* 5 - 9 */
+     "AGIO10A", "AGIO11A", "AGIO12A", "AGIO13A", "AGIO14A",  /* 10 - 14 */
+     "AGIO15A", "AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B",      /* 15 - 19 */
+     "AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B", "AGIO8B",       /* 20 - 24 */
+     "AGIO9B", "AGIO10B", "AGIO11B", "AGIO12B", "AGIO13B",   /* 25 - 29 */
+     "AGIO14B", "AGIO15B",                                   /* 30 - 31 */
+};

Quoted 3 lines

Quoted 1 line
+ /* Let's assign data-sheet names to channels */
Not seeing any value in this comment given the code that follows. Probably drop it

It was my suggestion. I don't know if you noticed that the amount of the values is *not* power-of-two and it's harder to find a needed value in the list. Moreover, you can read the discussion back and find that actually it was a mistake in the list, which can be avoided (or chances of which will be minimized) in the first place if we see the comments.

Signature · 2 lines

With Best Regards,
Andy Shevchenko

Matti Vaittinen

author maintainer

2025-09-08 05:10 UTC #12 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

Quoted 18 lines · Andy Shevchenko

Quoted 2 lines · Jonathan Cameron

On Fri, 5 Sep 2025 09:42:31 +0300
Matti Vaittinen <[email protected]> wrote:

...

Quoted 12 lines

drivers/iio/adc/rohm-bd79112.c new file +11 -0

+/* ADC channels as named in the data-sheet */
+static const char * const bd79112_chan_names[] = {
+     "AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", "AGIO4A",       /* 0 - 4 */
+     "AGIO5A", "AGIO6A", "AGIO7A", "AGIO8A", "AGIO9A",       /* 5 - 9 */
+     "AGIO10A", "AGIO11A", "AGIO12A", "AGIO13A", "AGIO14A",  /* 10 - 14 */
+     "AGIO15A", "AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B",      /* 15 - 19 */
+     "AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B", "AGIO8B",       /* 20 - 24 */
+     "AGIO9B", "AGIO10B", "AGIO11B", "AGIO12B", "AGIO13B",   /* 25 - 29 */
+     "AGIO14B", "AGIO15B",                                   /* 30 - 31 */
+};
 
+     /* Let's assign data-sheet names to channels */

Quoted 8 lines

Quoted 2 lines
Not seeing any value in this comment given the code that follows. Probably drop it
It was my suggestion. I don't know if you noticed that the amount of> the values is *not* power-of-two and it's harder to find a needed value in the list. Moreover, you can read the discussion back and find
that actually it was a mistake in the list, which can be avoided (or
chances of which will be minimized) in the first place if we see the
comments.

I believe Jonathan meant the:

Quoted 1 line

Quoted 1 line
Quoted 1 line
+/* ADC channels as named in the data-sheet */

not the "index comments". And I kinda agree with him, that's not adding too much. I'll drop that as suggested.

Yours,
-- Matti

Jonathan Cameron

2025-09-09 16:25 UTC #13 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

Quoted 28 lines · On Mon, 8 Sep 2025 08:10:11 +0300 Matti Vaittinen <[email protected]>…

Quoted 18 lines · Andy Shevchenko
Quoted 2 lines · Jonathan Cameron
On Fri, 5 Sep 2025 09:42:31 +0300
Matti Vaittinen <[email protected]> wrote:
...
Quoted 12 lines
Quoted 12 lines
drivers/iio/adc/rohm-bd79112.c new file +11 -0
+/* ADC channels as named in the data-sheet */
+static const char * const bd79112_chan_names[] = {
+     "AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", "AGIO4A",       /* 0 - 4 */
+     "AGIO5A", "AGIO6A", "AGIO7A", "AGIO8A", "AGIO9A",       /* 5 - 9 */
+     "AGIO10A", "AGIO11A", "AGIO12A", "AGIO13A", "AGIO14A",  /* 10 - 14 */
+     "AGIO15A", "AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B",      /* 15 - 19 */
+     "AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B", "AGIO8B",       /* 20 - 24 */
+     "AGIO9B", "AGIO10B", "AGIO11B", "AGIO12B", "AGIO13B",   /* 25 - 29 */
+     "AGIO14B", "AGIO15B",                                   /* 30 - 31 */
+};  
 
+     /* Let's assign data-sheet names to channels */  
Quoted 8 lines
Quoted 2 lines
Not seeing any value in this comment given the code that follows. Probably drop it
It was my suggestion. I don't know if you noticed that the amount of> the values is *not* power-of-two and it's harder to find a needed value in the list. Moreover, you can read the discussion back and find
that actually it was a mistake in the list, which can be avoided (or
chances of which will be minimized) in the first place if we see the
comments.

Quoted 6 lines

I believe Jonathan meant the:
Quoted 1 line
Quoted 1 line
Quoted 1 line
+/* ADC channels as named in the data-sheet */
not the "index comments". And I kinda agree with him, that's not adding too much. I'll drop that as suggested.

Yeah. I like the index comments - though less necessary if power of 2 as you say.

Jonathan

Quoted 3 lines

Yours,
-- Matti

kernel test robot

build bot

2025-09-08 20:02 UTC #14 lore raw

Re: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO

In reply to Matti Vaittinen

kernel test robot noticed the following build errors:

Hi Matti,

kernel test robot noticed the following build errors:

[auto build test ERROR on d1487b0b78720b86ec2a2ac7acc683ec90627e5b]

url:    https://github.com/intel-lab-lkp/linux/commits/Matti-Vaittinen/dt-bindings-iio-adc-ROHM-BD79112-ADC-GPIO/20250905-144454
base:   d1487b0b78720b86ec2a2ac7acc683ec90627e5b
patch link:    https://lore.kernel.org/r/3cc1faffcb4f71f0755b6192f193acecd36bea67.1757053456.git.mazziesaccount%40gmail.com
patch subject: [PATCH v3 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO
config: i386-randconfig-r133-20250908 (https://download.01.org/0day-ci/archive/20250909/[email protected]/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250909/[email protected]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All errors (new ones prefixed by >>, old ones prefixed by <<):

>> ERROR: modpost: "spi_sync" [drivers/base/regmap/regmap-spi.ko] undefined!
>> ERROR: modpost: "spi_async" [drivers/base/regmap/regmap-spi.ko] undefined!
>> ERROR: modpost: "spi_write_then_read" [drivers/base/regmap/regmap-spi.ko] undefined!
>> ERROR: modpost: "__spi_register_driver" [drivers/iio/adc/rohm-bd79112.ko] undefined!
>> ERROR: modpost: "spi_sync" [drivers/iio/adc/rohm-bd79112.ko] undefined!

Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for REGMAP_SPI Depends on [n]: SPI [=n]
Selected by [m]:
- ROHM_BD79112 [=m] && IIO [=m] && I2C [=y] && GPIOLIB [=y]

Signature · 2 lines

0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Matti Vaittinen

author maintainer

2025-09-05 06:42 UTC #15 lore raw

PATCH v3 3/3 MAINTAINERS: Support ROHM BD79112 ADC

In reply to Matti Vaittinen

Add the ROHM BD79112 ADC in the list of the BD791xx ADC drivers which are maintained by undersigned.

Signed-off-by Matti Vaittinen <[email protected]>

---
Revision history:
v1 => :
- no changes

---
 MAINTAINERS | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

MAINTAINERS +2 -1

index af1c8d2bfb3d..8e78a1168c17 100644
@@ -21864,9 +21864,10 @@ S:	Supported
 F:	drivers/power/supply/bd99954-charger.c
 F:	drivers/power/supply/bd99954-charger.h
 
-ROHM BD79124 ADC / GPO IC
+ROHM BD791xx ADC / GPO IC
 M:	Matti Vaittinen <[email protected]>
 S:	Supported
+F:	drivers/iio/adc/rohm-bd79112.c
 F:	drivers/iio/adc/rohm-bd79124.c
 
 ROHM BH1745 COLOUR SENSOR

Signature · 1 line

2.51.0