Skip to contentSkip to conversation

arm64: dts: s32g: Add device tree information for the OCOTP driver

PATCH Applied Dan Carpenter 2 participants 2 messages Sep 12, 2025 – Sep 14, 2025 1 message not in the archive

Subsystems (3)
Device tree bindings Arm i.MX and Layerscape Arm/NXP S32G architecture
lore
Share & tools
lore

A message that is not in the archive (sent off-list or not yet received): [email protected]

Dan Carpenter

author
#1 lore raw

PATCH v4 1/1 arm64: dts: s32g: Add device tree information for the OCOTP driver

Add the device tree information for the S32G On Chip One-Time Programmable Controller (OCOTP) chip.

Signed-off-by Dan Carpenter <[email protected]>

---
The other patches in this patch set were applied but this one needed to be rebased.

v4: rebase on imx/dt64
v3: Add the device tree entry in the correct location based on

    the 0x400a4000 address.

v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {"

 arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
 arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
 2 files changed, 14 insertions(+)
arch/arm64/boot/dts/freescale/s32g2.dtsi +7 -0
index 3ff3b2ff09be..d167624d1f0c 100644
@@ -325,6 +325,13 @@ usdhc0-200mhz-grp4 {
 			};
 		};
 
+		ocotp: nvmem@400a4000 {
+			compatible = "nxp,s32g2-ocotp";
+			reg = <0x400a4000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		swt0: watchdog@40100000 {
 			compatible = "nxp,s32g2-swt";
 			reg = <0x40100000 0x1000>;
arch/arm64/boot/dts/freescale/s32g3.dtsi +7 -0
index 6292ae99883a..be3a582ebc1b 100644
@@ -383,6 +383,13 @@ usdhc0-200mhz-grp4 {
 			};
 		};
 
+		ocotp: nvmem@400a4000 {
+			compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
+			reg = <0x400a4000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		swt0: watchdog@40100000 {
 			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
 			reg = <0x40100000 0x1000>;
Signature · 1 line
2.51.0