riscv: soc: re-organized allwinner

PATCH In review [email protected] 5 participants 13 messages Nov 8, 2025 – Nov 10, 2025

Subsystems (3)

Device tree bindings RISC-V Arm/Allwinner sunXi SoC support

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[email protected]

author

2025-11-08 08:21 UTC #0 lore raw

cover riscv: soc: re-organized allwinner

From: Han Gao <[email protected]>

Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.

d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907

Han Gao (3):
riscv: soc: re-organized allwinner menu
riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE
riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES

 arch/riscv/Kconfig.socs                | 22 +++++++++++++++++-----
 arch/riscv/boot/dts/allwinner/Makefile | 20 ++++++++++----------
 arch/riscv/configs/defconfig           |  2 ++
 3 files changed, 29 insertions(+), 15 deletions(-)

Signature · 1 line

2.47.3

[email protected]

author

2025-11-08 08:21 UTC #1 lore raw

PATCH 1/3 riscv: soc: re-organized allwinner menu

From: Han Gao <[email protected]>

Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.

d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907

Signed-off-by Han Gao <[email protected]>

---
 arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

arch/riscv/Kconfig.socs +17 -5

index 848e7149e443..7cba5d6ec4c3 100644
@@ -54,14 +54,26 @@ config SOC_STARFIVE
 	help
 	  This enables support for StarFive SoC platform hardware.
 
-config ARCH_SUNXI
-	bool "Allwinner sun20i SoCs"
+menuconfig ARCH_SUNXI
+	bool "Allwinner RISC-V SoCs"
+
+if ARCH_SUNXI
+
+config ARCH_SUNXI_XUANTIE
+	bool "Allwinner Xuantie IP SoCs"
 	depends on MMU && !XIP_KERNEL
-	select ERRATA_THEAD
 	select SUN4I_TIMER
+	select ERRATA_THEAD
 	help
-	  This enables support for Allwinner sun20i platform hardware,
-	  including boards based on the D1 and D1s SoCs.
+	  This enables support for Allwinner Xuantie IP SoCs.
+
+config ARCH_SUNXI_ANDES
+	bool "Allwinner Andes IP SoCs"
+	select ERRATA_ANDES
+	help
+	  This enables support for Allwinner Andes IP SoCs.
+
+endif
 
 config ARCH_THEAD
 	bool "T-HEAD RISC-V SoCs"

Signature · 1 line

2.47.3

Krzysztof Kozlowski

2025-11-08 11:29 UTC #2 lore raw

Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu

Quoted 20 lines · On 08/11/2025 09:20, [email protected] wrote:

From: Han Gao <[email protected]>
Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.
d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907
Signed-off-by Han Gao <[email protected]>
---
 arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)
arch/riscv/Kconfig.socs +0 -0
index 848e7149e443..7cba5d6ec4c3 100644
@@ -54,14 +54,26 @@ config SOC_STARFIVE
 	help

arch/riscv/Kconfig.socs config SOC_STARFIVE · line 62

Quoted 10 lines

arch/riscv/Kconfig.socs +6 -2

 	  This enables support for StarFive SoC platform hardware.
 
-config ARCH_SUNXI
-	bool "Allwinner sun20i SoCs"
+menuconfig ARCH_SUNXI
+	bool "Allwinner RISC-V SoCs"
+
+if ARCH_SUNXI
+
+config ARCH_SUNXI_XUANTIE

You should not get multiple ARCHs. ARCH is only one. There is also not much rationale in commit msg for that.

Best regards,
Krzysztof

revy

author

2025-11-08 14:00 UTC #3 lore raw

Re: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu

Quoted 33 lines

-----Original Messages-----
From: "Krzysztof Kozlowski" <[email protected]>
Sent Time: 2025-11-08 19:29:07 (Saturday)
To: [email protected], "Paul Walmsley" <[email protected]>, "Palmer Dabbelt" <[email protected]>, "Albert Ou" <[email protected]>, "Alexandre Ghiti" <[email protected]>, "Rob Herring" <[email protected]>, "Krzysztof Kozlowski" <[email protected]>, "Conor Dooley" <[email protected]>, "Chen-Yu Tsai" <[email protected]>, "Jernej Skrabec" <[email protected]>, "Samuel Holland" <[email protected]>, "Yixun Lan" <[email protected]>, "Drew Fustini" <[email protected]>, "Geert Uytterhoeven" <[email protected]>, "Guodong Xu" <[email protected]>, "Haylen Chu" <[email protected]>, "Joel Stanley" <[email protected]>
Cc: [email protected], [email protected], [email protected], [email protected], [email protected], "Han Gao" <[email protected]>
Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu
Quoted 22 lines · On 08/11/2025 09:20, [email protected] wrote:
From: Han Gao <[email protected]>
Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.
d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907
Signed-off-by Han Gao <[email protected]>
---
arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
arch/riscv/Kconfig.socs +0 -0
index 848e7149e443..7cba5d6ec4c3 100644
@@ -54,14 +54,26 @@ config SOC_STARFIVE
 	help
 	  This enables support for StarFive SoC platform hardware.
 

Quoted 12 lines

arch/riscv/Kconfig.socs config SOC_STARFIVE · line 62
Quoted 8 lines
arch/riscv/Kconfig.socs +6 -2
-config ARCH_SUNXI
-	bool "Allwinner sun20i SoCs"
+menuconfig ARCH_SUNXI
+	bool "Allwinner RISC-V SoCs"
+
+if ARCH_SUNXI
+
+config ARCH_SUNXI_XUANTIE
You should not get multiple ARCHs. ARCH is only one. There is also not much rationale in commit msg for that.

The main goal is to avoid choosing multiple IP addresses for erreta. If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA.

For example, v821 uses Andes ax27, but it used to select ERRATA_THEAD.

Quoted 3 lines

Best regards,
Krzysztof

Krzysztof Kozlowski

2025-11-08 14:47 UTC #4 lore raw

Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu

Quoted 46 lines · revy

Quoted 33 lines
-----Original Messages-----
From: "Krzysztof Kozlowski" <[email protected]>
Sent Time: 2025-11-08 19:29:07 (Saturday)
To: [email protected], "Paul Walmsley" <[email protected]>, "Palmer Dabbelt" <[email protected]>, "Albert Ou" <[email protected]>, "Alexandre Ghiti" <[email protected]>, "Rob Herring" <[email protected]>, "Krzysztof Kozlowski" <[email protected]>, "Conor Dooley" <[email protected]>, "Chen-Yu Tsai" <[email protected]>, "Jernej Skrabec" <[email protected]>, "Samuel Holland" <[email protected]>, "Yixun Lan" <[email protected]>, "Drew Fustini" <[email protected]>, "Geert Uytterhoeven" <[email protected]>, "Guodong Xu" <[email protected]>, "Haylen Chu" <[email protected]>, "Joel Stanley" <[email protected]>
Cc: [email protected], [email protected], [email protected], [email protected], [email protected], "Han Gao" <[email protected]>
Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu
Quoted 22 lines · On 08/11/2025 09:20, [email protected] wrote:
From: Han Gao <[email protected]>
Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.
d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907
Signed-off-by Han Gao <[email protected]>
---
arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
arch/riscv/Kconfig.socs +0 -0
index 848e7149e443..7cba5d6ec4c3 100644
@@ -54,14 +54,26 @@ config SOC_STARFIVE
 	help
 	  This enables support for StarFive SoC platform hardware.
 
Quoted 12 lines
arch/riscv/Kconfig.socs config SOC_STARFIVE · line 62
Quoted 8 lines
arch/riscv/Kconfig.socs +6 -2
-config ARCH_SUNXI
-	bool "Allwinner sun20i SoCs"
+menuconfig ARCH_SUNXI
+	bool "Allwinner RISC-V SoCs"
+
+if ARCH_SUNXI
+
+config ARCH_SUNXI_XUANTIE
You should not get multiple ARCHs. ARCH is only one. There is also not much rationale in commit msg for that.

Quoted 2 lines

The main goal is to avoid choosing multiple IP addresses for erreta. If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA.

Not explained in commit msg but anyway not a good argument. It is some sort of micro optimization and you completely miss the point we target multiarch kernels.

Best regards,
Krzysztof

Krzysztof Kozlowski

2025-11-08 14:48 UTC #5 lore raw

Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu

Quoted 47 lines · Krzysztof Kozlowski

Quoted 46 lines · revy
Quoted 45 lines
-----Original Messages-----
From: "Krzysztof Kozlowski" <[email protected]>
Sent Time: 2025-11-08 19:29:07 (Saturday)
To: [email protected], "Paul Walmsley" <[email protected]>, "Palmer Dabbelt" <[email protected]>, "Albert Ou" <[email protected]>, "Alexandre Ghiti" <[email protected]>, "Rob Herring" <[email protected]>, "Krzysztof Kozlowski" <[email protected]>, "Conor Dooley" <[email protected]>, "Chen-Yu Tsai" <[email protected]>, "Jernej Skrabec" <[email protected]>, "Samuel Holland" <[email protected]>, "Yixun Lan" <[email protected]>, "Drew Fustini" <[email protected]>, "Geert Uytterhoeven" <[email protected]>, "Guodong Xu" <[email protected]>, "Haylen Chu" <[email protected]>, "Joel Stanley" <[email protected]>
Cc: [email protected], [email protected], [email protected], [email protected], [email protected], "Han Gao" <[email protected]>
Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu
Quoted 20 lines · On 08/11/2025 09:20, [email protected] wrote:
From: Han Gao <[email protected]>
Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.
d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907
Signed-off-by Han Gao <[email protected]>
---
arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
arch/riscv/Kconfig.socs +0 -0
index 848e7149e443..7cba5d6ec4c3 100644
@@ -54,14 +54,26 @@ config SOC_STARFIVE
 	help
arch/riscv/Kconfig.socs config SOC_STARFIVE · line 62
Quoted 10 lines
arch/riscv/Kconfig.socs +6 -2
 	  This enables support for StarFive SoC platform hardware.
 
-config ARCH_SUNXI
-	bool "Allwinner sun20i SoCs"
+menuconfig ARCH_SUNXI
+	bool "Allwinner RISC-V SoCs"
+
+if ARCH_SUNXI
+
+config ARCH_SUNXI_XUANTIE
You should not get multiple ARCHs. ARCH is only one. There is also not much rationale in commit msg for that.

Quoted 6 lines

Quoted 2 lines
The main goal is to avoid choosing multiple IP addresses for erreta. If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA.
Not explained in commit msg but anyway not a good argument. It is some sort of micro optimization and you completely miss the point we target multiarch kernels.

Heh, and I actually did not forbid or discourage choosing erratas per your soc. I said you only get one top level ARCH. Look at all arm64 platforms. How many ARCHs are there per one vendor?

Best regards,
Krzysztof

Conor Dooley

2025-11-08 16:24 UTC #6 lore raw

Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu

Quoted 51 lines · Krzysztof Kozlowski

Quoted 50 lines · Krzysztof Kozlowski
Quoted 48 lines · revy
Quoted 33 lines
-----Original Messages-----
From: "Krzysztof Kozlowski" <[email protected]>
Sent Time: 2025-11-08 19:29:07 (Saturday)
To: [email protected], "Paul Walmsley" <[email protected]>, "Palmer Dabbelt" <[email protected]>, "Albert Ou" <[email protected]>, "Alexandre Ghiti" <[email protected]>, "Rob Herring" <[email protected]>, "Krzysztof Kozlowski" <[email protected]>, "Conor Dooley" <[email protected]>, "Chen-Yu Tsai" <[email protected]>, "Jernej Skrabec" <[email protected]>, "Samuel Holland" <[email protected]>, "Yixun Lan" <[email protected]>, "Drew Fustini" <[email protected]>, "Geert Uytterhoeven" <[email protected]>, "Guodong Xu" <[email protected]>, "Haylen Chu" <[email protected]>, "Joel Stanley" <[email protected]>
Cc: [email protected], [email protected], [email protected], [email protected], [email protected], "Han Gao" <[email protected]>
Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu
Quoted 22 lines · On 08/11/2025 09:20, [email protected] wrote:
From: Han Gao <[email protected]>
Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.
d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907
Signed-off-by Han Gao <[email protected]>
---
arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
arch/riscv/Kconfig.socs +0 -0
index 848e7149e443..7cba5d6ec4c3 100644
@@ -54,14 +54,26 @@ config SOC_STARFIVE
 	help
 	  This enables support for StarFive SoC platform hardware.
 
Quoted 12 lines
arch/riscv/Kconfig.socs config SOC_STARFIVE · line 62
Quoted 8 lines
arch/riscv/Kconfig.socs +6 -2
-config ARCH_SUNXI
-	bool "Allwinner sun20i SoCs"
+menuconfig ARCH_SUNXI
+	bool "Allwinner RISC-V SoCs"
+
+if ARCH_SUNXI
+
+config ARCH_SUNXI_XUANTIE
You should not get multiple ARCHs. ARCH is only one. There is also not much rationale in commit msg for that.
The main goal is to avoid choosing multiple IP addresses for erreta. If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA.

Quoted 7 lines

Quoted 3 lines
Not explained in commit msg but anyway not a good argument. It is some sort of micro optimization and you completely miss the point we target multiarch kernels.
Heh, and I actually did not forbid or discourage choosing erratas per your soc. I said you only get one top level ARCH. Look at all arm64 platforms. How many ARCHs are there per one vendor?

Yeah, it only allows you to enable the errata, it doesn't force any of them to "y". Some will get enabled by default when ARCH_SUNXI is enabled, but if someone is only targeting on device they can just turn them off... I'm pretty inclined to just NAK this unless there's some actual value.

Han Gao

author

2025-11-08 16:32 UTC #7 lore raw

Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu

Quoted 65 lines · Conor Dooley

Quoted 51 lines · Krzysztof Kozlowski
Quoted 50 lines · Krzysztof Kozlowski
Quoted 48 lines · revy
Quoted 33 lines
-----Original Messages-----
From: "Krzysztof Kozlowski" <[email protected]>
Sent Time: 2025-11-08 19:29:07 (Saturday)
To: [email protected], "Paul Walmsley" <[email protected]>, "Palmer Dabbelt" <[email protected]>, "Albert Ou" <[email protected]>, "Alexandre Ghiti" <[email protected]>, "Rob Herring" <[email protected]>, "Krzysztof Kozlowski" <[email protected]>, "Conor Dooley" <[email protected]>, "Chen-Yu Tsai" <[email protected]>, "Jernej Skrabec" <[email protected]>, "Samuel Holland" <[email protected]>, "Yixun Lan" <[email protected]>, "Drew Fustini" <[email protected]>, "Geert Uytterhoeven" <[email protected]>, "Guodong Xu" <[email protected]>, "Haylen Chu" <[email protected]>, "Joel Stanley" <[email protected]>
Cc: [email protected], [email protected], [email protected], [email protected], [email protected], "Han Gao" <[email protected]>
Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu
Quoted 22 lines · On 08/11/2025 09:20, [email protected] wrote:
From: Han Gao <[email protected]>
Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.
d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907
Signed-off-by Han Gao <[email protected]>
---
arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
arch/riscv/Kconfig.socs +0 -0
index 848e7149e443..7cba5d6ec4c3 100644
@@ -54,14 +54,26 @@ config SOC_STARFIVE
help
This enables support for StarFive SoC platform hardware.
Quoted 12 lines
arch/riscv/Kconfig.socs config SOC_STARFIVE · line 62
Quoted 8 lines
arch/riscv/Kconfig.socs +6 -2
-config ARCH_SUNXI
- bool "Allwinner sun20i SoCs"
+menuconfig ARCH_SUNXI
+ bool "Allwinner RISC-V SoCs"
+
+if ARCH_SUNXI
+
+config ARCH_SUNXI_XUANTIE
You should not get multiple ARCHs. ARCH is only one. There is also not much rationale in commit msg for that.
The main goal is to avoid choosing multiple IP addresses for erreta. If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA.
Quoted 7 lines
Quoted 3 lines
Not explained in commit msg but anyway not a good argument. It is some sort of micro optimization and you completely miss the point we target multiarch kernels.
Heh, and I actually did not forbid or discourage choosing erratas per your soc. I said you only get one top level ARCH. Look at all arm64 platforms. How many ARCHs are there per one vendor?

Quoted 5 lines

Yeah, it only allows you to enable the errata, it doesn't force any of them to "y". Some will get enabled by default when ARCH_SUNXI is enabled, but if someone is only targeting on device they can just turn them off... I'm pretty inclined to just NAK this unless there's some actual value.

I understand. I'm going to abandon this patch and plan to resubmit a patch that only modifies the description from sun20i to allwinnner.

[email protected]

author

2025-11-08 08:21 UTC #8 lore raw

PATCH 2/3 riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE

In reply to [email protected]

From: Han Gao <[email protected]>

d1(s) use Xuantie IP.

Signed-off-by Han Gao <[email protected]>

---
 arch/riscv/boot/dts/allwinner/Makefile | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

arch/riscv/boot/dts/allwinner/Makefile +10 ~~-10~~

index 1c91be38ea16..635762ba06fe 100644
@@ -1,11 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1s-mangopi-mq.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-clockworkpi-v3.14.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-devterm-v3.14.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-dongshan-nezha-stu.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-lichee-rv-86-panel-480p.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-lichee-rv-86-panel-720p.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-lichee-rv-dock.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-lichee-rv.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-mangopi-mq-pro.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1-nezha.dtb
+dtb-$(CONFIG_ARCH_SUNXI_XUANTIE) += sun20i-d1s-mangopi-mq.dtb

Signature · 1 line

2.47.3

[email protected]

author

2025-11-08 08:21 UTC #9 lore raw

PATCH 3/3 riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES

In reply to [email protected]

From: Han Gao <[email protected]>

These options need to be enabled to prepare for v821/v861/v881.

Signed-off-by Han Gao <[email protected]>

---
 arch/riscv/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

arch/riscv/configs/defconfig +2 -0

index fc2725cbca18..ed0ac65babdc 100644
@@ -29,6 +29,8 @@ CONFIG_ARCH_SOPHGO=y
 CONFIG_ARCH_SPACEMIT=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUNXI_XUANTIE=y
+CONFIG_ARCH_SUNXI_ANDES=y
 CONFIG_ARCH_THEAD=y
 CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_CANAAN=y

Signature · 1 line

2.47.3

Krzysztof Kozlowski

2025-11-08 11:29 UTC #10 lore raw

Re: [PATCH 3/3] riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES

Quoted 14 lines · On 08/11/2025 09:20, [email protected] wrote:

From: Han Gao <[email protected]>
These options need to be enabled to prepare for v821/v861/v881.
Signed-off-by Han Gao <[email protected]>
---
 arch/riscv/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)
arch/riscv/configs/defconfig +0 -0
index fc2725cbca18..ed0ac65babdc 100644

arch/riscv/configs/defconfig CONFIG_ARCH_SOPHGO=y · line 33

Quoted 5 lines

arch/riscv/configs/defconfig +2 -0

@@ -29,6 +29,8 @@ CONFIG_ARCH_SOPHGO=y
 CONFIG_ARCH_SPACEMIT=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUNXI_XUANTIE=y
+CONFIG_ARCH_SUNXI_ANDES=y

No. One ARCH. You do not need more.

Best regards,
Krzysztof

Geert Uytterhoeven

2025-11-10 09:04 UTC #11 lore raw

Re: [PATCH 3/3] riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES

In reply to [email protected]

Hi Gaohan,

Quoted 5 lines · On Sat, 8 Nov 2025 at 09:21, <[email protected]> wrote:

From: Han Gao <[email protected]>
These options need to be enabled to prepare for v821/v861/v881.
Signed-off-by Han Gao <[email protected]>

Thanks for your patch!

arch/riscv/configs/defconfig CONFIG_ARCH_SOPHGO=y · line 36

Quoted 11 lines

arch/riscv/configs/defconfig +2 -0

@@ -29,6 +29,8 @@ CONFIG_ARCH_SOPHGO=y
 CONFIG_ARCH_SPACEMIT=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUNXI_XUANTIE=y
+CONFIG_ARCH_SUNXI_ANDES=y
 CONFIG_ARCH_THEAD=y
 CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_CANAAN=y

Other subarchs handle this with "default y" in drivers/soc/*/Kconfig.

Gr{oetje,eeting}s,

Geert

Signature · 5 lines

Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Jernej Škrabec

maintainer

2025-11-08 09:46 UTC #12 lore raw

In reply to [email protected]

Hi,

Dne sobota, 8. november 2025 ob 09:20:22 Srednjeevropski standardni čas je [email protected] napisal(a):

Quoted 5 lines

From: Han Gao <[email protected]>
Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V, using different IPs.

Quoted 8 lines

d1(s): Xuantie C906
v821: Andes A27 + XuanTie E907
v861/v881: XuanTie C907
Han Gao (3):
riscv: soc: re-organized allwinner menu
riscv: soc: allwinner: d1: use the ARCH_SUNXI_XUANTIE
riscv: defconfig: enable SUNXI_XUANTIE and SUNXI_ANDES

This series is incomplete. It introduces ARCH_SUNXI_ANDES symbol but it is never used.

Additionally, patches are not organized properly. First, you should introduce reorganization and only then introduce new features. Also, not a single patch should break existing functionality for bisectability reasons. First patch breaks compilation of DT files while second restores that. This must not happen.

Best regards,
Jernej

Quoted 7 lines

 arch/riscv/Kconfig.socs                | 22 +++++++++++++++++-----
 arch/riscv/boot/dts/allwinner/Makefile | 20 ++++++++++----------
 arch/riscv/configs/defconfig           |  2 ++
 3 files changed, 29 insertions(+), 15 deletions(-)