arm64: dts: mt8167: Add the mmsys reset bit to reset DSI
cover arm64: dts: mt8167: Add the mmsys reset bit to reset DSI
This series adds support for the MMSYS reset registers for mt8167 and uses them to trigger DSI reset during mtk-drm probe. Registers and values are taken from the kernel source code for the Lenovo Smart Clock and other mt8167 devices.
Luca Leonardo Scorcia (7):
soc: mediatek: mtk-mmsys: Add resets for mt8167
dt-bindings: mediatek: Add reset controller constants for mt8167
watchdog: mediatek: Add support for mt8167 TOPRGU/WDT
dt-bindings: watchdog: Support MediaTek MT8167 wdt
arm64: dts: mt8167: Add a specific watchdog dts node
arm64: dts: mt8167: Add the mmsys reset bit to reset dsi
arm64: dts: mt8167: Add additional mmsys reset bits
.../bindings/watchdog/mediatek,mtk-wdt.yaml | 1 + arch/arm64/boot/dts/mediatek/mt8167.dtsi | 10 ++++ drivers/soc/mediatek/mt8167-mmsys.h | 3 ++ drivers/soc/mediatek/mtk-mmsys.c | 2 + drivers/watchdog/mtk_wdt.c | 6 +++ include/dt-bindings/reset/mt8167-resets.h | 47 +++++++++++++++++++ 6 files changed, 69 insertions(+) create mode 100644 include/dt-bindings/reset/mt8167-resets.h
Signature · 1 line
2.43.0
PATCH 1/7 soc: mediatek: mtk-mmsys: Add resets for mt8167
The mt8167 SoC has 64 MMSYS resets, split in two contiguous 32-bits registers, MMSYS_SW0_RST_B (0x140) and MMSYS_SW1_RST_B (0x144), as also stated in the downstream kernel for the Lenovo Smart Clock in the ddp_reg.h header.
--- drivers/soc/mediatek/mt8167-mmsys.h | 3 +++ drivers/soc/mediatek/mtk-mmsys.c | 2 ++ 2 files changed, 5 insertions(+)
drivers/soc/mediatek/mt8167-mmsys.h +3 -0
@@ -18,6 +18,9 @@#define MT8167_DSI0_SEL_IN_RDMA0 0x1#define MT8167_DSI0_SEL_IN_MASK 0x3 +#define MT8167_MMSYS_SW0_RST_B 0x140 +#define MT8167_MMSYS_SW1_RST_B 0x144 +static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { MMSYS_ROUTE(OVL0, COLOR0, MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
drivers/soc/mediatek/mtk-mmsys.c +2 -0
@@ -57,6 +57,8 @@ static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), + .sw0_rst_offset = MT8167_MMSYS_SW0_RST_B, + .num_resets = 64, };static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
Signature · 1 line
2.43.0
PATCH 2/7 dt-bindings: mediatek: Add reset controller constants for mt8167
In reply to Luca Leonardo ScorciaThis file comes from the Lenovo Smart Clock kernel sources.
--- include/dt-bindings/reset/mt8167-resets.h | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 include/dt-bindings/reset/mt8167-resets.h
include/dt-bindings/reset/mt8167-resets.h new file +38 -0
@@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* +* Copyright (c) 2015 MediaTek Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8167 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8167 + +/* TOPRGU resets */ +#define MT8167_TOPRGU_DDRPHY_FLASH_RST 0/* reset ddrphy and flash pad macro */ +#define MT8167_TOPRGU_AUD_PAD_RST 1/* Write 1 to reset audio_tdm_in_pad,audio_tdm_pad,audio_fifo */ +#define MT8167_TOPRGU_MM_RST 2/* Write 1 to reset MMSYS */ +#define MT8167_TOPRGU_MFG_RST 3/* Write 1 to reset MFG */ +#define MT8167_TOPRGU_MDSYS_RST 4/* Write 1 to reset INFRA_AO */ +#define MT8167_TOPRGU_CONN_RST 5/* Write 1 to reset CONNSYS WDT reset */ +#define MT8167_TOPRGU_PAD2CAM_DIG_MIPI_RX_RST 6/* Write 1 to reset MM and its related pad macro(DPI,MIPI_CFG,MIPI_TX) */ +#define MT8167_TOPRGU_DIG_MIPI_TX_RST 7/* Write 1 to reset digi_mipi_tx */ +#define MT8167_TOPRGU_SPI_PAD_MACRO_RST 8/* Write 1 to reset SPI_PAD_MACRO */ +#define MT8167_TOPRGU_APMIXED_RST 10/* Write 1 to reset APMIXEDSYS */ +#define MT8167_TOPRGU_VDEC_RST 11/* Write 1 to reset VDEC module */ +#define MT8167_TOPRGU_CONN_MCU_RST 12/* Write 1 to reset CONNSYS */ +#define MT8167_TOPRGU_EFUSE_RST 13/* Write 1 to reset efuse */ +#define MT8167_TOPRGU_PWRAP_SPICTL_RST 14/* Write 1 to reset pwrap_spictl module */ +#define MT8167_TOPRGU_SW_RST_NUM 15 + +/* MMSYS resets */ +#define MT8167_MMSYS_SW0_RST_B_DISP_DSI0 22 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8167 */
Signature · 1 line
2.43.0
PATCH 3/7 watchdog: mediatek: Add support for mt8167 TOPRGU/WDT
In reply to Luca Leonardo ScorciaAdd support for the Top Reset Generation Unit/Watchdog Timer found on mt8167.
--- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/watchdog/mtk_wdt.c +6 -0
@@ -13,6 +13,7 @@#include <dt-bindings/reset/mediatek,mt6735-wdt.h> #include <dt-bindings/reset/mediatek,mt6795-resets.h> #include <dt-bindings/reset/mt7986-resets.h> +#include <dt-bindings/reset/mt8167-resets.h> #include <dt-bindings/reset/mt8183-resets.h> #include <dt-bindings/reset/mt8186-resets.h> #include <dt-bindings/reset/mt8188-resets.h>
@@ -105,6 +106,10 @@ static const struct mtk_wdt_data mt7988_data = { .has_swsysrst_en = true, }; +static const struct mtk_wdt_data mt8167_data = { + .toprgu_sw_rst_num =MT8167_TOPRGU_SW_RST_NUM , +}; +static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num =MT8183_TOPRGU_SW_RST_NUM , };
@@ -498,6 +503,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data }, + { .compatible = "mediatek,mt8167-wdt", .data = &mt8167_data }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
Signature · 1 line
2.43.0
PATCH 4/7 dt-bindings: watchdog: Support MediaTek MT8167 wdt
In reply to Luca Leonardo ScorciaModify dt-binding to add support for mt8167 dts node of wdt
--- Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +1 -0
@@ -26,6 +26,7 @@ properties: - mediatek,mt6795-wdt - mediatek,mt7986-wdt - mediatek,mt7988-wdt + - mediatek,mt8167-wdt - mediatek,mt8183-wdt - mediatek,mt8186-wdt - mediatek,mt8188-wdt
Signature · 1 line
2.43.0
PATCH 5/7 arm64: dts: mt8167: Add a specific watchdog dts node
In reply to Luca Leonardo ScorciaThe watchdog driver for mt8167 relies on DT data, so the fallback compatible mt8516 won't work, need to update watchdog device node to sync with watchdog dt-binding document.
--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/mediatek/mt8167.dtsi +7 -0
@@ -48,6 +48,13 @@ apmixedsys: apmixedsys@10018000 { #clock-cells = <1>; }; + watchdog@10007000 { + compatible = "mediatek,mt8167-wdt"; + reg = <0 0x10007000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + scpsys: syscon@10006000 { compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>;
Signature · 1 line
2.43.0
PATCH 6/7 arm64: dts: mt8167: Add the mmsys reset bit to reset dsi
In reply to Luca Leonardo ScorciaDSI hardware reset is needed to prevent different settings between the bootloader and the kernel.
--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +++ 1 file changed, 3 insertions(+)
arch/arm64/boot/dts/mediatek/mt8167.dtsi +3 -0
@@ -8,6 +8,7 @@ #include <dt-bindings/clock/mt8167-clk.h> #include <dt-bindings/memory/mt8167-larb-port.h> #include <dt-bindings/power/mt8167-power.h> +#include <dt-bindings/reset/mt8167-resets.h> #include "mt8167-pinfunc.h"
@@ -189,6 +190,7 @@ dsi: dsi@14012000 { <&mmsys CLK_MM_DSI_DIGITAL>, <&mipi_tx>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8167_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx>; phy-names = "dphy"; status = "disabled";
@@ -295,6 +297,7 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; smi_common: smi@14017000 {
Signature · 1 line
2.43.0
PATCH 7/7 arm64: dts: mt8167: Add additional mmsys reset bits
In reply to Luca Leonardo ScorciaSome extra mmsys reset bits are defined in the Lenovo Smart Clock kernel sources - file cmdq_mdp.c
--- include/dt-bindings/reset/mt8167-resets.h | 9 +++++++++ 1 file changed, 9 insertions(+)
include/dt-bindings/reset/mt8167-resets.h +9 -0
@@ -33,6 +33,15 @@#define MT8167_TOPRGU_SW_RST_NUM 15/* MMSYS resets */ +#define MT8167_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT8167_MMSYS_SW0_RST_B_SMI_LARB 1 +#define MT8167_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT8167_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ0 4 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ1 5 +#define MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0 6 +#define MT8167_MMSYS_SW0_RST_B_MDP_WDMA 7 +#define MT8167_MMSYS_SW0_RST_B_MDP_WROT0 8#define MT8167_MMSYS_SW0_RST_B_DISP_DSI0 22#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8167 */
Signature · 1 line
2.43.0
Re: [PATCH 6/7] arm64: dts: mt8167: Add the mmsys reset bit to reset dsi
In reply to Luca Leonardo ScorciaI apologize for the mistake, I did not notice that the dsi node is not present upstream yet, so this specific patch won't apply. Any comments are appreciated though!
I will send a separate patch to add the display nodes to the dts and the required compatibles to the bindings.
Il giorno mer 11 feb 2026 alle ore 20:06 Luca Leonardo Scorcia <[email protected]> ha scritto:
Quoted 40 lines
DSI hardware reset is needed to prevent different settings between the bootloader and the kernel.
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +++ 1 file changed, 3 insertions(+)arch/arm64/boot/dts/mediatek/mt8167.dtsi +3
-1@@ -8,6 +8,7 @@ #include <dt-bindings/clock/mt8167-clk.h> #include <dt-bindings/memory/mt8167-larb-port.h> #include <dt-bindings/power/mt8167-power.h> +#include <dt-bindings/reset/mt8167-resets.h> #include "mt8167-pinfunc.h"@@ -189,6 +190,7 @@ dsi: dsi@14012000 { <&mmsys CLK_MM_DSI_DIGITAL>, <&mipi_tx>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8167_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx>; phy-names = "dphy"; status = "disabled";@@ -295,6 +297,7 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; smi_common: smi@14017000 { --2.43.0
Signature · 2 lines
Luca Leonardo Scorcia [email protected]
AngeloGioacchino Del Regno
maintainerRe: [PATCH 1/7] soc: mediatek: mtk-mmsys: Add resets for mt8167
In reply to Luca Leonardo ScorciaIl 11/02/26 20:03, Luca Leonardo Scorcia ha scritto:
Quoted 30 lines
The mt8167 SoC has 64 MMSYS resets, split in two contiguous 32-bits registers,
MMSYS_SW0_RST_B(0x140) andMMSYS_SW1_RST_B(0x144), as also stated in the downstream kernel for the Lenovo Smart Clock in theddp_reg.hheader.Signed-off-by Luca Leonardo Scorcia <[email protected]>--- drivers/soc/mediatek/mt8167-mmsys.h | 3 +++ drivers/soc/mediatek/mtk-mmsys.c | 2 ++ 2 files changed, 5 insertions(+)drivers/soc/mediatek/mt8167-mmsys.h +3
-0@@ -18,6 +18,9 @@#define MT8167_DSI0_SEL_IN_RDMA0 0x1#define MT8167_DSI0_SEL_IN_MASK 0x3 +#define MT8167_MMSYS_SW0_RST_B 0x140 +#define MT8167_MMSYS_SW1_RST_B 0x144 +static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { MMSYS_ROUTE(OVL0, COLOR0, MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,drivers/soc/mediatek/mtk-mmsys.c +0
-0
drivers/soc/mediatek/mtk-mmsys.c static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { · line 61
Quoted 5 lines
drivers/soc/mediatek/mtk-mmsys.c +2
-0@@ -57,6 +57,8 @@ static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), + .sw0_rst_offset = MT8167_MMSYS_SW0_RST_B, + .num_resets = 64,
Unless you have the full reset table...
.rst_tb = (const u8[]) {
[MT8167_MMSYS_SW0_RST_B_SMI_COMMON] = MMSYS_RST_NR(0, 0),
[MT8167_MMSYS_SW0_RST_B_SMI_LARB] = MMSYS_RST_NR(0, 1),
[MT8167_MMSYS_SW0_RST_B_CAM_MDP] = MMSYS_RST_NR(0, 2),
[MT8167_MMSYS_SW0_RST_B_MDP_RDMA0] = MMSYS_RST_NR(0, 3),
[MT8167_MMSYS_SW0_RST_B_MDP_RSZ0] = MMSYS_RST_NR(0, 4),
[MT8167_MMSYS_SW0_RST_B_MDP_RSZ1] = MMSYS_RST_NR(0, 5),
[MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0] = MMSYS_RST_NR(0, 6),
[MT8167_MMSYS_SW0_RST_B_MDP_WDMA] = MMSYS_RST_NR(0, 7),
[MT8167_MMSYS_SW0_RST_B_MDP_WROT0] = MMSYS_RST_NR(0, 8),
[MT8167_MMSYS_SW0_RST_B_DISP_DSI0] = MMSYS_RST_NR(0, 22),
},
.num_resets = 10,Cheers,
Angelo
Quoted 3 lines
drivers/soc/mediatek/mtk-mmsys.c +0
-0};static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
AngeloGioacchino Del Regno
maintainerRe: [PATCH 2/7] dt-bindings: mediatek: Add reset controller constants for mt8167
In reply to Luca Leonardo ScorciaIl 11/02/26 20:03, Luca Leonardo Scorcia ha scritto:
Quoted 5 lines
This file comes from the Lenovo Smart Clock kernel sources.
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- include/dt-bindings/reset/mt8167-resets.h | 38 +++++++++++++++++++++++
Please rename this to "mediatek,mt8167-resets.h"
include/dt-bindings/reset/mt8167-resets.h line 4
Quoted 13 lines
1 file changed, 38 insertions(+)create mode 100644
include/dt-bindings/reset/mt8167-resets.hinclude/dt-bindings/reset/mt8167-resets.h new file +4
-0@@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* +* Copyright (c) 2015 MediaTek Inc. +*
End the comment here; the extra text is redundant with the specified license identifier anyway.
Quoted 5 lines
include/dt-bindings/reset/mt8167-resets.h new file +5
-0+* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful,
include/dt-bindings/reset/mt8167-resets.h line 19
Quoted 10 lines
include/dt-bindings/reset/mt8167-resets.h new file +10
-0+* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8167 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8167 + +/* TOPRGU resets */ +#define MT8167_TOPRGU_DDRPHY_FLASH_RST 0/* reset ddrphy and flash pad macro */
Please remove all of the extra comments: they're stating the obvious anyway.
include/dt-bindings/reset/mt8167-resets.h line 27
Quoted 8 lines
include/dt-bindings/reset/mt8167-resets.h new file +8
-0+#define MT8167_TOPRGU_AUD_PAD_RST 1/* Write 1 to reset audio_tdm_in_pad,audio_tdm_pad,audio_fifo */ +#define MT8167_TOPRGU_MM_RST 2/* Write 1 to reset MMSYS */ +#define MT8167_TOPRGU_MFG_RST 3/* Write 1 to reset MFG */ +#define MT8167_TOPRGU_MDSYS_RST 4/* Write 1 to reset INFRA_AO */ +#define MT8167_TOPRGU_CONN_RST 5/* Write 1 to reset CONNSYS WDT reset */ +#define MT8167_TOPRGU_PAD2CAM_DIG_MIPI_RX_RST 6/* Write 1 to reset MM and its related pad macro(DPI,MIPI_CFG,MIPI_TX) */ +#define MT8167_TOPRGU_DIG_MIPI_TX_RST 7/* Write 1 to reset digi_mipi_tx */ +#define MT8167_TOPRGU_SPI_PAD_MACRO_RST 8/* Write 1 to reset SPI_PAD_MACRO */
You're missing reset N.9 - I'm mostly sure that 9 is
MT8167_TOPRGU_INFRA_AO_RST
include/dt-bindings/reset/mt8167-resets.h line 36
Quoted 9 lines
include/dt-bindings/reset/mt8167-resets.h new file +9
-0+#define MT8167_TOPRGU_APMIXED_RST 10/* Write 1 to reset APMIXEDSYS */ +#define MT8167_TOPRGU_VDEC_RST 11/* Write 1 to reset VDEC module */ +#define MT8167_TOPRGU_CONN_MCU_RST 12/* Write 1 to reset CONNSYS */ +#define MT8167_TOPRGU_EFUSE_RST 13/* Write 1 to reset efuse */ +#define MT8167_TOPRGU_PWRAP_SPICTL_RST 14/* Write 1 to reset pwrap_spictl module */ +#define MT8167_TOPRGU_SW_RST_NUM 15 + +/* MMSYS resets */ +#define MT8167_MMSYS_SW0_RST_B_DISP_DSI0 22
That's not ok. All of the bindings must not be hardware specific, and I know that this "22" is bit(22) of MMSYS.
The definitions must start from 0 and must have no holes (0 1 2 4 6 7 8 is not ok, but 0 1 2 3 4 5 is ok).
If you have the entire list and it also matches 1:1 with the HW coincidentally, that'd be okay as well.
Since I have a hunch that you don't actually have the entire list, you should at this point define your MT8167_SW0_RST_B_DISP_DSI0 as 0, and check the review on your mmsys patch for more hints.
P.S.:
#define MT8167_MMSYS_SW0_RST_B_SMI_COMMON 0
#define MT8167_MMSYS_SW0_RST_B_SMI_LARB 1
#define MT8167_MMSYS_SW0_RST_B_CAM_MDP 2
#define MT8167_MMSYS_SW0_RST_B_MDP_RDMA0 3
#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ0 4
#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ1 5
#define MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0 6
#define MT8167_MMSYS_SW0_RST_B_MDP_WDMA 7
#define MT8167_MMSYS_SW0_RST_B_MDP_WROT0 8
#define MT8167_MMSYS_SW0_RST_B_DISP_DSI0 9
Quoted 2 lines
include/dt-bindings/reset/mt8167-resets.h new file +2
-0+ +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8167 */
Re: [PATCH 4/7] dt-bindings: watchdog: Support MediaTek MT8167 wdt
In reply to Luca Leonardo ScorciaIl 11/02/26 20:03, Luca Leonardo Scorcia ha scritto:
Quoted 3 lines
Modify dt-binding to add support for mt8167 dts node of wdt
Signed-off-by Luca Leonardo Scorcia <[email protected]>
Please put the binding patch before the driver patch (you anyway have to send a v2, so ...)
AngeloGioacchino Del Regno
maintainerRe: [PATCH 5/7] arm64: dts: mt8167: Add a specific watchdog dts node
In reply to Luca Leonardo ScorciaIl 11/02/26 20:03, Luca Leonardo Scorcia ha scritto:
Quoted 4 lines
The watchdog driver for mt8167 relies on DT data, so the fallback compatible mt8516 won't work, need to update watchdog device node to sync with watchdog dt-binding document.
Sorry, what are you talking about?
You probably forgot to update the commit description after pulling this from some midstream tree of yours ;-)
Please update the commit description.
Quoted 10 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm64/boot/dts/mediatek/mt8167.dtsi +0
-0
arch/arm64/boot/dts/mediatek/mt8167.dtsi apmixedsys: apmixedsys@10018000 { · line 51
Quoted 4 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +1
-0@@ -48,6 +48,13 @@ apmixedsys: apmixedsys@10018000 { #clock-cells = <1>; }; + watchdog@10007000 {
All devicetree nodes must be ordered by mmio start (when they have one, or by name when they are not addressable).
In this case, the watchdog node goes *after* the scpsys node, and before imgsys.
Cheers,
Angelo
Quoted 9 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +6
-0+ compatible = "mediatek,mt8167-wdt"; + reg = <0 0x10007000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + scpsys: syscon@10006000 { compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>;
Re: [PATCH 3/7] watchdog: mediatek: Add support for mt8167 TOPRGU/WDT
In reply to Luca Leonardo ScorciaIl 11/02/26 20:03, Luca Leonardo Scorcia ha scritto:
Quoted 13 lines
Add support for the Top Reset Generation Unit/Watchdog Timer found on mt8167.
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+)drivers/watchdog/mtk_wdt.c +0
-0
drivers/watchdog/mtk_wdt.c line 16
Quoted 4 lines
drivers/watchdog/mtk_wdt.c +1
-0@@ -13,6 +13,7 @@#include <dt-bindings/reset/mediatek,mt6735-wdt.h> #include <dt-bindings/reset/mediatek,mt6795-resets.h> #include <dt-bindings/reset/mt7986-resets.h> +#include <dt-bindings/reset/mt8167-resets.h>
After changing the filename of that header, you'll obviously have to change it here and everywhere else - so with that name changed:
Quoted 22 lines
drivers/watchdog/mtk_wdt.c +5
-0#include <dt-bindings/reset/mt8183-resets.h> #include <dt-bindings/reset/mt8186-resets.h> #include <dt-bindings/reset/mt8188-resets.h> @@ -105,6 +106,10 @@ static const struct mtk_wdt_data mt7988_data = { .has_swsysrst_en = true, }; +static const struct mtk_wdt_data mt8167_data = { + .toprgu_sw_rst_num =MT8167_TOPRGU_SW_RST_NUM , +}; +static const struct mtk_wdt_data mt8183_data = { .toprgu_sw_rst_num =MT8183_TOPRGU_SW_RST_NUM , };@@ -498,6 +503,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data }, + { .compatible = "mediatek,mt8167-wdt", .data = &mt8167_data }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
AngeloGioacchino Del Regno
maintainerRe: [PATCH 6/7] arm64: dts: mt8167: Add the mmsys reset bit to reset dsi
In reply to Luca Leonardo ScorciaIl 11/02/26 20:03, Luca Leonardo Scorcia ha scritto:
Quoted 13 lines
DSI hardware reset is needed to prevent different settings between the bootloader and the kernel.
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +++ 1 file changed, 3 insertions(+)arch/arm64/boot/dts/mediatek/mt8167.dtsi +0
-0
arch/arm64/boot/dts/mediatek/mt8167.dtsi line 11
Quoted 4 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +1
-0@@ -8,6 +8,7 @@ #include <dt-bindings/clock/mt8167-clk.h> #include <dt-bindings/memory/mt8167-larb-port.h> #include <dt-bindings/power/mt8167-power.h> +#include <dt-bindings/reset/mt8167-resets.h>
Change header name.
Cheers,
Angelo
Quoted 19 lines
arch/arm64/boot/dts/mediatek/mt8167.dtsi +2
-0#include "mt8167-pinfunc.h"@@ -189,6 +190,7 @@ dsi: dsi@14012000 { <&mmsys CLK_MM_DSI_DIGITAL>, <&mipi_tx>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8167_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx>; phy-names = "dphy"; status = "disabled";@@ -295,6 +297,7 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; smi_common: smi@14017000 {
AngeloGioacchino Del Regno
maintainerRe: [PATCH 7/7] arm64: dts: mt8167: Add additional mmsys reset bits
In reply to Luca Leonardo ScorciaIl 11/02/26 20:03, Luca Leonardo Scorcia ha scritto:
Quoted 3 lines
Some extra mmsys reset bits are defined in the Lenovo Smart Clock kernel sources - file
cmdq_mdp.c
Hah, just noticed that this patch actually adds the same resets as the ones in my hints at patch 2.
In any case, since you're adding the MMSYS resets in patch [2/7], having two patches doesn't make any sense.
Leaving the fact that this patch has the wrong title ... but well anyway, just squash this one with [2/7] and send one patch adding all of the mmsys resets at once.
Cheers,
Angelo
Quoted 25 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- include/dt-bindings/reset/mt8167-resets.h | 9 +++++++++ 1 file changed, 9 insertions(+)include/dt-bindings/reset/mt8167-resets.h +9
-0@@ -33,6 +33,15 @@#define MT8167_TOPRGU_SW_RST_NUM 15/* MMSYS resets */ +#define MT8167_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT8167_MMSYS_SW0_RST_B_SMI_LARB 1 +#define MT8167_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT8167_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ0 4 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ1 5 +#define MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0 6 +#define MT8167_MMSYS_SW0_RST_B_MDP_WDMA 7 +#define MT8167_MMSYS_SW0_RST_B_MDP_WROT0 8#define MT8167_MMSYS_SW0_RST_B_DISP_DSI0 22#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8167 */
AngeloGioacchino Del Regno
maintainerRe: [PATCH 6/7] arm64: dts: mt8167: Add the mmsys reset bit to reset dsi
In reply to Luca Leonardo ScorciaIl 12/02/26 09:01, Luca Leonardo Scorcia ha scritto:
Quoted 6 lines
I apologize for the mistake, I did not notice that the dsi node is not present upstream yet, so this specific patch won't apply. Any comments are appreciated though!
I will send a separate patch to add the display nodes to the dts and the required compatibles to the bindings.
Initially, I didn't notice either.
P.S.: resets goes after phy (alphabetical order)
Cheers
Quoted 44 lines
Il giorno mer 11 feb 2026 alle ore 20:06 Luca Leonardo Scorcia <[email protected]> ha scritto:
Quoted 40 lines
DSI hardware reset is needed to prevent different settings between the bootloader and the kernel.
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +++ 1 file changed, 3 insertions(+)arch/arm64/boot/dts/mediatek/mt8167.dtsi +3
-1@@ -8,6 +8,7 @@ #include <dt-bindings/clock/mt8167-clk.h> #include <dt-bindings/memory/mt8167-larb-port.h> #include <dt-bindings/power/mt8167-power.h> +#include <dt-bindings/reset/mt8167-resets.h> #include "mt8167-pinfunc.h"@@ -189,6 +190,7 @@ dsi: dsi@14012000 { <&mmsys CLK_MM_DSI_DIGITAL>, <&mipi_tx>; clock-names = "engine", "digital", "hs"; + resets = <&mmsys MT8167_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx>; phy-names = "dphy"; status = "disabled";@@ -295,6 +297,7 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; smi_common: smi@14017000 { --2.43.0
Re: [PATCH 2/7] dt-bindings: mediatek: Add reset controller constants for mt8167
In reply to Luca Leonardo ScorciaQuoted 2 lines · Luca Leonardo Scorcia
This file comes from the Lenovo Smart Clock kernel sources.
Where is the actual binding? Why is this separate file?
Quoted 3 lines
Signed-off-by Luca Leonardo Scorcia <[email protected]>--- include/dt-bindings/reset/mt8167-resets.h | 38 +++++++++++++++++++++++
Filename matching compatible,
Quoted 11 lines
1 file changed, 38 insertions(+) create mode 100644 include/dt-bindings/reset/mt8167-resets.hinclude/dt-bindings/reset/mt8167-resets.h new file +2
-0@@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/*
include/dt-bindings/reset/mt8167-resets.h line 12
Quoted 10 lines
include/dt-bindings/reset/mt8167-resets.h new file +10
-0+* Copyright (c) 2015 MediaTek Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details.
Drop boiler plate. It is not even correct - conflicts SPDX which leads to another point - you need copyright owners agreement to relicense the code.
Just write new one, instead of sending us 2015 old code.
Quoted 14 lines
include/dt-bindings/reset/mt8167-resets.h new file +14
-0+*/ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8167 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8167 + +/* TOPRGU resets */ +#define MT8167_TOPRGU_DDRPHY_FLASH_RST 0/* reset ddrphy and flash pad macro */ +#define MT8167_TOPRGU_AUD_PAD_RST 1/* Write 1 to reset audio_tdm_in_pad,audio_tdm_pad,audio_fifo */ +#define MT8167_TOPRGU_MM_RST 2/* Write 1 to reset MMSYS */ +#define MT8167_TOPRGU_MFG_RST 3/* Write 1 to reset MFG */ +#define MT8167_TOPRGU_MDSYS_RST 4/* Write 1 to reset INFRA_AO */ +#define MT8167_TOPRGU_CONN_RST 5/* Write 1 to reset CONNSYS WDT reset */ +#define MT8167_TOPRGU_PAD2CAM_DIG_MIPI_RX_RST 6/* Write 1 to reset MM and its related pad macro(DPI,MIPI_CFG,MIPI_TX) */ +#define MT8167_TOPRGU_DIG_MIPI_TX_RST 7/* Write 1 to reset digi_mipi_tx */
include/dt-bindings/reset/mt8167-resets.h line 36
Quoted 10 lines
include/dt-bindings/reset/mt8167-resets.h new file +10
-0+#define MT8167_TOPRGU_SPI_PAD_MACRO_RST 8/* Write 1 to reset SPI_PAD_MACRO */ +#define MT8167_TOPRGU_APMIXED_RST 10/* Write 1 to reset APMIXEDSYS */ +#define MT8167_TOPRGU_VDEC_RST 11/* Write 1 to reset VDEC module */ +#define MT8167_TOPRGU_CONN_MCU_RST 12/* Write 1 to reset CONNSYS */ +#define MT8167_TOPRGU_EFUSE_RST 13/* Write 1 to reset efuse */ +#define MT8167_TOPRGU_PWRAP_SPICTL_RST 14/* Write 1 to reset pwrap_spictl module */ +#define MT8167_TOPRGU_SW_RST_NUM 15 + +/* MMSYS resets */ +#define MT8167_MMSYS_SW0_RST_B_DISP_DSI0 22
Nope, It's 16. IDs increment by 1.
Best regards,
Krzysztof
Re: [PATCH 7/7] arm64: dts: mt8167: Add additional mmsys reset bits
In reply to Luca Leonardo ScorciaQuoted 15 lines · Luca Leonardo Scorcia
Some extra mmsys reset bits are defined in the Lenovo Smart Clock kernel sources - file
cmdq_mdp.cSigned-off-by Luca Leonardo Scorcia <[email protected]>--- include/dt-bindings/reset/mt8167-resets.h | 9 +++++++++ 1 file changed, 9 insertions(+)include/dt-bindings/reset/mt8167-resets.h +0
-0@@ -33,6 +33,15 @@#define MT8167_TOPRGU_SW_RST_NUM 15
include/dt-bindings/reset/mt8167-resets.h line 44
Quoted 10 lines
include/dt-bindings/reset/mt8167-resets.h +9
-0/* MMSYS resets */ +#define MT8167_MMSYS_SW0_RST_B_SMI_COMMON 0 +#define MT8167_MMSYS_SW0_RST_B_SMI_LARB 1 +#define MT8167_MMSYS_SW0_RST_B_CAM_MDP 2 +#define MT8167_MMSYS_SW0_RST_B_MDP_RDMA0 3 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ0 4 +#define MT8167_MMSYS_SW0_RST_B_MDP_RSZ1 5 +#define MT8167_MMSYS_SW0_RST_B_MDP_TDSHP0 6 +#define MT8167_MMSYS_SW0_RST_B_MDP_WDMA 7 +#define MT8167_MMSYS_SW0_RST_B_MDP_WROT0 8
? You just added this file in other commit. Don't add half-baked bindings/code, but complete at once.
Best regards,
Krzysztof